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A hard macro created with fpga editor is saved in a .nmc file. It can be saved in a .ncd design file. I first thought of having this .ncd back in ISE to create a post PAR model, but how? Maybe Modelsim can take others file format as inputs? Thanks for helpArticle: 93176
"john" <john.wo54@gmail.com> schrieb im Newsbeitrag news:ee93082.-1@webx.sUN8CHnE... >A hard macro created with fpga editor is saved in a .nmc file. > > It can be saved in a .ncd design file. > nmc is actually a special ncd file with different extension > I first thought of having this .ncd back in ISE to create a post PAR > model, but how? > you must create an desing that uses the NMC and do past par simulation > Maybe Modelsim can take others file format as inputs? > no, not the NMC > Thanks for help AnttiArticle: 93177
Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!! Thank a lot, AlastairArticle: 93178
Hi, Xilinx iMPACT is not detecting my parallel cable III when I am trying to download projects to the board. My board is Spartan-3. I am using Windows XP and My ISE Version is 6.3 Please tell me what do i do? The error messages are: ----------- Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. Cable connection failed. Cable connection failed. Cable connection failed. Cable connection failed. Cable connection failed. ----------- Thanks in advance. Regards, Prateek SinghalArticle: 93179
"al99999" <alastairlynch@gmail.com> schrieb im Newsbeitrag news:1134651034.610713.142150@f14g2000cwb.googlegroups.com... > Hi, > > I was wondering if anybody had designed a vhdl sram controller for the > Digilent Memory Expansion board that is designed for the spartan 3 > starter kit. It is just two ISSI IS61LV5128AL sram chips. I have > tried writing a controller but cant seem to get it to work!! > > Thank a lot, > > Alastair > SRAM doesnt need an controller, just connect it to whatever you want, if you did it right and the hardware is ok it will work. for EDK just add an EMC IP core to the SoC and setup the port connection in the ucf file, thats should be it. AnttiArticle: 93180
HHIS... another one, maybe no more complicated, but fpga_editor keeps closing every few minutes... How to deal with the clock? Unable to route, and each clock input I have linked is a external pin. Is that normal behavior? With the reset, I have the same kind of problem: unable to route from an external pin input...Article: 93181
"john" <john.wo54@gmail.com> schrieb im Newsbeitrag news:ee93082.1@webx.sUN8CHnE... > HHIS... > > another one, maybe no more complicated, but fpga_editor keeps closing > every few minutes... > > How to deal with the clock? Unable to route, and each clock input I have > linked is a external pin. Is that normal behavior? > > With the reset, I have the same kind of problem: unable to route from an > external pin input... fpga_editor really likes to speed close itself, seen the same thing check last serive pack, + tactical patches on xilinx website, and get a lot patience... AnttiArticle: 93182
Hi, I am using a Xilinx Virtex Pro P20 FPGA.The system clock (155M) is comes out of a DCM FX which is phase locked to input 19 M. Everything works fine till 75 degree temperature. But as the temperature crosses 75 degree I see my logic behaving badly. I clearly suspect the DCM because at 80 degree centrigrade the system clock (155M) stops coming out of DCM. It is always low. The virtex pro data sheet says the maximum temperature range to be 85-90 degree centrigrade.Is there is solution to this. There is good heat sink on the FPGA. Has anyone seen this problem before ? Logic utilization is around 65 %. --DebashishArticle: 93183
I smell a homework assignment.Article: 93184
Hi! I'm using the ISE 7.1 but I hope to be useful to you. We I have the same problem, I start iMPACT and setup manually the cable configuration. Choose the menu Output --> Cable Setup... and check manually the configuration mode, the port and etc.. I also save the configuration.Article: 93185
Thanks, I'm not using EDK, only ISE, so I need a simple controller for the CE, OE and WE pins and to put the data and address on the correct buses at the right times.Article: 93186
I'm using ISE 7.1 and, we I have problem like you, I check manually the cable configuration in iMPACT. Start iMPACT, choose the menu Output -> Cable Setup... and check correctly the Communication Mode, Port, Cable Location... and try again! Then I also save the configuration to prevent to do the same manual configuration again!!Article: 93187
"al99999" <alastairlynch@gmail.com> schrieb im Newsbeitrag news:1134655074.184301.148800@g49g2000cwa.googlegroups.com... > Thanks, I'm not using EDK, only ISE, so I need a simple controller for > the CE, OE and WE pins and to put the data and address on the correct > buses at the right times. > that is just plain wires, if you have some circuitry that the SRAM can be connected. if you have trouble then just use VIO in chipscope, connected the SRAM to VIO pins and check the that the sram is really working properly, then go ahead and check your desing AnttiArticle: 93188
Here is a RAM tester for the S3 kit: http://www.derepas.com/fabrice/hard/ It'll probably help you. LeonArticle: 93189
debashish.hota@gmail.com wrote: > Hi, > > I am using a Xilinx Virtex Pro P20 FPGA.The system clock (155M) is > comes out of a DCM FX which is phase locked to input 19 M. Everything > works fine till 75 degree temperature. But as the temperature crosses > 75 degree I see my logic behaving badly. I clearly suspect the DCM > because at 80 degree centrigrade the system clock (155M) stops coming > out of DCM. It is always low. > > The virtex pro data sheet says the maximum temperature range to be > 85-90 degree centrigrade.Is there is solution to this. There is good > heat sink on the FPGA. Has anyone seen this problem before ? Logic > utilization is around 65 %. > > --Debashish The temperature range is for die temperature usually. How and where are you measuring the temperature? With internal logic running at 155MHz (at least the clock section) a 10-15C die temperature rise is not unusual (for the internal sections, power dissipation is generally directly proportional to toggle rates). Alternaltively (and I admit to not having looked closely at the data sheet), the temperature may be for ambient, but one has to be very careful - the power dissipation ratings get derated above a certain temperature, which may be 70C, but is more commonly device dependent. When a manufacturer states their device will work in ambient temperatures of (for instance) 85C, they mean 'work at ambient temperatures of 85C with this [you have to work it out] maximum power dissipation. The ultimate issue is always die temperature. Cheers PeteSArticle: 93190
I have the impression as you have mentioned, that the hardware protection would be vulnerable to these kind of modifications at that level, changing the BRAM code to something else. Wouldnt it be that XAPP780 provides some kind of hardware check that is done in order to verify for the sanity of the software. Like calculating the checksum. This should be done in hardware though.... I really think that there isnt any ideal solution to that problem and sooner or later, the design would be broken. I was thinking to enclose it in a box, but now, someone told me that some ppl can go up to EM radiation patterns detection. Guys, is this a myth or reality? JA henk wrote: > As the appnote says: It is vulnerable to bitstream attack. The method > uses a Picoblaze to do the final go/nogo check (amongst others). Just > modify the bitstream with an other blockram contents (DATA2MEM), even > by trial and error, and you can overrule the whole mechanism. By > replacing the BlockRAM with distributed ROM could help here. > Regards, > Henk van Kampen > Mediatronix.com > > Austin Lesea wrote: > > http://www.xilinx.com/bvdocs/appnotes/xapp780.pdf > > > > Austin > > > > Thomas Stanka wrote: > > > > > Why Ngc? > > > And is it necessary to stay on S3? Maybe you should think about Flash > > > based Fpgas (Actel, Lattice,..). > > > > > > bye Thomas > > >Article: 93191
Thanks, trying to use VIO in chipscope with the code below and getting
the following error:
ERROR:Xst:2091 Different types for port <async_in> on entity and
component for <vio>.
Any ideas?
Thanks
entity vio_top is
Port(
control: in std_logic_vector(35 downto 0);
async_in: in std_logic_vector(7 downto 0)
);
end vio_top;
architecture structure of vio_top is
-------------------------------------------------------------------
--
-- VIO core component declaration
--
-------------------------------------------------------------------
component vio
port
(
control : in std_logic_vector(35 downto 0);
async_in : in std_logic_vector(7 downto 0)
);
end component;
begin
-------------------------------------------------------------------
--
-- VIO core instance
--
-------------------------------------------------------------------
i_vio : vio
port map
(
control => control,
async_in => async_in
);
end structure;
Article: 93192Hi John, Thank you for your advice to look at the Knuth's volume 3. I have the book and will look at the paget 212. Do you use 'mirror' algorithm to handle the side image pixels? Does 'mirror' algorithm do the following way: Original frame of image: row0, row1, ... row 1023 Mirrored frame of image: row1, row0, row1, ... row1023, row 1022 Same things are done with column. WengArticle: 93193
kl31n wrote:
> That's what I did, but I don't have access to Xilinx cores internals to
> really see what's going on and what I could do to fix the problem. The
> behavioural model always works like expected, the Post-Translate instead
> cannot work correctly with data entereing with a period smaller than 260n.
Maybe that's just the way it is.
You could open a case with Xilinx
or use a different core
or write your own code.
-- Mike Treseler
Article: 93194Hi community, I got a problem you might be able to assist me in solving. I downloaded several HSPICE models for the Xilinx Virtex-II Pro FPGAs from the Xilinx homepage. They are stored in a format I don't know: *.inc. The included readme-file says that all models are encrypted and must be used in Synopsys HSPICE. All I got is a free PSPICE version running that supports file formats like *.opj, *.dsn, *.sch, *.olb, *.lib, *.vhd, *.txt. I already generated several schematics with PSPICE which I want to test in combination with the Xilinx models. Unfortunately it looks like that is not possible at all. Has anyone of you made similar experiences or has a hint how to solve that incompatibility problem? Any help is highly appreciated. Regards, Melanie NasicArticle: 93195
David, Our latest Virtex 4 is 600% less likely to be upset by soft errors. http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_v4rse or http://tinyurl.com/clzqh As well, its total dose resistance has also increased (improved). Your intuition is incorrect: the more advanced technologies are improving their ability to withstand the effects of cosmic rays, and radiation. There may have been intermediate products that were designed poorly (by other manufacturers), but that is no reason to avoid the latest technology when it is properly executed (by everyone else). AustinArticle: 93196
On Thu, 15 Dec 2005 18:34:48 +0100, "Melanie Nasic"
<quinn_the_esquimo@freenet.de> wrote:
>Hi community,
>
>I got a problem you might be able to assist me in solving. I downloaded
>several HSPICE models for the Xilinx Virtex-II Pro FPGAs from the Xilinx
>homepage. They are stored in a format I don't know: *.inc. The included
>readme-file says that all models are encrypted and must be used in Synopsys
>HSPICE. All I got is a free PSPICE version running that supports file
>formats like *.opj, *.dsn, *.sch, *.olb, *.lib, *.vhd, *.txt. I already
>generated several schematics with PSPICE which I want to test in combination
>with the Xilinx models. Unfortunately it looks like that is not possible at
>all. Has anyone of you made similar experiences or has a hint how to solve
>that incompatibility problem? Any help is highly appreciated.
>
>Regards, Melanie Nasic
>
Welcome to the wonderful world of HSpice dominating the simulator
world... because management equates high price with high performance
;-)
While PSpice CAN read some encrypted models, I _believe_ it can't read
HSpice versions.
Charlie Edmondson ??
Melanie, I suspect that you're a student, so you have no leverage. If
you're at a company simply have your purchasing department declare
Xilinx as "Do not purchase".
I did that once to Motorola... gets their attention real quick ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Article: 93197Dave, If you are concerned about "reliability", then I would assume you are concerned about gate oxide lifetime, hot carrier injection (HCI), negative temperature bias instability (NBTI), electromigration (EM), and so on. All of these are detailed in our process qualifications which ensure that every device we sell meets the generally accepted commercial (and industrial) lifetimes of better than 20 years. In fact the latest 90nm triple oxide reliability results are as good, if not better, that the previous technology nodes. http://www.xilinx.com/bvdocs/userguides/ug116.pdf (see page 20) AustinArticle: 93198
Debashish, All Xilinx specifications are based on die temperature (junction temperature). As long as the junction is below the specified temperature (85C for commercial, 100C for industrial), all specifications are met. It sounds like your junction temperature is much higher than what you think it is. How much power is your part dissipating? What sort of heatsink is on it? What is the airflow over the part (heatsink)? Have you predicted the junction temperature from the above information (and what is the predicted value)? AustinArticle: 93199
Hi, Unfortunately, I can't even do that manually. My port (LPT1) doesn't come in the list of the ports. The list is empty in fact. Any ideas what could be wrong? Any checklists for me to double check?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z