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thanks,can i have a look at your document or source files?Article: 96501
Anonymous wrote: > Thanks for all the feedback recently on linux on Xilinx. I think I > understand it now: > > PPC linux is faster and technically superior but monte vista has a strangle > hold on the source and tools which discourages anybody from using it. > > uClinux/microblaze is slower but more open source and easier to get a system > up and running with. MontaVista offers commercial support and prebuilt toolchain/environment which mean they will help you bring up _your_ custom platform. But all the sources / toolchain are available for download. As a matter of fact, I saw a patch to add the Virtex4-FX cpu IDs to the kernel.org's kernel recently. On the other hand, a _whole_ lot more people work on microblaze than on Virtex4-FX and those who work on Virtex4-FX may prefer to pay for commercial support to get their application up & running faster. Which is probably why you find more on-line doc on uBlaze than Virtex 4 FX. That said, for a experienced kernel developper, one is not harder than the other ... SylvainArticle: 96502
Thank you all for the info....now this is what I want and what I have done.....Plz help me further I am doing only a project titled "RTL coding of DDR2 SDRAM memory controller" so what I want is only a verilog code which is synthesizable. I myself tried writing some of the modules but the problem is that I am new to verilog and there is a time constraint, so I need some help in the coding part. Moreover I downloaded the MIG tool V1.4 from the xilinx site..... http://www.xilinx.com/support/software/memory/protected/ise_71i_mig14.zip now I have the ISE8.1i webpack version and when I install MIG1.4 it doesn't work (or i donno how to work with it...plz help) Can someone tell me how to work with it...in a detailed way...I mean if I double click the tool its not opening!!! How shud I go abt it.....can someone plz read the code available in the link I provided( u have to download it...itz some 24mb zip file) and tell me whether it is correct and synthesizable...when I imported all these files directly into Mentor Graphics FPGA Advantage tool it shows a lot of errors....what changes shud I do...plz read the code and help me asap....thanq all a lot.Article: 96503
Hi, Has anybody ever designed anything to decode and display GPS NMEA data coming out in ascii form from a UART? Any ideas of where to start or how to go about decoding comma delimted ascii strings? Thanks, AlArticle: 96504
al99999 wrote: > Hi, > > Has anybody ever designed anything to decode and display GPS NMEA data > coming out in ascii form from a UART? > > Any ideas of where to start or how to go about decoding comma delimted > ascii strings? I think this would typically be done using a processor rather than an FPGA. Even a small, single chip MCU would have enough horsepower to handle the 4800 bps data rate and control a display. But of course that depends on the interface to the display. Generating a VGA signal would take a bit more than sending a serial bit map to a small LCD. If you really want to do this in an FPGA you would need to construct state diagrams for the logic that will parse the input stream and generate binary numbers from the characters. This will take some significant logic since it involves muliplications. Then you need to design a circuit that will draw lines in your display based on your current and last position, again, this can be a lot of logic to figure out. I think if I was told to do this in an FPGA, I would construct a CPU in the FPGA (or use one of the CPUs provided by the FPGA vendors) and find C code to draw the display. The rest of the work is easy in software.Article: 96505
Thanks Peter, So if I understand you correctly, the DCR is to be used mainly in PPC designs and not in MB. I have another question if possible - I would like to know if it is possible to debug a MB design with both sw debug (MDM) and hw debug (chipscope), the reason for this question is that both of this modules are working via JTAG. Thanks in advance, Mordehay.Article: 96506
My application requires a USB2.0 slave mode. Does anyone know which tree is best for USB gadgets: PPC/Linux or MB/uClinux? Thanks, ClarkArticle: 96507
I have a couple of spread sheets from FPGA vendors for power calculation. They "protect" the spread sheet, I assume so that you don't mess with the calculations. I find that my anti-virus software can't open the document and reports an error every time it is scanned. I tried to disable the protection, but that option is not available on these files. Anyone know what is going on? Even if I need a password to unprotect the workbook, I can't find where to enter it. I guess I can just delete it to get it off the PC and download it fresh each time I need to use it, or maybe put it on a CD. But I am tired of going through a list of dozens of errors on protected files each time I run my AVS and I am getting rid of them one way or the other.Article: 96508
My first response would be to ask the FPGA vendor. Explain your problem and see what they suggest. It's in their interest to make this as easy as possible for you, and I've always found them helpful. Alternatively, you can probably convince your AV software to ignore files you place in certain subdirectories or some such. It depends on whose AV software you use. Bill ---------------------------- rickman wrote: > I have a couple of spread sheets from FPGA vendors for power > calculation. They "protect" the spread sheet, I assume so that you > don't mess with the calculations. I find that my anti-virus software > can't open the document and reports an error every time it is scanned. > I tried to disable the protection, but that option is not available on > these files. Anyone know what is going on? Even if I need a password > to unprotect the workbook, I can't find where to enter it. > > I guess I can just delete it to get it off the PC and download it fresh > each time I need to use it, or maybe put it on a CD. But I am tired of > going through a list of dozens of errors on protected files each time I > run my AVS and I am getting rid of them one way or the other. >Article: 96509
Hi Clark, Anonymous wrote: > Also, I was wondering if anybody has a multi-processor flavor of Linux > running on xilinx? Seems like an obvious next step since there are multiple > PPC cores in the chips. As other posters have said, V4FX/V2Pro PPC and MicroBlaze both lack cache coherency support. So, it's not really feasible to implement SMP Linux on either architecture. We've sketched out plans for a MicroBlaze cache snoop unit and protocol, but ultimately you still require some software-intrusive stuff - slow slow slow. It's also not very scaleable, a 4-way cache snoop architecture would quickly consume logic gates that would be better used doing real work. SMP is a compromise. It makes sense if you have to optimise an architecture across as many use-cases as possible - ie fixed silicon. In FPGA-land, we should be designing custom architectures to suit each application, and SMP will rarely be the best architecture for any particular problem. That said, I do have an implementation of dual mb-uclinux kernels running from the same memory. It works fine, you can use either shared memory or FSL or even ethernet to communicate between them. However, it's not SMP. Regards, JohnArticle: 96510
Clark, Anonymous wrote: > My application requires a USB2.0 slave mode. Does anyone know which tree is > best for USB gadgets: PPC/Linux or MB/uClinux? I suggest we take this off-list before we are lynched for being permanently off-topic. Can you email me directly, or discuss on the microblaze-uclinux list? http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ Thanks, JohnArticle: 96511
have a look at reference designs on the altera and xilinx websites. And for interfaces take a look at opencores.org, theres a ton of interface (PCI, USB) and micro-processor designs available, many of which are written in VHDLArticle: 96512
On 3 Feb 2006 15:59:38 -0800, "Peter Alfke" <peter@xilinx.com> wrote: >Paul, don't get offended. You were the one who stoked the fire. >The OP asked for a technical comparison between FPGAs and ASICs. And I >interpret that as a comparison between customer-specific designs >(Leaving out microprocessors, and ASSP, since they serve a different >market requirement. If uPs and/or ASSPs fill the need, anybody would be >a fool for not using them.) >So the comparison here is only between two different ways to achieve a >custom hardware solution: FPGAs or ASICs. >The relative merits have been described ad nauseam. My point was that >you cannot discuss this without mentioning economics. And economics >more and more favor FPGAs, as Moore's Law drives all of us to smaller >geometries. This may sound like Xilinx Marketing, but it also happens >to be a fact. >The ASIC market is still big, but relative to FPGAs it is shrinking, >especially when you look at the number of new design starts. >There will alays be a market for both methods, but the old religion of >"Real men do ASICs" is fading, similar to Jerry Sanders' "Real men have >fabs". We have all got smarter with time. >Peter Alfke I agree (apart from the assertion that I 'stoked the fire'!). The OP appeared, from what I could see, to be asking how the relative technical merit scaled with generations. I replied that it was my opinion that the relative technical difference probably stays constant over generations. You introduced the economics, and I made the point that there were 2 sides to the economics story, and I gave some real figures to back that up. But yes, I was irritated by Austin's claim that ASIC starts are decreasing by a factor of 10 a year. It's not even possible given that there were only 10K starts a year maybe 7 years ago. It's also of debatable relevance, given that a start at 90 or 110nm is going to contain a lot more logic than a start at 130 or 180. PaulArticle: 96513
Xilinx has a report on Infiniband cable characterisation with RocketIO MGTs (v2.0, May 10th 2004, http://direct.xilinx.com/bvdocs/reports/ug043.pdf). Unfortunately, this is vague on BER measurements. The intro states that BERs are presented for various configurations but, in the event, the data summary table only states whether or not the configuration "meets RX requirements", which presumably means whether or not the BER is <= 1E-12. The tests also used PRBS 2E7 rather than 8B/10B encoding, so the BERs wouldn't be correct for Infiniband anyway, or for Aurora. Anyone happen to know of any better figures, or a later report? Or have any experience of measuring BERs on RocketIO over these cables? Thanks - PaulArticle: 96514
me_2003@walla.co.il wrote: > I have another question if possible - I would like to know if it is > possible to debug a MB design with both sw debug (MDM) and hw debug > (chipscope), the reason for this question is that both of this modules > are working via JTAG. Yes, they can work together. You can even do tricky stuff like connect the chipscope and MDM triggers together, so that you get a bus trace of the previous NN cycles prior to a CPU trap, that sort of thing. Unfortunately it doesn't work in V4 ES (early silicon) parts due to a silicon bug. I assume it was fixed for production silicon. JohnArticle: 96515
"urielka" <uriel.katz@gmail.com> writes: > from what i understand,doing a full ogg decoder on chip is madness so Yep, and Andrey is definately a mad scientist: http://www.linuxdevices.com/articles/AT3888835064.html - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 96516
Hi everyone, I have recently purchased a XC3S200 based board with 256KB Flash, 256KB platform flash and 32KB SRAM. So out of my interests I figured I would design a simple SoC as a learning excercise. I have designed a VGA framebuffer which does 640x480 (but uses pixel doubling so 320x240x2-bit). A complete framebuffer is ~19KB. At this point I decided I would have to read the framebuffer at a line at a time. A scanline in this mode would need 80 bytes of memory. Naturally I decided to infer a block RAM with 8-bit data width (well 9-bit, but I am not using parity). The problem though is that when the Block RAM is 8-bits, you get almost 2KB of space!! So that means I am wasting more than 90% of the space!! I was looking into using a 8 128x1 distributed RAM and wire them in a way to extend the data word to 8-bits. I am not certain how much of my logic resources this would eat up. I am fairly new to the FPGA's so I'm not certain if these are the best methods to buffer such a small amount of memory. What would you do if you were in my situation? Regards -IsaacArticle: 96517
I just would like to also add that the unit is working perfectly. I just would like some suggestions. ThanksArticle: 96518
I don't know about spartan 3. On a spartan 2, you can hook 8 blocks of RAMB4_S1 in parallel, giving you a total of 1KByte.Article: 96519
For making fine modifications to PCBs, which of Tefzel and Kynar insulated wired are best to use ? JonnArticle: 96520
HI, I am not sure i understand your architecture, can you please describe exactly what you are doing with a single BRAM? Pending further information, One this is for sure, you dont want to use D-RAM as long as you can avoid it. I may have completely misunderstood, but why can't you address the entire block RAM (with its 2K depth) using a combination of the horizontal and vertical address lines? so suppose you keep your current form factor for the BRAM block (8-bit wide). then you could have the high 7 horizontal pixel counter bits hooked up to the low seven address lines of the BRAM, giving you 128 addressable locations. Each location contains 4 pixels, which you can then multiplex on to the output with addtional logic (as i presume u are already doing). the high 4 address lines to the BRAM block can be connected to the low 4 bits of the vertical line counter. Thus, you would be using 16*80 = 1280 bytes of the total available 2K. You would still have 4 additional vertical counter bits remaining, which means you will have to use a total of 16 BRAM blocks. This also implies you will need a 16to1 8-bit wide MUX. Hope this helps.Article: 96521
Thanks Symon
It was good study meterials
Dear Franceso and Allan
Thanks,
You are right I needed a general Bock diagram of what all is
implemented in an FPGA and what all are interfaced to it on the board,
for studying for all STM's, pls provide me what you know about it .
What current industry is thinking and what is the latest solution to
implement the design as of Market and more about it and which is
valuable to me and fellow students to study. To prepare for the project
in academic at the such companies and be Competitive.
thanks
Satish K
Article: 96522Did anyone notice that hprep on linux ( CPLD flow ) is crashing (with service pack installed ) ? Or is this an issue just on Debian ? Thanks!Article: 96523
You could also put the file into any password protected archive, like ZIP. This way antivirus will see the archive, but will not scan its contents. WBR, Vladimir Mirgorodsky Bill Martin wrote: > My first response would be to ask the FPGA vendor. Explain your problem and see > what they suggest. It's in their interest to make this as easy as possible for > you, and I've always found them helpful. > > Alternatively, you can probably convince your AV software to ignore files you > place in certain subdirectories or some such. It depends on whose AV software > you use. > > Bill > ---------------------------- > rickman wrote: > > I have a couple of spread sheets from FPGA vendors for power > > calculation. They "protect" the spread sheet, I assume so that you > > don't mess with the calculations. I find that my anti-virus software > > can't open the document and reports an error every time it is scanned. > > I tried to disable the protection, but that option is not available on > > these files. Anyone know what is going on? Even if I need a password > > to unprotect the workbook, I can't find where to enter it. > > > > I guess I can just delete it to get it off the PC and download it fresh > > each time I need to use it, or maybe put it on a CD. But I am tired of > > going through a list of dozens of errors on protected files each time I > > run my AVS and I am getting rid of them one way or the other. > >Article: 96524
Anand, I think it is a terrible idea to start with DDR2 SDRAM controller if you have absolutely NO idea of how to use a HDL and the corresponding tools in a correct manner. First try to learn the HDL and the use of your tools. Rgds Andr=E9 > now I have the ISE8.1i webpack version and when I install MIG1.4 it > doesn't work (or i donno how to work with it...plz help) Can someone > tell me how to work with it...in a detailed way...I mean if I double > click the tool its not opening!!! How shud I go abt it.....can someone > plz read the code available in the link I provided( u have to download > it...itz some 24mb zip file) and tell me whether it is correct and > synthesizable...when I imported all these files directly into Mentor > Graphics FPGA Advantage tool it shows a lot of errors....what changes > shud I do...plz read the code and help me asap....thanq all a lot.
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Compare FPGA features and resources
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