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thank poul. ill download it. CMOSArticle: 96476
>Once one has done the compiling, >How fast can one program >an fpga anyway? Look in the data sheets. There will be a max clock rate and a table of number-of-config bits vs chip size. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 96477
Have a look at products like dialite, fs2, or vendor specific ones like chipscope and signaltap. http://www.temento.com/solutions/fpga.php http://www.fs2.com/ Hans www.ht-lab.com <shawnn@gmail.com> wrote in message news:1139009089.347862.164300@f14g2000cwb.googlegroups.com... > Hello, > > When doing development using microcontrollers/processors, you can often > find ICEs and ICDs that allow you to set breakpoints. You can stop the > code in execution and view the contents of registers, state of input > pins, etc. > > Suppose I want to do something similar with an FPGA-based design. What > are my options? I know I can output internal signals to output pins and > sniff them using a logic analyzer, but I'm hoping there is a more > elegant solution. I'd like to stop everything at some point and view > all inputs, outputs, registers, etc. > > Can someone point me in the right direction? >Article: 96478
Austin Lesea schrieb: > What I claim is that the force of the third added wire will be less than > that of the first wire, and the force of the first on the same side of > the glass wire will be somewhat less, but will not be 1/2. In fact with > the BART rail spacing, it would be 2/3 and 1/3. > > At DC. > > Guess what? Current creates a field, a field tells current how to flow. > > I think Faraday discovered this? ;-) This is really funny. A very basic effect of physics is "forgotten" by the highly trained specialists. Maybe I can jump in and help to enlight the non-belivers. The effect in question is called Lorentz-Force (Lorentz-Kraft in german). Its the effect that makes every electrical engine spin. Just have a look at those small toy motors, they use a permanent magnet to greate a static magnetic field and a DC current inside the rotator loop. OK, the current gets reversed by the commutator every fraction of a revolution, but this is not the point. Another example is the good old CRT TV set. A (quasi) magnetic field is used to deflect a electron beam (moving charge carriers). > This works by the way for superconducting wires, resistance has no part > in this. R does not appear in the equations to show this is true. > > QED for this "Gendanken" Experiment... "Gedanken"Experiment. Just a small typo. (yeahh, germans are known to be real pedantic ;-) Regards Falk P.S. To be onest I never thought of the magnetics stuff before when looking at the GND/VCC balls on a package. Interesting!Article: 96479
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> writes: > I've used quartus_pgm in a makefile successfully some time (and perhaps > some Quartus version) ago, but now I get a strange error: > > Info: Command: quartus_pgm -c ByteBlasterMV -m JTAG -o p;quartus/cycconf/cyc_con > f_init.pof I usually have a chain description file, i.e. quartus_pgm -c ByteBlasterMV -m JTAG chain.cdf The cdf files describes order of the jtag chain as well as the name and location of the pof file. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 96480
Not so much on rates of change, but for a 90nm point comparison, see the paper by Kuon and Rose about to be published in FPGA next month. There the comparison is standard-cell ASIC to Stratix-II or similar. Caleb Leak wrote: > I have been searching around online for a good comparison of the growth > rates of FPGAs and ASICs (specifically gate size, power consumption per > gate, cost per gate, and clock speed). I am trying to show the gap > narrowing between these two over time. I have yet to find any good > information, and even raw data would be very useful. Is there any such > comparison anyone has seen? If not, does anyone know of a good place to > find this type of raw data and historical pricing for FPGAs? I seem to > be completely unable to find ASIC equivalent gate ratings for most FPGAs. > > Thanks in advance.Article: 96481
hi, i've completed a introdutory vhdl book and done several small scale designs using vhdl for FPGA implementations. However the book i read does not cover any advanced topics or designs that we meet in real life, like micro-controllers, USB interfaces, etc. i' ve serched the net for books and tutorials which will discuss advanced topics and having a moderately complex case study at the end, but found non for vhdl. If anyone knows any such books, tutorials or other resources, please let me know. CMOSArticle: 96482
HI, I have just installed Xilinx 7.1 SP3 and trying to compile the libraries in a subdirectory under the install PATH in a way I have done for a number of years but now it fails using vcs 2005.06(7.2). I chose to compile to /tmp/ it works fine but not to my preferd directory! ERROR:CAEInterfaces:570 - COMPXLIB[file]: unable to create directory '/opt/eda/xilinx/ise/alliance_7.1isp4/verilog/vcsmx_2005.06/unisims_ver' What is the limitation in compxlib using VCS? MTI 5.6 works fine to the same PATH! /michaelArticle: 96483
Thanks for all the feedback recently on linux on Xilinx. I think I understand it now: PPC linux is faster and technically superior but monte vista has a strangle hold on the source and tools which discourages anybody from using it. uClinux/microblaze is slower but more open source and easier to get a system up and running with. Is that about the picture? Also, I was wondering if anybody has a multi-processor flavor of Linux running on xilinx? Seems like an obvious next step since there are multiple PPC cores in the chips. Thanks, ClarkArticle: 96484
Falk, Thank you. I only had three years of high school German, so forgive my spelling. Just think how surprised those Westinghouse Engineers were when they had 10,000 trains....and 6 empty train blocks light up on the 10 meter by 3 meter map display! Austin Falk Brunner wrote: > Austin Lesea schrieb: > >> What I claim is that the force of the third added wire will be less >> than that of the first wire, and the force of the first on the same >> side of the glass wire will be somewhat less, but will not be 1/2. In >> fact with the BART rail spacing, it would be 2/3 and 1/3. >> >> At DC. >> >> Guess what? Current creates a field, a field tells current how to flow. >> >> I think Faraday discovered this? > > > ;-) This is really funny. A very basic effect of physics is "forgotten" > by the highly trained specialists. > > Maybe I can jump in and help to enlight the non-belivers. The effect in > question is called Lorentz-Force (Lorentz-Kraft in german). Its the > effect that makes every electrical engine spin. Just have a look at > those small toy motors, they use a permanent magnet to greate a static > magnetic field and a DC current inside the rotator loop. OK, the current > gets reversed by the commutator every fraction of a revolution, but this > is not the point. Another example is the good old CRT TV set. A (quasi) > magnetic field is used to deflect a electron beam (moving charge carriers). > >> This works by the way for superconducting wires, resistance has no >> part in this. R does not appear in the equations to show this is true. >> >> QED for this "Gendanken" Experiment... > > > "Gedanken"Experiment. Just a small typo. (yeahh, germans are known to be > real pedantic ;-) > > Regards > Falk > > P.S. To be onest I never thought of the magnetics stuff before when > looking at the GND/VCC balls on a package. Interesting!Article: 96485
austin schrieb: > Just think how surprised those Westinghouse Engineers were when they had > 10,000 trains....and 6 empty train blocks light up on the 10 meter by 3 > meter map display! Hmm, but why didn't they have a small prototype for testing? Or did they think this is sooo trivial no need for testing? Regards FalkArticle: 96486
Hi Roger, The docs do not explain too well what they mean by "local target memory". If you notice, the Master PLB IPIF comes with a slave attachment. Thus, the master IPIF is not a pure master. Contrast this with the PPC Master interfaces (Instr-PLB and Data-PLB) which are pure masters. Because of the slave attachment, the master-slave IPIF has an address range like any PLB slave: you set this address range in the MHS file instantiation. The key insight (which the docs do not explain) is that the IP2IPBus_Addr should always be set to some address within the addressable range of the slave attachment. Thus, if your user_logic has internal memory, the idea is that you use the IP2IPBus_Addr address range for this "local target memory". If your master pcore does not need to have any internal memory, you can hard code IP2IPBus_Addr to a static address within the slave attachment address range. This was the case for me (I was designing a PLB to PLB bridge, so my data came from one side of the bridge and I pushed it out to the other side). Another thing to note is that the slave attachment is also used for master transactions. Master Read: Issue read request, the read data returns through the slave attachment, appearing like a write-request to your "local target memory". (Imagine after you receive the return data, you have to write it to your "local target memory"). Master Write: 1st read from "local target memory" using slave attachment, then you can push the data on the IP2Bus data bus with the external target address.... If found this scheme confusing, especially since not much documentation real estate was dedicated to explaining it. NN agou wrote: > Hi, Nju > > Thank you for the reply. I don't know whether your code in last thread > derived from the user_logic.v generated by the Create and Import > Peripheral Wizard. And I am currently reading this code. > > In this code, there is a port named IP2IP_Addr, and in your last > thread, you first connected with the IP2Bus_Addr and then you revised > it to your local target memory. What I am not clear is that how to > instantiate the "local target memory" which is compatible to the IPIF? > Should I instantiate a PLB_BRAM block? > > Besides the above, in the user_logic.v, there is a 16 bytes flattened > registers(mst_reg(0:15) in the sample code) which are used for the > control from the software side. Meanwhile, in the sample code, each of > this address is assigned a specific address, e.g. IP2IP register is > located at C_BASEADDR+0x104. And I saw another reference design in > which software could read these register directly by the address. So I > just wonder whether I could allocate some other registers in my > hardware and specify the address myself. If it could be done, then for > writing, I could just store my data in these registers first and then > assign these registers' addresses to the IP2IP_Addr. But I don't find > anything on how to specify the registers' addresses in the sample code. > > So now, could you tell me how did you do to use a "local target > memory"? And do you know whether the second method would work or not? > > Thank you > Roger > > Nju Njoroge wrote: > > Hello, > > > > Please refer to this thread: > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/4373c26ee4c38328/aebfcf5e6f06f52c?lnk=st&q=PLB+Master&rnum=1&hl=en#aebfcf5e6f06f52c > > > > (Google "PLB Master" in Googe Groups and this will be your first hit). > > > > Properly using the IP2IP_Addr in the IPIF is what allowed my master to > > work properly. > > > > Good luck, > > > > NN > > > > > > agou wrote: > > > Hi, group > > > > > > I generated a IPIC interface by the Create and Import Peripheral Wizard > > > > > > to access PLB_DDR blockon the PLB bus. > > > > > > I chose the DMA, user logic Master Support mode. And then try to > > > develop my own logic based on the generated files. Here, I have one > > > problem: > > > > > > To write to an address on PLB bus, I need to provide two addresses: > > > IP2IP_Addr which stores the source data and IP2Bus_Addr > > > to which writes the data. Do I need to instantiate a BRAM in the FPGA > > > to provide the source address? > > > > > > What I am not clear is whether the BRAM is compatible the IPIC logic. > > > Or do I have to instantiate another PLB_Bram and then hook it up to the > > > PLB? Are there any other simple method? > > > > > > Thank you for the help. > > > RogerArticle: 96487
MontaVista does not have a strangle hold on the anymore than RedHat has a strangle hold on x86 Linux. MontaVista developed the OS adapters for the Xilinx peripheral cores and has submitted them to the appropriate open source repositories. They do provide commercial support and extra benefits by working with them. However, everything required is available open source. Earlier this week I yet again compiled Linux from scratch for the Virtex2Pro PowerPC405 from the excellent Howto hosted by UIUC: http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html The same is largely true for Microblaze uclinux. It is an open source project and Petalogix (http://www.petalogix.com/) is available to provide commercial support/services should that be of interest to you. In terms of performance, the only difference between Linux and uClinux is the former requires a Memory Management Unit (MMU) while the latter does not. For all intents and purposes that doesn't affect performance directly. The lack of memory protection support can in theory make software more difficult to debug but there are tons of products shipping using uClinux so plenty of folks have figured this out. In contemporary FPGAs, a hard-core processor such as the PowerPC405 will operate at 300MHz whereas a soft-core processor such as Microblaze operates around 100MHz. However, overall application performance is dependent on many factors besides just the processor core operating frequency. As for multi-processor designs, neither the PowerPC405 nor Microblaze directly supports cache coherency. However, there are many ways to partition a problem so that more than one processor contributes to the application solution. These issues are discussed here periodically. A final note. The exciting part about processors in FPGAs is that so many design parameters are flexible--both the hardware and software architectures can be adapted to the problem at hand. Many more opportunities but also much more rope to hang yourself with. Exciting times! Paul Anonymous wrote: > > Thanks for all the feedback recently on linux on Xilinx. I think I > understand it now: > > PPC linux is faster and technically superior but monte vista has a strangle > hold on the source and tools which discourages anybody from using it. > > uClinux/microblaze is slower but more open source and easier to get a system > up and running with. > > Is that about the picture? > > Also, I was wondering if anybody has a multi-processor flavor of Linux > running on xilinx? Seems like an obvious next step since there are multiple > PPC cores in the chips. > > Thanks, > ClarkArticle: 96488
Anonymous wrote: > Thanks for all the feedback recently on linux on Xilinx. I think I > understand it now: > > PPC linux is faster and technically superior but monte vista has a strangle > hold on the source and tools which discourages anybody from using it. > MontaVista provides some sort of design environment, and paid support. You can also get a free Linux distribution and design environment from Denx: http://www.denx.de/en/News/WebHome This was what came with an Avnet V2Pro development card that we bought, and it has worked fine for us. It was the 2.4 version of the kernel. Is there anyone here that has used MontaVista that would care to comment on their experiences? I spent about an hour on the phone with someone from MontaVista a while back trying to figure out what they are offering. I asked to have someone technical call me. The person that did call could tell me the price of everything, but could not tell me much more than they provided a design environment and paid support by the "incident". She had no idea what qualified as an incident. I asked if they would be providing Linux drivers for the Xilinx cores in the EDK. She did not know, but said she would call me back with an answer. I never heard from them again. I wrote my own drivers for what I needed, and did not bother trying to call them again. > uClinux/microblaze is slower but more open source and easier to get a system > up and running with. > > Is that about the picture? > > Also, I was wondering if anybody has a multi-processor flavor of Linux > running on xilinx? Seems like an obvious next step since there are multiple > PPC cores in the chips. While there are two PPCs in many of the Xilinx chips, they do not support cache coherency which you really want if you want to run an SMP single image kernel. You could run two independent copies of the kernel. > > Thanks, > ClarkArticle: 96489
Falk, I have no idea. But they (Westinghouse) had never done a modern urban transit system before, and had been given the contract. Politics, pork, etc. There were many at the time who said that this was yet another example of incompetence, and that the contract should have been given to the experts in electric traction urban transit...who were Germans (at that time). All in all, the system was well engineered, and was very modern (when introduced). IBM did the payment system, which was so easy to clone that students bragged about how they could make copies of their $20 cards with nothing but a flat iron. (Do not know if this was true or not). Presumably that got fixed ... Austin Falk Brunner wrote: > austin schrieb: > >> Just think how surprised those Westinghouse Engineers were when they >> had 10,000 trains....and 6 empty train blocks light up on the 10 meter >> by 3 meter map display! > > > Hmm, but why didn't they have a small prototype for testing? Or did they > think this is sooo trivial no need for testing? > > Regards > FalkArticle: 96490
I have an upcoming project requiring a programmable logic device with three unique requirements: 1) It needs to have a simple, nonproprietary logical architecture, similar to the "sum of products" architecture of many PALs 2) It needs to have a well-documented architecture, i.e., I need to know how each configuration bit relates to the device's internal configuration. 3) It needs to be high density (as high as possible given hard requirements 1 and 2, above). I'm not an expert on current product offerings, but it seems to me that today's high-density programmable devices (CPLDs and FPGAs) have become more complex & proprietary. Given my needs, am I stuck with the PLA devices of the 80s? Any help will be greatly appreciated. -ChessArticle: 96491
chessaurus@yahoo.com wrote: > 1) It needs to have a simple, nonproprietary logical architecture, > similar to the "sum of products" architecture of many PALs > 2) It needs to have a well-documented architecture, i.e., I need to > know how each configuration bit relates to the device's internal > configuration. The bit streams for XC4000 and Virtex devices are pretty well documented, as you can extract most of the info from the configuration guide of Virtex parts, the fpga editor, and JHDL's router/bitstream tools. There are a few otherwise hidden bits, but outside what you would normally program from what I understand. Readback/column programming gets you 98%??? > 3) It needs to be high density (as high as possible given hard > requirements 1 and 2, above). > > I'm not an expert on current product offerings, but it seems to me that > today's high-density programmable devices (CPLDs and FPGAs) have become > more complex & proprietary. Given my needs, am I stuck with the PLA > devices of the 80s? Depends just how much you are willing to be flexible on 2.Article: 96492
Hello everybody, sorry in advance if my question will sound stupid but basically I am starting a course in embedded systems co-design where we use DK3 to create programs in Handle-c and a simulator to test our code before upload it on the real xilinx board (Virtex II-XC2V300). As I don't have access to the lab 24/7 I would like to practice at home. Here comes the question: can I program in Handle-C and then use the student Xilinx Foundation to test my programs in simulation? I read some stuff on Xilinx web site but I don't want to waste my time downloading and installing it (and learning it) if it doesn't do what I need. Thanks a lot in advance and apologies if I am writing to the wrong NG. Any comment/advice/suggestion would be greatly appreciated. Thanks, Davide.Article: 96493
>Anyone who can point to a clear and simple explanation, please do. >When I first mentioned this to our packaging group, the lead engineer >said "oh yes, I see this in the EM simulations..." I think the key idea is that the return current is flowing close to the forward current. Or rather closer to parts of the conductor than it is to the rest. What's the current distribution in the center conductor of a coax carrying DC? Where are the balls carrying the "return" current relative to the central clump of ground balls?? >So, I know I am not imagining it! Simulations never get the wrong answer? [I used to be reasonably good at this stuff, but that was a long long time ago. This feels like a good question for PHD orals.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 96494
> PPC linux is faster and technically superior but monte vista has a strangle > hold on the source and tools which discourages anybody from using it. Not true. Support for Xilinx PowerPC is available in the linuxppc open source repository which is picked up by various distributions. MontaVista Linux is one such distribution. > uClinux/microblaze is slower but more open source and easier to get a system > up and running with. Bringing up a Linux system is always a complex task. Linux for MicroBlaze and PowerPC are open source. > Also, I was wondering if anybody has a multi-processor flavor of Linux > running on xilinx? Seems like an obvious next step since there are multiple > PPC cores in the chips. The PPCs in Virtex-II Pro and Virtex-4 do not support bus snooping to maintain cache coherency. With that you cannot run the two PowerPCs as an SMP system. However, you can run an instance of Linux per PowerPC. - PeterArticle: 96495
DCR bus stands for device control register bus. It can be used to control devices. In EDK the PLB2OPB, the OPB2PLB and the INTC have a DCR interface (the INTC is also available as an OPB version). The PPC has a native DCR master interface while the MB does not have a DCR interface at all, however, there is an OPB2DCR bridge. The DCR is a very simple bus. It is not high-performance and really intended to be used for control operations. To learn more about the DCR interface have a look at the PowerPC Processor Block Manual [pg. 100ff] (http://www.xilinx.com/bvdocs/userguides/ug018.pdf). - Peter me_2003@walla.co.il wrote: > Hi , > I would realy appreciate it if someone could explain the possible usage > of a DCR bus (with PPC or MB). > Thanks in advance, Mordehay. >Article: 96496
Thanks for the link. I guess I'm more frustrated with Xilinx then I am with monta vista. I was expecting to go to www.xilinx.com/linux and see: 1. standard PPC architecture 2. link to toolsuite 3. link to source 4. schematics for standard design (fpga + flash + ram + enet phy, etc.) 5. tutorial on getting a system up and going You'd think a company interested in selling chips would make the process a lot easier for us newbies. Instead I've bounced around quite a bit frequently running in to the dead end at the monte vista site which has little if any info for non-subscribers. I'm wondering why I'm forced to go through a meet and greet with MV just to get a platform up that I can evaluate my application on. Are they selling timeshares or something!? The fact that there are vendors selling boards with V4 FX parts that are choosing to run MB/ucLinux instead of use the PPC core that they already paid for gives me pause and should cause Xilinx to shake their head too. At any rate, I appreciate the feedback. -Clark "Paul Hartke" <phartke@Stanford.EDU> wrote in message news:43E4E8DB.BFD61D2B@Stanford.EDU... > MontaVista does not have a strangle hold on the anymore than RedHat has > a strangle hold on x86 Linux. MontaVista developed the OS adapters for > the Xilinx peripheral cores and has submitted them to the appropriate > open source repositories. They do provide commercial support and extra > benefits by working with them. However, everything required is > available open source. > Earlier this week I yet again compiled Linux from scratch for the > Virtex2Pro PowerPC405 from the excellent Howto hosted by UIUC: > http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html > > The same is largely true for Microblaze uclinux. It is an open source > project and Petalogix (http://www.petalogix.com/) is available to > provide commercial support/services should that be of interest to you. > > In terms of performance, the only difference between Linux and uClinux > is the former requires a Memory Management Unit (MMU) while the latter > does not. For all intents and purposes that doesn't affect performance > directly. The lack of memory protection support can in theory make > software more difficult to debug but there are tons of products shipping > using uClinux so plenty of folks have figured this out. > > In contemporary FPGAs, a hard-core processor such as the PowerPC405 will > operate at 300MHz whereas a soft-core processor such as Microblaze > operates around 100MHz. However, overall application performance is > dependent on many factors besides just the processor core operating > frequency. > > As for multi-processor designs, neither the PowerPC405 nor Microblaze > directly supports cache coherency. However, there are many ways to > partition a problem so that more than one processor contributes to the > application solution. These issues are discussed here periodically. > > A final note. The exciting part about processors in FPGAs is that so > many design parameters are flexible--both the hardware and software > architectures can be adapted to the problem at hand. Many more > opportunities but also much more rope to hang yourself with. > > Exciting times! > > Paul > > Anonymous wrote: > > > > Thanks for all the feedback recently on linux on Xilinx. I think I > > understand it now: > > > > PPC linux is faster and technically superior but monte vista has a strangle > > hold on the source and tools which discourages anybody from using it. > > > > uClinux/microblaze is slower but more open source and easier to get a system > > up and running with. > > > > Is that about the picture? > > > > Also, I was wondering if anybody has a multi-processor flavor of Linux > > running on xilinx? Seems like an obvious next step since there are multiple > > PPC cores in the chips. > > > > Thanks, > > ClarkArticle: 96497
"CMOS" <manusha@millenniumit.com> wrote in message news:1139068845.604136.314600@g14g2000cwa.googlegroups.com... > hi, > i've completed a introdutory vhdl book and done several small scale > designs using vhdl for FPGA implementations. However the book i read > does not cover any advanced topics or designs that we meet in real > life, like micro-controllers, USB interfaces, etc. i' ve serched the > net for books and tutorials which will discuss advanced topics and > having a moderately complex case study at the end, but found non for > vhdl. If anyone knows any such books, tutorials or other resources, > please let me know. http://www.ashenden.com.au/designers-guide/DG-intro-lectures.html or, even better, buy his book. http://www.amazon.com/gp/product/1558606742/sr=1-2/qid=1139103691/ref=sr_1_2/103-7172689-9857457?%5Fencoding=UTF8Article: 96498
>What's the current distribution in the center conductor of a coax >carrying DC? Argh/blush. Stupid example. How about: What's the currrent distribution in a pair of tightly coupled striplines? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 96499
you might want to look at the DVD.. its 800Megs as one file... 1.8G as individuals Simon "CMOS" <manusha@millenniumit.com> wrote in message news:1139044107.726226.138800@g47g2000cwa.googlegroups.com... > thank poul. ill download it. > > CMOS >
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