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Peter, there is no evidence of _dynamic_ reconfiguration in this article. Actually, Smith-Waterman algorithm is not a good candidate for demonstrating dynamicity, because the query sequence occupies only an edge of the accelerator array => programming a long register is ok. Changing algorithm coefficients would benefit from DPR, but actually, biologists never do so! Xilinx paper "Gene Matching using JBits" in FPL 2002 was an implementation of the Needleman-Wunsch algorithm (simpler than S-W); it also uses a run-time query, and implementation is optimized for given coefficients, so it's not clearly taking advantage of DPR. Anyway JBits was demonstrated to work. Stephane Peter Alfke wrote: > I recommend reading the article below: > > http://www.fpgajournal.com/articles_2006/20060207_cray.htm > > Apparently RC works... > Peter Alfke >Article: 97026
Of course it works. Self-Reconfiguration on Virtex2,Spartan2 and Spartan3 works fine. I said that Partial Reconfiguration on Virtex4 using ISE doesnt work. I dont know if using PlanAhead it works. We have made many experiments and using Virtex4 during the final assembly phase it fails due to problem with the disabled DCMs, and many global logic that appears during this phase. That global logic goes from TIE elements to CE inputs of the registers inside the slices. For smal designs we have route it manually and we've got some simple design of PR on Virtex4, but for larger designs is imposible to route that logic. Appart for it there are a problem about using Virtex4 block rams in modular design, I reported it, and it supposed to be solved in a IP update for ISE8.1. I havent test it yet. Yesterday, when I downloaded SP2 for ISE8.1 I tested again the designs and the problem of the global logic and unconnected DCMs havent disappear. Regards Javier On 14 Feb 2006 14:16:00 -0800, "Peter Alfke" <peter@xilinx.com> wrote: >I recommend reading the article below: > >http://www.fpgajournal.com/articles_2006/20060207_cray.htm > >Apparently RC works... >Peter AlfkeArticle: 97027
Hi Al, If you check an European distributor for Altera like EBV (www.ebv.com) you should see that they do have a fair amount of lead-free inventory of Altera. So it inculdes their distis. I think this campain is more for the European market since we need to go over to the RoHS side now. In US only the companies that sell products into Europe has to comply with their products (AFAIK). That might explain Arrows lack of stocking in NA.=20 Just my 0,02=80 FredrikArticle: 97028
Jim Granville <no.spam@designtools.co.nz> wrote in news:43f2b6aa@clear.net.nz: > rickman wrote: >> Al Clark wrote: >> >>>DigiKey, another Altera distributor shows only lead versions and >>>treats lead free versions as Non-Stock items. My guess is that they >>>didn't want to sell both types and wanted to make sure that they had >>>gotten rid of all the lead inventory first. >> >> >> I don't think you are going to see leaded parts going away just >> because the EU requires lead free parts. I work for a company that >> gets a lot of attention from distributors and manufacturers and they >> have assured us that lead based parts will be around for a long time. >> There are just too many designs that are not going to change even if >> they can't be sold in the EU. > > Can you clarify which ones actually _have_ lead, as opposed to > not being RoHS complaint ( which includes other materials too ). > > ie I thought that gull wing packages like TQFP and PQFP, as > well as MLF packages, resistors, caps, > are already tin or nickel plated, and have been for a while ? You have to check with each mfr. Some have new numbers, some don't. Altera places an 'N" at the end of their part number. Lots of passives, QFPs, etc use lead solder plating > > BGA packages, I CAN understand, as they use Solder Balls, > so those you would want to match to your paste... Its important to pay attention to BGAs because the balls are solder. If they are lead free, they melt at a higher temperature than lead-tin solder. > > -jg > > -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 97029
Try using the Help menu, select index, search for back annotation. Hope that gets you going in the right direction. Alan Sophie Liu wrote: > Hi, Dears: > > I am using QuartusII now. I am not clear to back-annotate. What is > back_annotate? and what's the use of back-annotate? > > Thank you! > > > > Jude >Article: 97030
Matt Clement wrote: > Hey guys > I am actually using a CPLD by Altera Max 7000S. I have an output pin that > needs to either be tristated or drive a '1' at all times other than when > driving data on the bus. I have used the second option up until now and it > has some weird glitches since it is inside a process and until it gets the > first clock it doesnt go to '1'. Maybe if there was a way to initialize it > to a '1' at power up. I think the best way is to do a tristate, but I have > very little resources left. in can go in HI-Z and you use an external pull-up (or internal if available) on this pin. Aurash > > Matt > > > "Aurelian Lazarut" <aurash@xilinx.com> wrote in message > news:dst25d$g1t2@cliff.xsj.xilinx.com... > >>radarman wrote: >> >>>Check the data sheet for your part. Some parts will allow for true >>>*internal* tri-states, while others do not. For example, a Xilinx 4000 >>>series FPGA will do true internal tristates, while neither the Virtex >>>nor Spartan series FPGA will not. >> >>Actually they do have. >>Spartan2 spartan2E virtex and virtexE they all have BUFT (or TBUFS) >> >>parts without BUFTs: virtex2/pro virtex4 spartan3/3E >> >>Aurash >> >>>For parts that do support it, you will need to add a line like this >>>(for VHDL): >>> >>>TSTATE_BUS <= My_bits when Enable = '1' else (others => 'Z'); >>> >>>Note, you can still do this even in later families, but the compiler >>>will turn it into a mux - so be careful. If you aren't aware of that >>>behavior, you can be surprised on large designs with low LUT margins. >>> >>>Note, I have seen some IP cores that use an 'OR'ed bus structure to >>>solve this problem. With an OR type bus, you just drive zeros when not >>>enabled: >>> >>>arcitecture rtl of sample is >>> >>> -- To simplify the OR logic, make these the same width. Your >>>compiler/synthesizer should optimize away bits you don't need - while >>>still making the correct connections. Just load the registers you DON'T >>>need with a constant value. >>> signal My_Bus_1_d, My_Bus_1_q : std_logic_vector( BUS_WIDTH_MINUS_1 >>>downto 0 ); >>> signal My_Bus_2_d, My_Bus_2_q : std_logic_vector( BUS_WIDTH_MINUS_1 >>>downto 0 ); >>> >>> -- Don't worry too much about the My_Data_n busses - you can pad the >>>bus when you feed it to My_Bus_n_d; >>> signal My_Data_1 : std_logic_vector( 3 downto 0); >>> signal My_Data_2 : std_logic_vector( 15 downto 0); >>> >>>begin >>> >>>-- You need one of these per *readable* register/entity >>>My_Bus_1_d <= My_Data_1 when Enable_1 = '1' else (others => '0'); >>>My_Bus_2_d <= My_Data_2 when Enable_2 = '1' else (others => '0'); >>> >>>-- To keep your combinational logic path to a minimum, register each >>>"My_Bus". This isn't necessary, and does add an additional clock of >>>latency, but if your timing is marginal, this will help. >>> >>>S_Regs : process( Reset_n, Clock ) >>>begin >>> if( Reset_n = '0' )then >>> My_Bus_1_q <= (others => '0'); >>> My_Bus_2_q <= (others => '0'); >>> elsif( rising_edge(Clock) )then >>> My_Bus_1_q <= My_Bus_1_d; >>> My_Bus_2_q <= My_Bus_2_d; >>> end if; >>>end process; >>> >>>-- Then, you need _only_ one of these somewhere in the code to "mux" >>>the bus together. >>>for i in BUS_WIDTH_MINUS_1 to 0 loop >>> OR_BUS(i) <= My_Bus_1_q(i) or My_Bus_2_q(i); >>>end loop; >>> >>>end rtl >>> >>>This is fairly resource intensive, but it is fast, and explicit. To >>>improve performance, I would suggest registering My_Bus_n as shown - >>>unless your design has few readable registers - or you can tolerate the >>>long combinational paths. BTW - if you look closely, you will see that >>>this only handles the READ portion of your bus. Use a separate bus for >>>handling writes. Not only will this improve performance, since you >>>don't have to simulate bus turnaround, but you don't need any muxing at >>>all for a WRITE bus - just clock enables on the registers. Saves a lot >>>of grief in the long run. >>> >>>Good luck! >>> > > >Article: 97031
Hi All, Iam working on a MPEG project for which Iam using the ML403 board. Iam new to this platfrom. My question is: Do i need to have a linuxppc kernel on top of the hardware or can i use the gcc commands supported by EDK to build my application and build the final image without the underlying linuxppc kernel ? Kindly suggest. Thanks in advance. RameshArticle: 97032
Gentlemen, May I remind you that that the leadfree, RoHS and Green stuff started in Japan, not in Europe. Europe adopted to this Japanes initiative, and only the US seems to have problems. I think the problem is that US just waited to long to start investigating how to implement. Luc On Tue, 14 Feb 2006 19:53:25 GMT, Al Clark <dsp@danvillesignal.com> wrote: >"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in >news:45eg2iF6cp26U1@individual.net: > >>> Sometimes, I think that the Europeans think that all products are >>> like consumer items that have a product life of a few months or maybe >>> a year (like a PC or cell phone). >> >> >> Al, >> >> Please don't tarr us all with the European 'politician's brush, they >> just _don't_ think. >> >> A couple of weeks ago someone on sci.electronics.design (I think) >> posted a link to a presentation that quoted TI's figures, that a >> worldwide conversion to lead free packages would save about the same >> amount of lead as in TEN car batteries. >> >> The european parliament is a complete waste of time and a huge waste >> of money. >> >> >> Nial. >> >> >> > >Fair enough, We sell our products to many European companies, both small >and large. I sure many EU based companies are struggling with these same >issues.Article: 97033
I think I have sufficient knowledge in English, but still had troubles understanding what back-annotation is used for in Quartus II software. I have an assumption, that feature is designed to allow designer to compile certain piece of project the same way many times, even if you add some more functionality to the project. Let's say, you created a module with very tight margins on setup/hold timings, frequencies, etc. Adding more functionality will definitely change the layout of the whole chip and may affect your critical block timings. To protect your critical part of design you may create a back-annotation file, which will guide Quartus II about exact way how to layout the module to achieve the same performance during next builds. During my experiments I failed to get it work properly. Maybe I don't know how to read, or Quartus II help system omits some critical rules/restrictions. Don't understand the difference between this feature and LogicLock feature. For me, both are doing the same. To Alan Myler: always hate people, who respond your way to the questions in the news-group. If you don't have to say anything about the topic, just ignore the post. You don't have to respond in the group if you don't like the question, neither obligated offend original poster. With best regards, Vladimir S. MIrgorodsky Alan Myler wrote: > Try using the Help menu, select index, search for back annotation. > > Hope that gets you going in the right direction. > > Alan > > > Sophie Liu wrote: > > > Hi, Dears: > > > > I am using QuartusII now. I am not clear to back-annotate. What is > > back_annotate? and what's the use of back-annotate? > > > > Thank you! > > > > > > > > Jude > >Article: 97034
No need of linux ppc ... you can use the gcc alone but you have to understand that you can't use any of the services provided by the os or the glibc/uclibc ... nor can you use c++ probably (as the libstdc++ will undoubtly depends on the libc ...)Article: 97035
News from Embedded World News, Nurnberg 14.02.2006 Actel ===== Had no booth, but Actel-guy was moving around so I catched him. Actel Fusion FPGAs: Delayed for 6 months. Do not expect Fusion silicon samples or starterkit sooner! Dont beg, dont ask - all Fusion silicon available has been allocated. This was really sad for me as I did order and pay for Actel Fusion starterkit already last year. Altera ====== Stratix IIGX sample shipping: week12 (end of march) 65nm FPGAs will be announced in 2006 or in worst case "within 1 year from today" There was fractal-movie running on NIOS board with DMA coupled hardware accelerator. When I asked about the camera, then it was just a matter of selecting different application using touch-screen interface (KROS board plugged into Avalon slot) and the camera demo was running. I got a overshoulder bag with 12cm small ball inside, my 2 year old daughter Anna likes the ball a lot. Atmel ===== AVR32 Architecture was launched, they had a gpraphical demonstration with real AVR32 silicon chip, well it was marked with code name "Morgan" and there was no actual info about any AVR32 'orderable parts' only benchmark comparisons that seemed to prove that AVR32 ISA beats ARM at 50% on all accounts. STK525 starterkit (with AT90USB1286) was on display priced 200EUR is immediatly available. AT90USB1287 - real nice chip is also available that is distributors must accept orders as order entry from Atmel is open - so if your disti says AT90SUB1287 is not orderable then the disti has not up-to-date info. USBKEY Demo board costs 30USD and is based on AT90SUB1287 I did see it working at the booth - this board is not immediatly avaiable as there are 20 of them manufactured as of today (2 of them being at embedded) but it should be orderable and should be shipping shortly as well. Lattice ======= On my inquirey: "LatticeSC sample silicon is it available today?" the anser was yes. But asking that a few more times the anser changed to 2006 Q2, meaning that samples for SC25 may or may not be available immediatly. LatticeSC evaluation board (with SC25) is however defenetly available immediatly on a 'loaner' basis. Its a nice board with PCIe 8 channel edge connector and lots of SMAs. The question is SC25 suitable for 8 Lane PCIe did not got full answer, should be yes, but well no we dont have it tested and working in 8 lane configuration. The first chip available is SC25 in 378 package then SC25 in 484 and then if I am not mistaken SC80 Both LatticeSC and ECP2 devices are supporting multiply configuration loading from industry standard SPI serial flash. ECP2 pricing is 50% of ECP, so smallest ECP2 has an pricetag of 3 USD. Smallest members of ECP2 family are however last on the roadmap the first member to be available is the largest ECP2-70 with smallest ones following. Pricing rule: ECP2: 0.50$ per 1K LUT SC: 3.0 USD per 1K LUT Nec === World smallest microcontroller was presented with a demo on credit card sized PCB, the IC is in 1.9mm by 2.2mm Chip Scale BGA package those requires less PCB area then MicroChip SOT23 micro what was smallest micro so far. PLDA ==== Supreme technical knoweledge! Was really nice talk. They had PCIe demos for both Altera and Xilinx based boards. On my request they also did online live demo of working 8 lane PCIe solution using a Altera Stratix-II board with 2 PMC 4 lane PHYs. PLDA 8 lane solution has been integrated into customer products (also with 2 10GBe interfaces - using PMC phy and Altera FPGA). A new 8 Lane board with Genesys PHYs and Xilinx Virtex4-LX will be available in June and is targetted to pass PCIe compliane at plugfest in July. SiLabs ====== A girl handed me some invitation to "USB and Industrial Connectivity Seminar" At first I refused to take, it, but then asked what does it cost - 99EUR, well I still refused to take the leaflet and made a very pissef off face saying "I tried to purchase the Toolstick but wasnt able to get it". "Do you want one right now?" she asked me. "Yes". At the end she ended up taking it from the booth from behind the glass. And I did take the seminar ad as well, here are links to the seminars: http://www.azzurri.com/go/mcuseminar2006 http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/en/usbseminars.htm at azzuri link there is picture of what you get free of charge at the seminar I list the items here (as it not clear from picture) 1) Bag and some books 2) ToolStick (value 10.99 USD) 3) USB FM Radio (no purchase possible) 4) C8051F340 Development kit (value 99$ USD) 5) CP2201 Evalution Kit, no info ??? what is it? there will be refreshments served. Silica ====== They had 1 piece of Xilinx Spartan3e starterkit at the booth. It did blink some LED's. If Silica's stock is 1 piece it means that as of today they are not yet shipping. Well shipping should start any day form now I guess. Both my youngest have now a ass-sledge with Silica logo, hopefully there will be some snow around to check them out. Simple Solutions ================ 3 new Spartan3e based modules! All of them use parallel flash and multiboot feature. The 500e based modules are shipping now the 100e based module will be shipping very shortly. TI == 20 USD USB development tool for MSP430 Similar to SiLabs toolstick, but the 'target' module can be removed from the main part (TUSB3410 based) TQC === Spartan3-1500 based module with MicroBlaze uClinux and MicroWindows demo Vmetro ====== 8 Lane PCIe protocol analyzer was advertized with 1 Lane version available at the booth Xilinx ====== EDK 8.1SP1 has DDR2 support included and is targetted for release on FEB 20. For V4 MGT there was absolutly no commitment of anyavailability date at all. To have a rest I did sit down for a live presentation. To my left an old guy with all-white hair possible having a rest as well, to my right was I think not a visitor. That was the audience. "Who has used PPC?" the speaker asked me for intro, I pulled a DIP40 form factor board with Virtex-4FX12 (see www.hydraxc.com) from my pocket as answer :) The presentation was about 'how to gain Ghz performance with the V4 APU'. I think I learned it: 300MHz multiplied by 17 is 5.4 GHz! That was the claim of the speaker. For sure it got 2 heads turning, I looked at the old man to the left and it was "What !?" on his face. Oh well I wasnt so good at simple math at scool. After that EDK was claimed to support PicoBlaze, what is not true. And it was also claimed that PicoBlaze can only be programmed with Assembler what of course is also not true. After that a comparison was done for pricing Virtex4-FX: 35 USD 2.4GHz pentium CPU: >100USD as a clear win for Xilinx. Hum at what qty does V4FX silicon cost 35 USD? And what does a cheapest 2.4GHz pentium class CPU cost at the same volume? Well that is something I do not know the answers. After the presentation I looked around to see faces I know or products I dont know, but did not see any. Pitty. Antti Lukats PS my best gift item prize goes to perforce http://www.perforce.com/ for a real balsa-wood model air-plane ! now having Andre (my 4 years old sun) as a pride ownerArticle: 97036
That sounds like possible date. Yesterday I did see one Spartan3e starterkit board at Silica's boot at Embedded in Nurnberg. They only have that one board so will be shipping as soon as they get the boards. AnttiArticle: 97037
Dave Greenfield wrote: > I'll refrain from commenting on the environmental merit of lead-free > devices. > > I did a quick check of inventory on a representative distributor (Arrow > Electronics North America) web site. Most MAX 3000A and Cyclone devices > (picking 2 representative product families) have similar lead-times for > both leaded and lead-free (RoHS compliant) versions. Altera's minimum > order quantities are the same for both devices. We have put in place a > rigorous (though clearly not perfect) plan to facitate the transition > to lead-free product. This is severely complicated by the fact that not > all customers have interest in immediately converting all devices to > lead-free product, which generally has a different manufacturing flow. > As a result we need both leaded and lead-free ordering codes for most > devices and most of these lead-free ordering codes have been in place > for several quarters. > For most component packages, there should not be a problem with providing only lead-free versions - some manufacturers (TI, IIRC) have been doing that for years. BGA packages are a different matter, of course, as lead-free solder balls need higher temperatures. So I suppose it's more of a problem for a company like Altera than most manufacturers, since a higher proportion of your chips are BGA. Perhaps Intel's copper pillar packaging would be a good choice in the future? (Not that I know anything about it other than the name...) > You can find a complete listing of Altera's lead-free solutions at > http://www.altera.com/products/devices/leadfree/lead-free_index.html > > > Dave Greenfield > Altera Marketing > > >> Today I got this in Altera's email newsletter > >> Get RoHS Compliant with Altera FPGAs, CPLDs and Structured ASICs > > >> I have never seen a single 3000 series PLD available in leadfree that you >> could actually purchase for delivery from stock. I have been able to buy >> lead versions of most of this family without too much trouble. . . . >Article: 97038
Antti schrieb: > PS my best gift item prize goes to perforce > http://www.perforce.com/ > for a real balsa-wood model air-plane ! > now having Andre (my 4 years old sun) as a pride owner Your 4 years old s_u_n must be a bright kid, isn't it? SCNR ;-) Regards FalkArticle: 97039
ROTFL - I ended up looking with google for SCNR :) well, I hope Andre (will be 4 on 5 May this year) is bright, but its kinda hard to tell as he isnt talking so much, to the extent that makes us to worry already. 3 words sentences do come(in 2 languages), but thats about it. But he has its own view how to build things and has great joy in drawing and painting, and does teach his daddy how to make pann-cakes (this is no joke). As of that model airplane, well my wife helped me to get it together - the weights at the front fuselage had strip off glue for fixing (I assumed they are magnetic and can be used to adjust the balance what happened to be wrong assumption). Andre was just plaing with it afterwards and was close to be late into the kindergarten - the doors close there at 0900 sharp no exceptions. AnttiArticle: 97040
the problems with download are not so big issue if the download works at the end, but not fixing the bugs sure is ISE 8.1SP2 1 "Alt-GR" on keyboard fixed !!! NICE !!! 2 wrong hotkey - not fixed, ok I can live with it 3 http://bugs.xilant.com/view.php?id=14 not fixed! :( I just needed to make a real minor change to real simple PLD design, should take 1 minute to implement. but ISE 8.1SP2 project navigator just self terminates !! Oh, well lets wait for SP3 !!! AnttiArticle: 97041
Has anybody managed to use the MiG to generate a controller for the DDR SDRAM on the Xilinx ML401 board? The RAM (infineon) on the board is not one of the listed options (they are all micron). Thanks, AlastairArticle: 97042
Luc <bnl_rsm.lscc@telenet.be> wrote: >May I remind you that that the leadfree, RoHS and Green stuff started >in Japan, not in Europe. You may and I have heard the claim before, but when I look I find no evidence that is it true.Article: 97043
nospam wrote: > Luc <bnl_rsm.lscc@telenet.be> wrote: > >> May I remind you that that the leadfree, RoHS and Green stuff started >> in Japan, not in Europe. > > You may and I have heard the claim before, but when I look I find no > evidence that is it true. > As far as I understand it, Japan has had a number of restrictions such as lead-free (or at least, reduced lead), for many years. However, the restrictions are not as strict as the new EU directives. I couldn't give you any more details or pointers, however, nor can I remember where I read about it.Article: 97044
Antti wrote: > ROTFL - I ended up looking with google for SCNR :) > > well, I hope Andre (will be 4 on 5 May this year) is bright, but its > kinda hard to tell as he isnt talking so much, to the extent that makes > us to worry already. 3 words sentences do come(in 2 languages), but If he is being raised bilingually, it is perfectly normal to be a slow starter at speaking. The kid has to learn two different languages at the same time, and that takes a bit longer to sort out. If the two languages use very different sets of phononyms, it's even harder, as it also takes longer for the brain to train the ears. Another influence is if he is getting on with life fine without saying much, then there is less incentive to learn. It can all add up and make a great difference - my first kid was extremely fast to learn to speak, while our second was almost worryingly slow. > thats about it. But he has its own view how to build things and has > great joy in drawing and painting, and does teach his daddy how to make > pann-cakes (this is no joke). As of that model airplane, well my wife > helped me to get it together - the weights at the front fuselage had > strip off glue for fixing (I assumed they are magnetic and can be used > to adjust the balance what happened to be wrong assumption). Andre was > just plaing with it afterwards and was close to be late into the > kindergarten - the doors close there at 0900 sharp no exceptions. > > Antti >Article: 97045
Antti schrieb: > ROTFL - I ended up looking with google for SCNR :) > > well, I hope Andre (will be 4 on 5 May this year) is bright, but its > kinda hard to tell as he isnt talking so much, to the extent that makes > us to worry already. 3 words sentences do come(in 2 languages), but Look at his this way. Today, people (not only in TV) are talking (too) much, but they SAY often nothing at all. My parents said that I did not talk a word until the age of two, which worried my folks a little bit. But then, I spoke very clearly (they said). That said, you see a genius does'nt need too much words. ;-) > just plaing with it afterwards and was close to be late into the > kindergarten - the doors close there at 0900 sharp no exceptions. Yeah, since the kindertgarten is usully run be 100% women, its another proof that woman always want to educate (to drill ?) the kids, which is not bad at all, but sometimes annoying when they try to this with big kids (aka, grown up men, preferable husbands/boyfriends) ;-) Regards FalkArticle: 97046
"mattdykes" <mattdykes@gmail.com> wrote in message news:1139952217.717191.282060@z14g2000cwz.googlegroups.com... > Thanks, Dave. I'm a dumb arse. I'm finishing up a project for a > co-worker and didn't notice he was using every library know to man. > > Note to self: > Don't include ieee.std_logic_signed.all AND > ieee.std_logic_unsigned.all. > Guys, Just a FYI, if you Google for "vhdl math tricks of the trade", there's a great article by Jim Lewis all about the wonders of VHDL arithmetic. I use it all the time. The bottom line is to use numeric_std for all new designs. HTH, Syms.Article: 97047
Hey All, I am working on a relatively large design involving DSP on an FPGA. We use a Virtex4 LX60 and fill up about 50-75% of the LUTs and all of the DSP48s. Anyway, in the process of development I decided to switch my design over to Synplify Pro. I compile the DSP portion of my design which subsequently spits out an .edf file. I then try and include this in my EDK design, as we have the uBlaze running in there and need to use EDK (apparently). However, I get the "portability" error that seems prominent on many designs (as per the Xilinx support website). Basically, it will not accept a generic .edf file into the design unless it is generated using XST. Here are my questions: 1. Is it possible to compile the uBlaze outside of EDK? 2. I have talked to Synplicity about doing the above, but has anyone ever taken the troubleof compiling a uBlaze design and then shoving it into Synplify Pro? (This is Synplicity's solution, which may work, but will take a while, especially over multiple design iterations) 3. Does ISE have a simpler implementation of including all of these peripherals that EDK claims to be speciallized for? 4. Has anyone seen the portability error described above before when trying to include an outside .edf file? If anyone could help me out, and not point me to the Xilinx support line in the process, it would be helpful. Not that I don't like the support line, I just don't want to send all of my code to them (or you). Thanks for your help! ChrisArticle: 97048
1) you can compile uBlaze with non XST tools only if you have purchased the uBlaze source, there pricing doesnt appear on Xilinx website anymore, last time it was listed I think it was 19,000 USD so paying that you can compile with synplify 3) wrap your EDK as submodule and use in ISE main project where you also include your edif file, that might work 4) the portability 127 error is the root of evil. its and generic error what can have zillion of causes in almost always there is no fix AnttiArticle: 97049
Chris, Unfortunately I can't help you, I am just another confused EDK user. I was wondering if there is a more specialized user group/mailing list that would be primarily concentranting on EDK? The one on Xilinx site doesn't look too alive... /Mikhail "Chris Gammell" <Chris.Gammell@gmail.com> wrote in message news:1140016510.090345.209650@g47g2000cwa.googlegroups.com... > Hey All, > > I am working on a relatively large design involving DSP on an FPGA. We > use a Virtex4 LX60 and fill up about 50-75% of the LUTs and all of the > DSP48s. Anyway, in the process of development I decided to switch my > design over to Synplify Pro. I compile the DSP portion of my design > which subsequently spits out an .edf file. I then try and include this > in my EDK design, as we have the uBlaze running in there and need to > use EDK (apparently). However, I get the "portability" error that seems > prominent on many designs (as per the Xilinx support website). > Basically, it will not accept a generic .edf file into the design > unless it is generated using XST. Here are my questions: > > 1. Is it possible to compile the uBlaze outside of EDK? > > 2. I have talked to Synplicity about doing the above, but has anyone > ever taken the troubleof compiling a uBlaze design and then shoving it > into Synplify Pro? (This is Synplicity's solution, which may work, but > will take a while, especially over multiple design iterations) > > 3. Does ISE have a simpler implementation of including all of these > peripherals that EDK claims to be speciallized for? > > 4. Has anyone seen the portability error described above before when > trying to include an outside .edf file? > > If anyone could help me out, and not point me to the Xilinx support > line in the process, it would be helpful. Not that I don't like the > support line, I just don't want to send all of my code to them (or > you). > > Thanks for your help! > > Chris >
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