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You have two choice : - Keep the 1 line prefetch architecture and use Distributed RAM. 128x8 will take you 16 Slices but you then need a 4:1 mux to select between pixels - Continue with the block ram and fetch 8 lines at a time, then you can use the asymettric port width features of the BRAM to select between pixels.Article: 96526
Yes, a comparison of technical merit between generations is what I was looking for. I am trying to support (or help reject) the conjecture that as time goes on, FPGAs are becoming a more viable alternative to traditional ASICs. With this in mind, I'm trying to cover all aspects of what would make them a viable alternative or not--which seem to be size per gate, cost per gate (not including NRE), power usage per gate, and clock speed. I am trying to avoid market speculation. Comparing FPGAs and ASICs seems to be a hard comparison to make (even when just comparing current generation technology), especially as measurements such as "total gates" become more abstract. The best way to do this comparison seems to be benchmarking various designs implemented on ASICs and FPGAs. Creating such benchmarks myself is way beyond the scope of what I am doing, so I am left looking for someone else's report or data. Also, Kuon and Rose's paper seems to cover many of the things I was looking for. I appreciate all the input so far from everyone, and I am sorry for the late reply (I have been away most of the weekend). "Paul Johnson" <abuse@127.0.0.1> wrote in message news:1stcu19l55754b42diqsho4m98nspeisua@4ax.com... > On 3 Feb 2006 15:59:38 -0800, "Peter Alfke" <peter@xilinx.com> wrote: > >>Paul, don't get offended. You were the one who stoked the fire. >>The OP asked for a technical comparison between FPGAs and ASICs. And I >>interpret that as a comparison between customer-specific designs >>(Leaving out microprocessors, and ASSP, since they serve a different >>market requirement. If uPs and/or ASSPs fill the need, anybody would be >>a fool for not using them.) >>So the comparison here is only between two different ways to achieve a >>custom hardware solution: FPGAs or ASICs. >>The relative merits have been described ad nauseam. My point was that >>you cannot discuss this without mentioning economics. And economics >>more and more favor FPGAs, as Moore's Law drives all of us to smaller >>geometries. This may sound like Xilinx Marketing, but it also happens >>to be a fact. >>The ASIC market is still big, but relative to FPGAs it is shrinking, >>especially when you look at the number of new design starts. >>There will alays be a market for both methods, but the old religion of >>"Real men do ASICs" is fading, similar to Jerry Sanders' "Real men have >>fabs". We have all got smarter with time. >>Peter Alfke > > I agree (apart from the assertion that I 'stoked the fire'!). The OP > appeared, from what I could see, to be asking how the relative > technical merit scaled with generations. I replied that it was my > opinion that the relative technical difference probably stays constant > over generations. You introduced the economics, and I made the point > that there were 2 sides to the economics story, and I gave some real > figures to back that up. > > But yes, I was irritated by Austin's claim that ASIC starts are > decreasing by a factor of 10 a year. It's not even possible given that > there were only 10K starts a year maybe 7 years ago. It's also of > debatable relevance, given that a start at 90 or 110nm is going to > contain a lot more logic than a start at 130 or 180. > > PaulArticle: 96527
spammersarevermin schrieb: > Is there any way for a hobbyist to obtain the EDK in order to work w/ > Microblaze? Or is there any other way to obtain Microblaze? I don't > have the experience to be able to go to opencores and dive into one of > the processors there. > > Thanks, Tom > Spamming this account signifies > your unqualified consent to a free security audit There are two clones of the microblaze available in sourcecode. the aeMB from poencores -- programmable with the gnu assembler (mb-as). the openfire processor -- should work with mb-gcc (there is a demonstration on the websites) have a nice synthesis EilertArticle: 96528
Memory in all FPGAs is relatively expensive and generally limited in size. One Xilinx feature that is generally useful to Video applications is the SRL16 mode of the LUTs. You get 16 bits of storage per LUT. With these you can build a line FIFO either in x8 or x1 format very efficiently. We often use these in conjuction with external memory for some of the video work we do and have 2 or 3 lines of data stored within the FPGA. Be careful of the 128x1 macro. I am not sure if this is supported in Spartan-3 due to the fact that only half the LUTs can be configured as RAM in the Spartan-3. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 Development Board. http://www.enterpoint.co.uk "Isaac Bosompem" <x86asm@gmail.com> wrote in message news:1139186254.703000.140870@f14g2000cwb.googlegroups.com... > Hi everyone, I have recently purchased a XC3S200 based board with 256KB > Flash, 256KB platform flash and 32KB SRAM. So out of my interests I > figured I would design a simple SoC as a learning excercise. I have > designed a VGA framebuffer which does 640x480 (but uses pixel doubling > so 320x240x2-bit). A complete framebuffer is ~19KB. > > At this point I decided I would have to read the framebuffer at a line > at a time. A scanline in this mode would need 80 bytes of memory. > > Naturally I decided to infer a block RAM with 8-bit data width (well > 9-bit, but I am not using parity). > > The problem though is that when the Block RAM is 8-bits, you get almost > 2KB of space!! So that means I am wasting more than 90% of the space!! > > I was looking into using a 8 128x1 distributed RAM and wire them in a > way to extend the data word to 8-bits. I am not certain how much of my > logic resources this would eat up. > > I am fairly new to the FPGA's so I'm not certain if these are the best > methods to buffer such a small amount of memory. > What would you do if you were in my situation? > > Regards > -Isaac >Article: 96529
Paul Johnson wrote: > Xilinx has a report on Infiniband cable characterisation with RocketIO > MGTs (v2.0, May 10th 2004, > http://direct.xilinx.com/bvdocs/reports/ug043.pdf). Unfortunately, > this is vague on BER measurements. The intro states that BERs are > presented for various configurations but, in the event, the data > summary table only states whether or not the configuration "meets RX > requirements", which presumably means whether or not the BER is <= > 1E-12. The tests also used PRBS 2E7 rather than 8B/10B encoding, so > the BERs wouldn't be correct for Infiniband anyway, or for Aurora. > > Anyone happen to know of any better figures, or a later report? Or > have any experience of measuring BERs on RocketIO over these cables? > > Thanks - > > Paul BER over IB cables have a specific compliance measurement requirement, which I unfortunately do not have access to at the office, but I'll look it up later (I was a member of the physical layer subgroups of both EWG and CIWG amongst other things and I have the docs at home). I would assume Xilinx used that compliance spec requirement for the test (if they didn't, they obviously should not be claiming compliance). The specific requirements for IB cable (for single data rate, 2.5Gb/s per pair) is BER : <= 1E-12 Attenuation: <=10dB For 4x and 12x cables, (again SDR) there are also specific xtalk requirements. There are also jitter spec requirements which I can look up once I get home. Note the requirements for DDR and QDR cables are somewhat different, as the loss budget was changed from a loss style measurement to an eye-closure method of measurement for the system, and the compliance requirements were changed to S-parameter form. Can't help on RocketIO, though. Cheers PeteSArticle: 96530
bjzhangwn schrieb: > thanks,can i have a look at your document or source files? I'm sorry I can't disclose any source ... the documents you will need can be found at www.t13.org bye, MichaelArticle: 96531
Hi John, Thanks for the answer, is there anywhere where I can get a reference design or appnote that describes such a design (CS + MDM) ? Thanks, Mordehay.Article: 96532
> the documents you will need can be found at www.t13.org Version 6 should be supported by most of the current drives so you could start with this document: http://t13.org/project/d1410r3b-ATA-ATAPI-6.pdf as it describes every detail it has 500 pages (but you won't need most of it) ... start with the electrical interface and pinout you will at least need these functions: - Power-on and hardware reset protocol - Bus idle protocol - PIO data-in and data-out command protocol - Ultra DMA read/write of a block on to of that you can build functinos that perform - device id - set features - read sector/write sector if those are working then you could start with udma - read dma/write dma bye, MichaelArticle: 96533
Hello, I ported linux 2.4_devel to the ml403 board. The zImage. that you get is fine for loading into the Virtex4 ppc. The only thing you need to do is "cp" it to another directory with the .elf extension. I integrated it with my download.bit into an .ace file and it works ok both for the reference design and for my custom design (a basic one). Feel free to ask me about what I did if you need help. PaulaArticle: 96534
Jonathan Schneider wrote: > For making fine modifications to PCBs, which of Tefzel and Kynar > insulated wired are best to use ? > > Jonn Tefzel strips easily, but the insulation isn't so rugged - tends to melt easily Kynar can be interesting to strip, but will withstand a soldering iron touch etc Sometimes 'enamel' (actually polyurethane) coated wire is the right thing to use, because you can tin the end without having to apply a force to strip it ! It is also easier to bend into an awkward corner. Obviously it is not as strong ... Tack it down afterwards with hotmelt or cyano DaveArticle: 96535
Jonathan Schneider wrote: > For making fine modifications to PCBs, which of Tefzel and Kynar > insulated wired are best to use ? I use PTFE wire. It doesn't melt and is a bit thicker than wire-wrap wire, making it less likely to break. LeonArticle: 96536
"gnathita" <gnathita@gmail.com> wrote in message news:WrqdnRI4UMOZpHreRVn-vQ@giganews.com... > Hello, > > I ported linux 2.4_devel to the ml403 board. > > The zImage. that you get is fine for loading into the Virtex4 ppc. The > only thing you need to do is "cp" it to another directory with the .elf > extension. > > I integrated it with my download.bit into an .ace file and it works ok > both for the reference design and for my custom design (a basic one). > > Feel free to ask me about what I did if you need help. > Paula > > > I'd like a copy of your .config file? I was also wondering if one generates the standard linux architecture (cpu, timer, interrupt controller, etc. all at the right memory addresses) can't they generate an .edn file and a top-level vhdl instantiation so that anyone else can use it without needing the EDK? Basically, it seems like there should be a coregen module that asks: 1. clock speed 2. processor: ppc or microblaze 3. device family: v2pro or v4 4. memory types and sizes 5. maybe some optional periperals And then it generates an .edn and a vhdl template that you pull into your ISE project like any othe core. This way we wouldn't need the EDK and they could provide prebuilt linux images that you would know work. Linux would become a 10 minute task for Xilinx: a competitive advantage I'd say. -ClarkArticle: 96537
hi,all. I am realize pci target core in fpga(cyclone),but there are some questions. 1,I don't know what type pin should pci_clk be,normal io or clk of fpga? 2,I series 50ohm resistors between pci connector and fpga,does this bring some problems? the goal is to make it suitable for 3.3v and 5v. thanks.Article: 96538
er ... 32 slices not 16 ... but as John pointed out, the 128x1 macro might not work in spartan3/virtex4 ...Article: 96539
I have a query regarding the Nital PExBuilder-X254-pci express X4 Xilinx design kit which uses xilinx Pci express logicore version 2.1. Presently the board is being tested with Supermicro X6DH8-G2 motherboard which has 8x and one 4x(8x slot mechanical and 4x electrical). I found that sometimes the board is being configured as 1x instead of 4x. This problem is quite random.Approx once in twenty times i.e if i reboot the machine twenty times the board may configure to 1x once. if anybody else has faced similar problem, can u please give some pointers regarding the problem I am facing. Thanks, SarunArticle: 96540
Thanks for the offer. I'm actually not doing anything particularly exotic. I just want to embed a "linux pc" into my fpgas to replace what was traditionally done by custom control processor designs and software. In my view it should just be a coregen module that Xilinx provides but it's turning out to be more involved. Anyway my specific wish list is: 1. linux (2.6 kernel preferred) 2. Virtex-4 family 3. gigabit ethernet 4. sd card (or other portable memory) 5. power control (reduce clock or sleep processor) 6. usb gadget driver and USB2.0 is the current microblaze/uClinux tree able to do this? Thanks, Clark "John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:newscache$nsj8ui$7ce$1@lbox.itee.uq.edu.au... > Clark, > > Anonymous wrote: > > > My application requires a USB2.0 slave mode. Does anyone know which tree is > > best for USB gadgets: PPC/Linux or MB/uClinux? > > I suggest we take this off-list before we are lynched for being > permanently off-topic. > > Can you email me directly, or discuss on the microblaze-uclinux list? > > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ > > Thanks, > > John > >Article: 96541
Paul Marciano wrote: > Hi. Quick question for you all. > > I have a 20MHz FPGA clock and I have some very low frequency periodic > actions to take care of so I want to generate an approximate 10Hz clock > to give to the modules that need it so they don't need their own big > wide counters. > > module slowclk(input clk, output slowclk); > reg [19:0] cnt = 29'h0; > > assign slowclk = cnt[19]; > > always @(posedge clk) > cnt <= cnt + 20'h1; > > endmodule > > > If I have a module that uses both the full speed and the slow speed > clocks, can I use the clk and slowclk together without problems? Let > me give you an example: > > ... in the mixed clock module: > > always @(posegde slowclk) > x <= expression > > always @(posedge clk) > if (x) > do_something; > else > do_something_else > > > I believe that as the clocks are in-phase there's no problem. Just > wanted to check with the experts. The clocks are _almost_ in phase. slowclk will be delayed from clk due to the clock to Q of counter bit cnt[19] and the global buffer that gets thrown in unless you specify otherwise. At 20 MHz, you generally won't have setup time ussues with passing x to the fast process. You may still want to put in a FROM : TO style timing constraint to make sure of this. The usual problem here is hold time violations going from the fast process to the slow one. If your (expression) in the slow process uses any outputs of the fast process, then you can have hold time violations due to the slowclk delay. Note that the skew times in your timing report are within each clock domain and don't indicate skew between the two clocks. Good luck, Gabor > > The target is a Spartan3 FPGA and ISE7.1i reports: > > WARNING:Route - CLK Net:slowclk_blk/cnt<19> > may have excessive skew because 1 NON-CLK pins > failed to route using a CLK template. > > ************************** > Generating Clock Report > ************************** > > +---------------------+--------------+------+------+------------+-------------+ > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > Delay(ns)| > +---------------------+--------------+------+------+------------+-------------+ > | CLK_i_BUFGP | BUFGMUX7| No | 366 | 0.191 | > 0.792 | > +---------------------+--------------+------+------+------------+-------------+ > | slowclk_blk/cnt<19> | BUFGMUX3| No | 24 | 0.181 | > 0.786 | > +---------------------+--------------+------+------+------------+-------------+ > > ... which looks good to me. > > > Advice welcome. > > Thanks. > Paul.Article: 96542
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:1139168954.693365.257390@g14g2000cwa.googlegroups.com > I have a couple of spread sheets from FPGA vendors for power > calculation. They "protect" the spread sheet, I assume so that you > don't mess with the calculations. I find that my anti-virus software > can't open the document and reports an error every time it is scanned. > I tried to disable the protection, but that option is not available on > these files. Anyone know what is going on? Even if I need a > password to unprotect the workbook, I can't find where to enter it. > > I guess I can just delete it to get it off the PC and download it > fresh each time I need to use it, or maybe put it on a CD. But I am > tired of going through a list of dozens of errors on protected files > each time I run my AVS and I am getting rid of them one way or the > other. You might give this a try if the vendor won't give you the password - http://www.lostpassword.com/excel.htm -- James T. WhiteArticle: 96543
On Mon, 6 Feb 2006 00:32:09 -0800, "Caleb Leak" <dornif@gmail.com> wrote: >Comparing FPGAs and ASICs seems to be a hard comparison to make (even when >just comparing current generation technology), Indeed. Particularly when you're trying to keep your suppliers sweet... :)Article: 96544
eehinjor wrote: > hi,all. > I am realize pci target core in fpga(cyclone),but there are some > questions. > 1,I don't know what type pin should pci_clk be,normal io or clk of > fpga? > 2,I series 50ohm resistors between pci connector and fpga,does this > bring some problems? the goal is to make it suitable for 3.3v and 5v. > thanks. > Cyclone is not compatible with PCI 5v, the voltage transients exceed 5v and will damage the device. You will need to use IDT Quickswitch or similar device to limit the input voltage to your Cyclone in a 5v scenario. Google for PCI and quickswitch, you should find a Xilinx app's note on the subject. AlanArticle: 96545
Jim Granville wrote: > austin wrote: >> dp, >> >> I know you do not belive me. And you haven't ever solved Maxwells >> equations for this case (or else you would see it). >> >> I am not going to convince you, so I will not try, but it is a real >> effect, and it really happens. >> >> I also admit that it is greatly misunderstood (after all, Westinghouse >> believed as you do, util they made a million dollar mistake by >> building it, and experiencing it first hand). > > Take a magnet near the front of a Shadow mask CRT, and you can > clearly see the effect a magnet has on moving (dc) electrons. > DC current requires electrons to move, even if the ammeter does not. > > -jg > That's a different situation, in that the electrons are moving quickly. The average speed of the electrons moving through a conductor is, AFAIK, very slow.Article: 96546
abgoyal@gmail.com wrote: > HI, > > > I am not sure i understand your architecture, can you please describe > exactly what you are doing with a single BRAM? > > Pending further information, One this is for sure, you dont want to use > D-RAM as long as you can avoid it. > > I may have completely misunderstood, but why can't you address the > entire block RAM (with its 2K depth) using a combination of the > horizontal and vertical address lines? > > so suppose you keep your current form factor for the BRAM block (8-bit > wide). > then you could have the high 7 horizontal pixel counter bits hooked up > to the low seven address lines of the BRAM, giving you 128 addressable > locations. Each location contains 4 pixels, which you can then > multiplex on to the output with addtional logic (as i presume u are > already doing). > > the high 4 address lines to the BRAM block can be connected to the low > 4 bits of the vertical line counter. Thus, you would be using 16*80 = > 1280 bytes of the total available 2K. > > You would still have 4 additional vertical counter bits remaining, > which means you will have to use a total of 16 BRAM blocks. This also > implies you will need a 16to1 8-bit wide MUX. > > Hope this helps. The problem with this method is that, I am using 8-bit wide SRAM. I wish I had 16-bit wide SDRAM on my board! I would like to get an SoC up so if I make changes to the VGA hardware I would like to relieve some pressure off the bus. I will have a softcore CPU and a delta-sigma DAC running so I would like the VGA hardware to use as little of the time as possible. So if I want to buffer more data, I would also like to reduce the frequency of the buffer reads. I can read a byte from the SRAM (fortunately) at every clock cycle. That means reading 1280 bytes during the H blanking period (I believe I have close to 100 clk cycles in HBlanking, I am not at home now) is impossible (unless I make the SRAM reading unit operate asynchronously with the VGA dot clock). So technically I am limited to either reading the whole frame (which will need most of the BRAMs available in my Spartan3) or read it a scanline at a time. I will check into using the SRL16's, but taking a quick glance through the app note I can't seem to find how to reload data in to the SRL16's. Do I have to shift it in a bit at a time at each clock cycle? It is possible, that I may have to eat my losses :(Article: 96547
I haven't gotten that far yet. I can't even find how to tell it I want to unprotect it. I guess I'll just have to tell the AVS to skip this file. James T. White wrote: > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:1139168954.693365.257390@g14g2000cwa.googlegroups.com > > I have a couple of spread sheets from FPGA vendors for power > > calculation. They "protect" the spread sheet, I assume so that you > > don't mess with the calculations. I find that my anti-virus software > > can't open the document and reports an error every time it is scanned. > > I tried to disable the protection, but that option is not available on > > these files. Anyone know what is going on? Even if I need a > > password to unprotect the workbook, I can't find where to enter it. > > > > I guess I can just delete it to get it off the PC and download it > > fresh each time I need to use it, or maybe put it on a CD. But I am > > tired of going through a list of dozens of errors on protected files > > each time I run my AVS and I am getting rid of them one way or the > > other. > > You might give this a try if the vendor won't give you the password - > http://www.lostpassword.com/excel.htm > > -- > James T. WhiteArticle: 96548
Where do I find Xilinx's MIG? What does it cost? Brad Smallridge aivision dot comArticle: 96549
Found it. Nevermind.
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