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"Ray Andraka" <ray@andraka.com> wrote in message news:_UpHf.48131$bF.46178@dukeread07... > Roger wrote: >> Ray, >> >> Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no >> problems. >> >> Rog. >> >> "Ray Andraka" <ray@andraka.com> wrote in message >> news:kpaHf.45966$bF.17191@dukeread07... >> >>>We are considering a change to the IO standard used for the QDR-II >>>interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx >>>has not created any demo boards that use the 1.5V interfaces, but they >>>claim that it should work fine. >>> >>>Have any of you completed a Xilinx design that uses the 1.5V interfaces >>>(for QDR-II) or know of a successful development? >> >> >> > > Thanks, that's what I needed to know. A customer is making a custom board > and wanted to know that the 1.5v HSTL worked before committing to it. I've just got 1 QDR on the board so the connections are simple point to point. I can't comment on a bus arrangement. Glad to help. Rog.Article: 96851
>hi, i am new to this field and studying my under graduate course on >FPGAs. to perform experiments practically i am planning to buy one >chip. so please suggest me which one among the available FPGAs suit me >so that i get in touch with it and also suggest me any softwares >available to interface the same with my pc. Do you really want a raw chip to put on a board you are designing? Or do you want a board that includes an FPGA you can easily program? Xilinx's Spartan 3 starter kit is $100. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 96852
"wicky" <wicky.zhang@gmail.com> wrote in message news:1139670926.240198.163270@f14g2000cwb.googlegroups.com... > Hi all, > > I want to use FPGA in control field. I know that uC or DSP processor is > a preferable choice to control engineer in general. But in my opinion, > the HDL-based logic inside FPGA is more appropriate for those high > performance needed but simple function tasks just as the role of a > controller in control system, while the C language can realize > complicated application. i.e. In my control system, the controller > will be based on HDL inside FPGA to get a extremely high performance > and high reliability, while the rest of the work, such as > communication, data processing and human-machine interface will be > based on C language to get a more flexible system. > > Certainly, the C-based embedded system may be implemented inside FPGA > to form a SOC system and may be based on an OS for more convinent. > > Can anyone give me some advice and papers about this idea? thans a > lot. > > Best Regards, > > Wicky > I did this recently using only an FPGA, with no host CPU. As you suggest, the FPGA is great for creating high performance control functions (in my case the performance wasn't high - just a phase controlled SCR drive, but things like feedback filtering, PLL's for synchronizing, etc etc) Since I had no host, I also implemented a communications protocol for a tuning and monitoring application hosted on a PC - I really wouldn't recommend this, such things are much easier in a processor. One piece of advice - if you can afford it, use an FPGA with embedded multiplier blocks and plentiful RAM. In pretty much all control functions you're MAC'ing process variables and coefficients. In my design, I ate up most of an EP1C6 with multipliers. You can reduce this somewhat by creating long multipliers, or off-line calculation of LUT's for partial products, but on my next design (way bigger and multi-channel servo performance), I'm moving to Cyclone II just for the embedded multipliers. Another thing that makes it somewhat harder on an FPGA than in MCU/DSP is implementing all the "what if" non-linear cases that are easy to code in C or assembler (simple example, avoid integral wind-up when some down-stream process saturates). Saturation versus overflow is also something that DSP's help you with. You will have to create saturating maths blocks. With all the caveats, you can achieve some pretty breathtaking loop closure times - not that you usually need them. GArticle: 96853
Gary Pace wrote: > "wicky" <wicky.zhang@gmail.com> wrote in message > news:1139670926.240198.163270@f14g2000cwb.googlegroups.com... > > > I did this recently using only an FPGA, with no host CPU. As you suggest, > the FPGA is great for creating high performance control functions (in my > case the performance wasn't high - just a phase controlled SCR drive, but > things like feedback filtering, PLL's for synchronizing, etc etc) > > Since I had no host, I also implemented a communications protocol for a > tuning and monitoring application hosted on a PC - I really wouldn't > recommend this, such things are much easier in a processor. > > One piece of advice - if you can afford it, use an FPGA with embedded > multiplier blocks and plentiful RAM. In pretty much all control functions > you're MAC'ing process variables and coefficients. In my design, I ate up > most of an EP1C6 with multipliers. You can reduce this somewhat by creating > long multipliers, or off-line calculation of LUT's for partial products, but > on my next design (way bigger and multi-channel servo performance), I'm > moving to Cyclone II just for the embedded multipliers. > > Another thing that makes it somewhat harder on an FPGA than in MCU/DSP is > implementing all the "what if" non-linear cases that are easy to code in C > or assembler (simple example, avoid integral wind-up when some down-stream > process saturates). Saturation versus overflow is also something that DSP's > help you with. You will have to create saturating maths blocks. > > With all the caveats, you can achieve some pretty breathtaking loop closure > times - not that you usually need them. > > G > > > > Or you can make it pretty small using sequential multipliers (scaling accumulators)Article: 96854
Roger wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:_UpHf.48131$bF.46178@dukeread07... > >>Roger wrote: >> >>>Ray, >>> >>>Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no >>>problems. >>> >>>Rog. >>> >>>"Ray Andraka" <ray@andraka.com> wrote in message >>>news:kpaHf.45966$bF.17191@dukeread07... >>> >>> >>>>We are considering a change to the IO standard used for the QDR-II >>>>interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx >>>>has not created any demo boards that use the 1.5V interfaces, but they >>>>claim that it should work fine. >>>> >>>>Have any of you completed a Xilinx design that uses the 1.5V interfaces >>>>(for QDR-II) or know of a successful development? >>> >>> >>> >>Thanks, that's what I needed to know. A customer is making a custom board >>and wanted to know that the 1.5v HSTL worked before committing to it. > > > I've just got 1 QDR on the board so the connections are simple point to > point. I can't comment on a bus arrangement. > > Glad to help. > > Rog. > > Ours has 4 banks, with the banks in pairs so that the address and control are shared between two devices. Those are clamshell mounted so that they are pretty close to single source-single destination. If you have it working with a single device, I think we'll be OK with this. The customer was concerned with whether or not the 1.5v worked with the QDR at all or not. Thanks!Article: 96855
PeterC wrote: >> I do need the same degree of control around 50 kHz (ideally even better > than 1 Hz, down to as low as 0.1 Hz) so I don't think a simple integer > division is acceptable. Hi, PeterC Here is a method that gives very fine resolution at low cost, but is not so easy to tune: Use the DCM in frequency synthesis mode. Let's assume a 100 MHz input clock. By using various mixtures of Multiply and Divide, you can generate, for example, 16 different frequencies between 103.22 MHz and 106.6 MHz (starting with 32/31, the 31/30, then 30/29 etc) Yes, you can multiply 100 MHz by 32 if you simultaneously also divide it down to a resonable value. >From this large (or even larger) number of tightly-spaced frequencies, you can divide down to 50 kHz with a granularity of a few Hz (perhaps even below 1 Hz if you have some patience playing with the numbers. The output frequency is 100 MHz x (A/B) / C,, where A and B are any integer up to 32, and C is any integer that you need. Jitter will be low, but there might be some wander. Best check for spectral purity. The problem is that this approach is not straightforward. It needs pre-computation. But if you need just a few hundred frequencies, you can store the constants in a BlockRAM. And you have to reconfigure the DCM whenever you need to change A or B. That may be the biggest drawback. I remember that you needed to convert between specific audio frequencies last summer. This method might be interesting for that. I did not think of it then. Peter Alfke, Xilinx ApplicationsArticle: 96856
And then Grey Beard wrote: > I'm quite new to this area..I'm completeing a bachelor in > electronics..As a part of my project i'm to create a sdram controller > for xilinx 11 pro(ff1152) based memec board...Although memory managent > is available as a ref design..We are not using the power processor > inside?Can anyone give me some directions on this one?i'd be grateful.. XESS (www.xess.com) has VHDL source code for SDRAM controller designed for some of their FPGA boards. With few little tweaks, you could adjust it for your needs.Article: 96857
Ray Andraka wrote: > Gary Pace wrote: > >> "wicky" <wicky.zhang@gmail.com> wrote in message >> news:1139670926.240198.163270@f14g2000cwb.googlegroups.com... >> > >> >> I did this recently using only an FPGA, with no host CPU. As you >> suggest, the FPGA is great for creating high performance control >> functions (in my case the performance wasn't high - just a phase >> controlled SCR drive, but things like feedback filtering, PLL's for >> synchronizing, etc etc) >> >> Since I had no host, I also implemented a communications protocol for >> a tuning and monitoring application hosted on a PC - I really wouldn't >> recommend this, such things are much easier in a processor. >> >> One piece of advice - if you can afford it, use an FPGA with embedded >> multiplier blocks and plentiful RAM. In pretty much all control >> functions you're MAC'ing process variables and coefficients. In my >> design, I ate up most of an EP1C6 with multipliers. You can reduce >> this somewhat by creating long multipliers, or off-line calculation of >> LUT's for partial products, but on my next design (way bigger and >> multi-channel servo performance), I'm moving to Cyclone II just for >> the embedded multipliers. >> >> Another thing that makes it somewhat harder on an FPGA than in MCU/DSP >> is implementing all the "what if" non-linear cases that are easy to >> code in C or assembler (simple example, avoid integral wind-up when >> some down-stream process saturates). Saturation versus overflow is >> also something that DSP's help you with. You will have to create >> saturating maths blocks. >> >> With all the caveats, you can achieve some pretty breathtaking loop >> closure times - not that you usually need them. >> >> G >> >> >> >> > > Or you can make it pretty small using sequential multipliers (scaling > accumulators) Or you can make an ALU and use a state machine to schedule all the computations through it. You'd be getting something suspiciously like a microprocessor, though. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 96858
I have ordered a development board of Xilinx----ML403, based on
Virtex4-FX (with PPC405 core inside). So the resource should be enough
for my prototype test.
I am designing a daughter card with 8 channel A/D and 8 channel D/A,
the chips are:
1: 2 pieces of A/D chip---- ADS8361, 2+2 Channel, 500kSPS, serial
input 16-Bit,
Simultaneous Sampling A/D
Converter
2: 2 pieces of D/A chip---- DAC8814 , Quad, 1uS settling time, Serial
Input 16-Bit
Multiplying Digital-to-Analog
Converter
i will interface those 4 chips separately. IO pins of ML403 are enough.
Because i want to use system generator tools to autogenerate the HDL
code instead of writing them in hand, i have to write the custom block
of the resource on my daughter card. It seems i should use the black
box characteritics of system generator, did anyone here have the
experience on it?
obviously, the cost of my prototype system will be expensive, but it
will only be for prototyping, in the real systems, i will chose such
low-cost FPGA such as CycloneII or SpartenIII.
Btw: can anyone give me some info of papers as reference in theory. And
I'm eager to know the current status of this research area.
Article: 96859
chaitu11311@gmail.com wrote:
> hi, i am new to this field and studying my under graduate course on
> FPGAs. to perform experiments practically i am planning to buy one
> chip. so please suggest me which one among the available FPGAs suit me
> so that i get in touch with it and also suggest me any softwares
> available to interface the same with my pc.
Unless you're planning to do a fair amount of work as a technician, you
probably want a pre-fabbed board rather than just a chip.
Xilinx has a Spartan 3 starter kit for about $100 here:
http://tinyurl.com/7pnsk
Altera has a Max II development kit for about $150 here:
http://tinyurl.com/76k5h
Lattice has a number of development boards around $100-200 available
here:
http://tinyurl.com/9ks2s
When/if you try to enter their online store, they'll ask for a user
name and password -- but if you cancel, it'll let you in (and I haven't
seen a place to sign up to get a user name or password either).
Enterpoint has a couple of nice looking boards available here:
http://www.enterpoint.co.uk/moelbryn/minican.html
Unfortunately, while the prices are pretty nice, shipping to the US is
a bit on the steep side.
Avnet has a fairly extensive list of development boards available here:
http://tinyurl.com/43ozs
FPGA4FUN.com has a number of (mostly Altera-based) boards available at
quite reasoanble prices here:
http://www.knjn.com/ShopBoards.html
That's far from an exhaustive list, but it's probably more than enough
to overwhelm you for now! :-)
One final note: keep in mind that you'll have to develop controllers
for most of what's on the board to actually be able to use them. The
connectors for PCI, Ethernet, USB, etc., each need to be driven
correctly to do anything useful. It's pretty easy to develop and/or
find cores for things like serial ports, but quite a bit more difficult
(and/or expensive) to deal with PCI (for one example). Likewise with
things like on-board memory -- just for example, a big DDR2 SDRAM may
sound sexy, but be prepared for a fair amount of work before you can
get data into or out of it dependably.
I haven't played with anywhere close to all of these, but of the ones I
have played with, the Spartan 3 starter kit probably has the most
accessible peripherals. Pretty much when you decide to do something
that needs to use the memory, serial port, LEDs, etc., you just do it
and it works. You could download and use any of several UART cores for
the serial port (for example) but I've never bothered -- I suspect it's
probably close to as much work to figure out how to use somebody else's
UART as it is to write at least a simple one of your own (though
somebody else's might be more efficient).
--
Later,
Jerry.
The universe is a figment of its own imagination.
Article: 96860what is a good schematic capture program that is compatible with Xilinx ISE? Does OSR exist? optical schematic recognition (TM) (c) can I scan a schematic and get CAD schematic file from it? RichArticle: 96861
rickman wrote: "This reminds me a bit of the way fuzzy logic was claimed to be such an advance, but when you looked at it hard you would find little or no real advantage. Do you see many fuzzy logic projects around anymore?" Yes, quite a few. Bruno Di Stefano posted these 10 recently: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ GPS car navigation from German company NAVIGON comes to USA (http://msmobiles.com/news.php/4766.html ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Emerson Wins $13 Million Contract to Digitally Automate Korea's Largest Coal-Fired Power Plant (http://www.automation.com/store/pdetails16264.php ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Socket Communications Unveils Industry First Cordless Ring Scanner for Bluetooth Enabled Mobile Computers (http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=n... ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Fujitec eases bottlenecks (http://news.enquirer.com/apps/pbcs.dll/article?AID=/20060116/BIZ01/60... ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ WCC Announces ELISE for Linux (http://www.prnewswire.com/cgi-bin/stories.pl?ACCT=104&STORY=/www/stor... ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Bluetooth "ring scanner" works with Windows Mobile handhelds (http://www.windowsfordevices.com/news/NS9845751870.html ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Online Marketing: Google Enhances Filters Once Again - How will it affect you? (http://rismedia.com/index.php/article/articleview/13227/1/1/) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Handwriting recognizer supports square screens, VGA (http://www.windowsfordevices.com/news/NS2550969623.html ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ CalliGrapher 8.2 for Mobile Devices (http://www.digitalhomecanada.com/content/view/1007/60/ ) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ The Weather Wizards (http://www.avweb.com/news/airman/191492-1.html ) "With the Forecast Icing Potential (FIP) tool, pilots can make themselves aware of expected icing hazards along their route up to 12 hours in advance. FIP provides a high-tech, color, weather map and a flight-route display of icing potential at flight levels from 3,000 to 18,000 feet. The algorithm analyzes weather data from a vertical column perspective. It determines the cloud top and base heights, checks for embedded cloud layers, and identifies precipitation types. Once the likely locations of clouds and precipitation are found, the physical icing situation is determined, and a fuzzy logic method is used to determine the icing potential. Every three hours the model generates forecasts out to 12 hours. The user can select forecast times from three-, six-, nine-, and 12-hour intervals to plan safe routes of travel." ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++Article: 96862
"Giox" <giovanniparodi79@yahoo.it> a écrit dans le message de news:
>I have the following code:
>
> signal busy_condition : std_logic;
> signal high_registered : std_logic_vector(1 downto 0);
> signal high_current : std_logic_vector(1 downto 0);
>
>
> busy_condition <= '1' WHEN (CONV_INTEGER(high_current) >
> CONV_INTEGER(high_registered))
> ELSE '0';
>
> During simulation
> high_registered become "10"
> and
> high_current = "00".
> However busy_condition is high impedence.
> Is there someone that can explain me what is my error?
> Thanks a lo Gio
>
Which library do you use? Signed or unsigned? If you use
ieee.std_logic_signed.all, the CONV_INTEGER ("10") is a negative number.
Change your library or add a sign bit like this:
busy_condition <= '1' WHEN (CONV_INTEGER('0'&high_current) >
CONV_INTEGER('0'&high_registered))
ELSE '0';
Dan.
Article: 96863
Hello,
I would like to configure a Spartan 3 device (3S200) using its parallel
slave interface mode. Unfortunately, I cannot provide a continuous data
stream, because it comes from a NAND flash memory module connected
to the configuration bus (it acts in user mode as a standard multimaster
interconnect between the memory, FPGA and MCU), so I need to
disconnect my partly configured FPGA chip temporarily to set up the
following data block and then reconnect it back. Can I use Spartan's
CS_B signal to achieve that?
Best regards
Piotr Wyderski
--
"If you were plowing a field, which would you rather use?
Two strong oxen or 1024 chickens?" -- Seymour Cray
Article: 96864Well I better put our case when mentioning prices. Raggedstone1 is US $90 , ?75, £50. If you don't have a scrap motherboard and power supply it can be bundled with the PCI I/O Header that allow stand alone use (not in PC and gives 50 extra 5V tolerant I/O). Bundle is $117 (discounts on quantities) and it is a bigger chip (XC3S400) that the standard starter kit has. If you are a student or University we can offer up to a XC3S2000 (RS1-2000) on the board at surprisingly good prices. There may be extended lead times on the bigger chip fits but we will see how popular they are to the target group and maybe start to hold more stock. The RS1-1500 is being made for stock and would be the recommend "large" chip version due to the support of the XC3S1500 in Xilinx Webpack tools. The XC3S2000 is not covered by Webpack. Find Raggedstone1 here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html . John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan-3 Development Board. http://www.enterpoint.co.uk "Jerry Coffin" <jerry.coffin@gmail.com> wrote in message news:1139723169.255425.58910@g43g2000cwa.googlegroups.com... > chaitu11311@gmail.com wrote: >> hi, i am new to this field and studying my under graduate course on >> FPGAs. to perform experiments practically i am planning to buy one >> chip. so please suggest me which one among the available FPGAs suit me >> so that i get in touch with it and also suggest me any softwares >> available to interface the same with my pc. > > Unless you're planning to do a fair amount of work as a technician, you > probably want a pre-fabbed board rather than just a chip. > > Xilinx has a Spartan 3 starter kit for about $100 here: > > http://tinyurl.com/7pnsk > > Altera has a Max II development kit for about $150 here: > > http://tinyurl.com/76k5h > > Lattice has a number of development boards around $100-200 available > here: > > http://tinyurl.com/9ks2s > > When/if you try to enter their online store, they'll ask for a user > name and password -- but if you cancel, it'll let you in (and I haven't > seen a place to sign up to get a user name or password either). > > Enterpoint has a couple of nice looking boards available here: > > http://www.enterpoint.co.uk/moelbryn/minican.html > > Unfortunately, while the prices are pretty nice, shipping to the US is > a bit on the steep side. > > Avnet has a fairly extensive list of development boards available here: > > http://tinyurl.com/43ozs > > FPGA4FUN.com has a number of (mostly Altera-based) boards available at > quite reasoanble prices here: > > http://www.knjn.com/ShopBoards.html > > That's far from an exhaustive list, but it's probably more than enough > to overwhelm you for now! :-) > > One final note: keep in mind that you'll have to develop controllers > for most of what's on the board to actually be able to use them. The > connectors for PCI, Ethernet, USB, etc., each need to be driven > correctly to do anything useful. It's pretty easy to develop and/or > find cores for things like serial ports, but quite a bit more difficult > (and/or expensive) to deal with PCI (for one example). Likewise with > things like on-board memory -- just for example, a big DDR2 SDRAM may > sound sexy, but be prepared for a fair amount of work before you can > get data into or out of it dependably. > > I haven't played with anywhere close to all of these, but of the ones I > have played with, the Spartan 3 starter kit probably has the most > accessible peripherals. Pretty much when you decide to do something > that needs to use the memory, serial port, LEDs, etc., you just do it > and it works. You could download and use any of several UART cores for > the serial port (for example) but I've never bothered -- I suspect it's > probably close to as much work to figure out how to use somebody else's > UART as it is to write at least a simple one of your own (though > somebody else's might be more efficient). > > -- > Later, > Jerry. > > The universe is a figment of its own imagination. >Article: 96865
For anyone that's interested the ?75 is 75 Euros. Carriage has recently dropped to all locations and we are working to drop in further. I believe US next day carriage (Customs etc allowing) will drop to same as the EEC courier rate this week TBC. John Adair Enterpoint Ltd. - Home of Raggedstone1. The 75 Euro Spartan-3 Development Board. http://www.enterpoint.co.uk "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:dsn67m$io9$1@news7.svr.pol.co.uk... > Well I better put our case when mentioning prices. Raggedstone1 is US $90 > , ?75, £50. > > If you don't have a scrap motherboard and power supply it can be bundled > with the PCI I/O Header that allow stand alone use (not in PC and gives 50 > extra 5V tolerant I/O). Bundle is $117 (discounts on quantities) and it is > a bigger chip (XC3S400) that the standard starter kit has. If you are a > student or University we can offer up to a XC3S2000 (RS1-2000) on the > board at surprisingly good prices. There may be extended lead times on the > bigger chip fits but we will see how popular they are to the target group > and maybe start to hold more stock. The RS1-1500 is being made for stock > and would be the recommend "large" chip version due to the support of the > XC3S1500 in Xilinx Webpack tools. The XC3S2000 is not covered by Webpack. > > Find Raggedstone1 here > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html . > > John Adair > Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan-3 Development > Board. > http://www.enterpoint.co.uk > > > "Jerry Coffin" <jerry.coffin@gmail.com> wrote in message > news:1139723169.255425.58910@g43g2000cwa.googlegroups.com... >> chaitu11311@gmail.com wrote: >>> hi, i am new to this field and studying my under graduate course on >>> FPGAs. to perform experiments practically i am planning to buy one >>> chip. so please suggest me which one among the available FPGAs suit me >>> so that i get in touch with it and also suggest me any softwares >>> available to interface the same with my pc. >> >> Unless you're planning to do a fair amount of work as a technician, you >> probably want a pre-fabbed board rather than just a chip. >> >> Xilinx has a Spartan 3 starter kit for about $100 here: >> >> http://tinyurl.com/7pnsk >> >> Altera has a Max II development kit for about $150 here: >> >> http://tinyurl.com/76k5h >> >> Lattice has a number of development boards around $100-200 available >> here: >> >> http://tinyurl.com/9ks2s >> >> When/if you try to enter their online store, they'll ask for a user >> name and password -- but if you cancel, it'll let you in (and I haven't >> seen a place to sign up to get a user name or password either). >> >> Enterpoint has a couple of nice looking boards available here: >> >> http://www.enterpoint.co.uk/moelbryn/minican.html >> >> Unfortunately, while the prices are pretty nice, shipping to the US is >> a bit on the steep side. >> >> Avnet has a fairly extensive list of development boards available here: >> >> http://tinyurl.com/43ozs >> >> FPGA4FUN.com has a number of (mostly Altera-based) boards available at >> quite reasoanble prices here: >> >> http://www.knjn.com/ShopBoards.html >> >> That's far from an exhaustive list, but it's probably more than enough >> to overwhelm you for now! :-) >> >> One final note: keep in mind that you'll have to develop controllers >> for most of what's on the board to actually be able to use them. The >> connectors for PCI, Ethernet, USB, etc., each need to be driven >> correctly to do anything useful. It's pretty easy to develop and/or >> find cores for things like serial ports, but quite a bit more difficult >> (and/or expensive) to deal with PCI (for one example). Likewise with >> things like on-board memory -- just for example, a big DDR2 SDRAM may >> sound sexy, but be prepared for a fair amount of work before you can >> get data into or out of it dependably. >> >> I haven't played with anywhere close to all of these, but of the ones I >> have played with, the Spartan 3 starter kit probably has the most >> accessible peripherals. Pretty much when you decide to do something >> that needs to use the memory, serial port, LEDs, etc., you just do it >> and it works. You could download and use any of several UART cores for >> the serial port (for example) but I've never bothered -- I suspect it's >> probably close to as much work to figure out how to use somebody else's >> UART as it is to write at least a simple one of your own (though >> somebody else's might be more efficient). >> >> -- >> Later, >> Jerry. >> >> The universe is a figment of its own imagination. >> > >Article: 96866
avishay wrote: > Hello all, > I have to create a low speed clock (8KHz) out of a high speed one > (50MHz) on an Altera FPGA (Cyclone II). It has to be a real clock, not > a clock enable. PLL is of course out of question because this frequency > is out of its range. Trying to generate it with a simple couter > generates many warning, and in some cases Quartus reports that the > design does not meet time constraints. I tried to designate the > generated signal as a clock, but it doesn't improve the situation. > Is there another, "correct" way for doing this? Maybe I should insert > some kind of buffer after the counter? I would appreciate your advice. > > Thanks, > Avishay Orpaz As mentioned, just use a synchronous counter. I generate a 8kHz clock (for PCM framing) from a 20.48MHz clock using precisely that scheme and it works fine. Does your output clock have a specific phase timing requirement to the original clock? That might be where your errors are coming from. If you are using a completely synchronous design, the 8kHz clock will be only a couple of propagation delays behind the master clock. Cheers PeteSArticle: 96867
You also might want to look at the T-Rex C1 Development Kit http://www.terasic.com.tw/english/fpga_01.htm For starting, all it needs is an USB port (power via USB).Article: 96868
hello ppl....can neone plz help me out...I guess i have done some homework regarding my tools....plz help me out guysArticle: 96869
On 11 Feb 2006 14:25:11 -0800, "Giox" <giovanniparodi79@yahoo.it> wrote: >I have the following code: > > signal busy_condition : std_logic; > signal high_registered : std_logic_vector(1 downto 0); > signal high_current : std_logic_vector(1 downto 0); > > >busy_condition <= '1' WHEN (CONV_INTEGER(high_current) > >CONV_INTEGER(high_registered)) > ELSE '0'; > >During simulation >high_registered become "10" >and >high_current = "00". >However busy_condition is high impedence. >Is there someone that can explain me what is my error? >Thanks a lo Gio The basic problem is that you are using non-standard libraries to make your code ambiguous. Is "10" a positive number or a negative one? Using "ieee.numeric_std" you would make the signals in question either signed or unsigned, according to what your code is meant to do, and simplify the expression to busy_condition <= '1' WHEN high_current > high_registered ELSE '0'; - BrianArticle: 96870
AluPin is right, you are taking off a bit more than you can chew. I myself have designed a Framebuffer VGA device and am working on a softcore CPU and even myself wouldnt try DDR (let alone DDR2). I would do SDRAM though, not too complicated as you will have to use FSM's, just get the clocking issues out of the way and you work is cut out for you. PS: Sorry for not posting context, the Google Groups trick does not seem to work anymore. My provider dropped USENET services about 2 weeks ago too :(Article: 96871
Hi Karel, I cannot comment on Microblaze, but we do this with our ERIC5-processor (also in S3E 250/500 design). For better performance, we use 1 BRAM as cache, and the SPI-flash-interface is optimized for sequential accesses. BTW: The ERIC5 needs much less resources than Microblaze, so maybe you could get away with a S3E 250 (if every dollar counts ;-). Regards, Thomas www.entner-electronics.com "Dolphin" <Karel.Deprez@gemidis.be> schrieb im Newsbeitrag news:eaydnWynH7c3IXXeRVn-rQ@giganews.com... > Hello, > > I have the following system: > - A Spartan 3E 500 FPGA > - Some internal BRAM memory > - An external SPI flash > > The external SPI flash contains the instruction code. However I can't use > a bootloader because the internal BRAM memory is not big enough for all > the code. > We don't use an external memory because price is important for this design > (every $ counts). > > I would like to have the Microblaze fetching code from the SPI flash. The > problem is that I have to use the OPB SPI interface for this and this > interface is not a 'real' memory interface. > > Has anyone had a similar problem? How did you solve it? > > Thanks and best regards, > Karel > >Article: 96872
a really stupid question.... so general purpose ports/pins. where are they on the spartan 3 starter kit? so i read that i can just use the jtag pins.. but that doesnt seem like many pins to toggle/twiddle. im used to programming on avr mega 128. where all the ports are obvious. what i sort of think is that i can use any pins on the board as general io? are there some pins that are faster ? i just want to connect it to some DACs. so im thinking ill need at least 20 pins. so i should be using the expansion slots? thanks peterArticle: 96873
look in your documentation! there are TONS of ports on this thing. You define what signal goes to what pin within the ISE... Start the Project Navigator, go to HELP go to TUTORIALS go to ISE QUICKSTART it will open a PDF. It takes about an hour to work through the tutorial, and explains how to set output and input pins on the example 4 bit counter circuit. RichArticle: 96874
in the schematic capture of Xilinx ISE, there is ADD symbol button, which will allow you to pick a component by function, IE : AND NAND MUX COUNTER etc... I want to be able to pick a symbol by 74xxxx digital logic series number. add symbol symbol = 7404 etc. Is this an available option? Rich
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