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I just tried downloading 8.1i SP2, after Xilinx recently
'improved' their download page.
I ended up in an endless loop of :
1) click on download link
2) allow script (IE6 SP2 message).
3) back to starting page with no download
I'd normally right click->save as to get around this, but
the new Xilinx download page uses scripts instead of
direct links to the files, which prevents one from right
clicking to get the complete .exe
It took numerous tries of changing cookie/popup/script
settings before I found the right one:
my original IE6 SP2 settings:
Internet Options->Security->Default Level at "medium"
required change:
Internet Options->Security->Custom Level-> Downloads->
automatic prompting for file downloads to "enable"
Brian
Article: 96976I just begining my work on dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs. I have readed those article sur the site of Xilinx e.g; the guild of configuration , use guid etc. but I havent also any idea for the begining. I wish someone can give me a real exemple or some advices for the dynamic partial reconfiguration of Virtex-4. thanks on advance, xunArticle: 96977
When I saw the little "updated" icon next to the link on Xilinx site, I thought you might have read an older version ;) This particular info has been added in the 1.4 revision from the 24th January 2006. (Check the revision history at the beginning of the document for more details on the changes)Article: 96978
Hi xun, Check out Xilinx's PlanAhead product. Quote:- "New Partial Reconfiguration features and capabilities in PlanAhead 8.1 simplify the implementation of this complex but powerful design flow. Combined with the ISE 8.1i Design Tools, PlanAhead 8.1 delivers the industry's only front-to-back solution for partial reconfiguration." www.xilinx.com/planahead Make sure you report back to let us know how you're getting along! Good luck (you'll need it!) Syms. <zhangxun0501@gmail.com> wrote in message news:1139929097.244112.281090@g44g2000cwa.googlegroups.com... >I just begining my work on dynamic partial reconfiguration of Xilinx > Virtex-4 FPGAs. I have readed those article sur the site of Xilinx > e.g; the guild of configuration , use guid etc. but I havent also any > idea for the begining. I wish someone can give me a real exemple or > some advices for the dynamic partial reconfiguration of Virtex-4. > > thanks on advance, > > xun >Article: 96979
Partial REconfiguration on Virtex-4 using ISE8.1 doesnt work. Good Luck On 14 Feb 2006 06:58:17 -0800, zhangxun0501@gmail.com wrote: >I just begining my work on dynamic partial reconfiguration of Xilinx >Virtex-4 FPGAs. I have readed those article sur the site of Xilinx >e.g; the guild of configuration , use guid etc. but I havent also any >idea for the begining. I wish someone can give me a real exemple or >some advices for the dynamic partial reconfiguration of Virtex-4. > >thanks on advance, > >xunArticle: 96980
Strange! I didn't understand any thing. Perhaps is it because I have influenza (Yesturday I had 40 degrees celcius) and I'm tired. Try to use short sentences. Provide a small piece of code or example plz. I also had another answer to you question when I read the title. But after reading the core of your message I'm lost. Mehdi Matt Clement wrote: > Hello > > Is there a way to setup a bit to be tri-stated so that it can be on a bus > multiplexed with other signals and only becomes active low when being driven > low by the process? How can I setup the bit to be tri-stated or at least > handle it such that it never goes low (and pulls the whole bus low) while > not being driven by my CPLD?? > > Thanks > MattArticle: 96981
Did you repartition your hard drive before reinstalling? if yes you are lost. If no, this means that you reinstalled windows in a different drive than before. The starter license uses the serial ID of the partition on which Windows is installed. There are ways to change the serial ID of a partition using disk utilities (like partition magic for example). Mehdi Sonali wrote: > I am using xilinx Tool Ver 6.3. > And Modelsim 5.8. > Due to some reasons I uninstalled modelsim. > After I installed it again I faced a problem related to license . > ModelSim is installed. and While running it asks for license. > > At licensing Wizard of ModelSim, > I choose a license file which was there previously( we kept a copy of > license file before uninstalling). > > but gives following error msg: > --------------------------------------------------------------- > Driver/Hostid is correctly configured. > > License HostID detection report: > > ERROR : The hostid type -Disk Serial Number- was referenced in the > license file > but does not match the value found on this machine. > -the license file value for Disk Serial Number is: e0ee2059 > -the actual value for Disk Serial Number is: 200e5645 > ---------------- and ----------------- > XE Starter simulator license (xe-starter) > The hostid of the license does not match the hostid for this machine. > One of the following is likely: > -The license is intended for another machine. > -A dongle is not plugged into this machine. > -The dongle driver is not installed or is not functioning properly. > -The hostid mechanism has been changed or removed from this machine. > --------------------------------------------------------------- > > So I go for submit license request where they ask for Disk serial no. > There is a warning that one mistake in serial no. cost u $395 for > re-licensing. > I didn't know what is disk serial no. for Full VHDL. > > I also have a latest copy of ModelSim where also i have to go for > licensing Wizard. > > What is the way to come out from this? > > "Is there any other Simulation tool which is free downloadable and > compatible with Xilinx 6.3 Tool ?" > > Regards, > SonaliArticle: 96982
> Syms, I think the strongest argument for schematics is readability. I still often have to draw out the schematic on an HDL design to fully grok what is going on, and I've been pretty much exclusively VHDL since aroun 1999. On the flip-side, the state of the HDL tools makes it much easier to reuse. It can be done with schematics, but the mainstream tools didn't do a very good job of supporting it. Back when I was an avid viewlogic user (and maybe a rabid one too), I had more or less perfected a system where I got much more reuse than the average bear. My schematics were also much more hierarchical than most, with each level of a design fitting on one sheet, and the low levels consisting of one and two bit slices. I could still use a good HDL to schematic viewer that allows you to hand edit the position of stuff to make it a readable schematic.Article: 96983
Just upgraded to Xilinx ISE 8.1i (a bug for my part in 6.3i resulted in
route errors) and am now getting syntax errors.(!) And neither errorno
gets any hits in Xilinx's Answer Database.
Offending code:
port(...; enable_out: out std_logic;...)
architecture...
signal output_status: std_logic_vector(3 downto 0);
begin
...
enable_out <= '0' when output_status="0010" else '1';
...
end
Error:
ERROR:HDLParsers:810 - "<filename>" Line <linenum>. = has two possible
definitions in this scope.
If I change output_status to std_logic, the error disappears so I
assumed it had to do w/ signed/unsigned so code was changed to:
enable_out <= '0' when output_status=unsigned("0010") else '1';
Which resulted in this error:
HDLParsers:3329 - "<filename>" Line <linenum>. Expression in type
conversion to unsigned has 6 possible definitions in this scope, for
example, std_ulogic_vector and std_logic_vector.
Now entrenched in iterative debugging mode I change the code to:
enable_out <= '0' when output_status=std_logic_vector("0010") else '1';
New/same error:
HDLParsers:3329 - "<filename>" Line <linenum>. Expression in type
conversion to std_logic_vector has 6 possible definitions in this
scope, for example, std_ulogic_vector and std_logic_vector.
Aren't I defining it as std_logic_vector? I want to say it's a bug in
ISE and I've registered w/ Xilinx support, but it'll probably be a few
days before they let me on the server and have a solution.
Also, this happens in processes, too, when comparing vectors in if
statements - if that sheds anymore light.
Anybody seen this? Understand why the error? I considered using
constants for the literals, but I have the same problem elsewhere
comparing dynamic vectors so it's not going to help me there. i.e.:
addr_hit <= '1' when addr(31 downto BASE_ADDR_SIZE) = base_addr(31
downto BASE_ADDR_SIZE) else '0';
Any help/insight/suggestions would be greatly appreciated. Thanks -Matt
Article: 96984Sonali schrieb: > --------------------------------------------------------------- > Driver/Hostid is correctly configured. > > License HostID detection report: > > ERROR : The hostid type -Disk Serial Number- was referenced in the > license file > but does not match the value found on this machine. > -the license file value for Disk Serial Number is: e0ee2059 > -the actual value for Disk Serial Number is: 200e5645 Change the volume ID back using this tool: http://www.sysinternals.com/Utilities/VolumeId.html This reminds me of a great phone conversation with an Insight Memec representative who refused to register 20 licenses of FPGA Express to volume ID 1111-1111. (We used to use volume ID 0000-0000 for all our drives, but a bug in FlexLM prohibits that) We ended up registering only a single license, used that on all machines and kept the other licenses unregistered. Stupid. Kolja SulimmaArticle: 96985
Hal Murray wrote: > >Lastly, I have noticed that simple designs seem to download more > >reliably than larger designs. Not sure why, as the programming file > >should be of equal length either way (though there may be a lot of zero > >padding in the smaller files) > > Have you tried a scope on the clock/data lines? > > Is this the same byteblaster you used back when it worked? > A newer PC might be a bit faster or there might be just a bit > more crosstalk on the cable or ... > Unfortunately, the project that the board was originally used for has long since ended. The PC was leased, and has since been returned, and I have no idea where the byteblaster we used then went. That does remind me, though - we originally had a Byteblaster II, not a Byteblaster MV. The original byteblaster used a slower '244 - LS family I think. That *shouldn't* be a problem, but I can try swapping the chip. I will try looking at the signals on a scope. I'm kind of flying blind without a scope at home, but I can take it to work and check out the signals.Article: 96986
Do you have the DCI references setup and plugged in properly? If so, you should use the LVDCI. LVCMOS is probably your next best bet unless you have reference voltages plugged into the chips, which most board vendors tend to ignore. The SGI box I have runs HSTL_DCI at 200MHz SDR without an issue. I'm able to DDR LVCMOS at 50MHz on lines of two inches or less without an issue. It works better than LVTTL at that speed. Unfortunately, I'm sure your bus is way longer than that. I think you would definitely need some termination. Hopefully you can use the DCI for all the V2 connection termination. It's unlikely your board has chip termination built in. For Point to Point, (when I cannot use LVDS) I send a clock along with the data (using an FDDRSE with constants on the data) and then an IBUF delay on the incoming clock before sending it to all the IOB register clock inputs. I also send an enable with the data a busy signal back the other way plugged into an almost-busy signal on the receiving fifo. I usually end up with a dual clock domain fifo on each end. If your distance is longer than a few inches, you will likely need to add a DCM to the outgoing clock and adjust the phase. That gets to be a real pain if you have a lot of chips. 66MHz DDR is the hairy edge of too fast for LVCMOS.Article: 96987
"Ray Andraka" <ray@andraka.com> wrote in message news:WMmIf.62387$bF.21574@dukeread07... > Syms, I think the strongest argument for schematics is readability. I > still often have to draw out the schematic on an HDL design to fully grok > what is going on, and I've been pretty much exclusively VHDL since aroun > 1999. Ray, yeah it's interesting to hear what works well for different folks. After about 8-9 years of almost exclusively doing HDL designs, I've found myself doing a fair bit of maintenance on some viewlogic stuff over the last month or so, and, for readability, I've found myself doing the same as I do for VHDL, i.e. drawing timing diagrams to work things out. It's got to the point where I've looked (unsuccessfully) for tools to do some PCB design entry using VHDL. I'm getting sick and tired of drawing a bunch of rectangles with hundreds of wires coming off them to represent an FPGA. Also, adding each and every bypass cap. If I could use VHDL for this, I could cut and paste a lot of the pin information from the data sheet to be more accurate and quicker. Of course, for analog electronics this makes little sense, but it would be nice to be able to mix and match the two entry methods. Cheers, Syms. p.s. This is a useful link which automates some of the symbol creation tedium. http://www.fpga-faq.org/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htmArticle: 96988
Hi, Thank you for the reply, but I use XPower in the command line mode, and hence would like to know what command line switch I could use to improve the precision of the power values shown. AltafArticle: 96989
Check the data sheet for your part. Some parts will allow for true
*internal* tri-states, while others do not. For example, a Xilinx 4000
series FPGA will do true internal tristates, while neither the Virtex
nor Spartan series FPGA will not.
For parts that do support it, you will need to add a line like this
(for VHDL):
TSTATE_BUS <= My_bits when Enable = '1' else (others => 'Z');
Note, you can still do this even in later families, but the compiler
will turn it into a mux - so be careful. If you aren't aware of that
behavior, you can be surprised on large designs with low LUT margins.
Note, I have seen some IP cores that use an 'OR'ed bus structure to
solve this problem. With an OR type bus, you just drive zeros when not
enabled:
arcitecture rtl of sample is
-- To simplify the OR logic, make these the same width. Your
compiler/synthesizer should optimize away bits you don't need - while
still making the correct connections. Just load the registers you DON'T
need with a constant value.
signal My_Bus_1_d, My_Bus_1_q : std_logic_vector( BUS_WIDTH_MINUS_1
downto 0 );
signal My_Bus_2_d, My_Bus_2_q : std_logic_vector( BUS_WIDTH_MINUS_1
downto 0 );
-- Don't worry too much about the My_Data_n busses - you can pad the
bus when you feed it to My_Bus_n_d;
signal My_Data_1 : std_logic_vector( 3 downto 0);
signal My_Data_2 : std_logic_vector( 15 downto 0);
begin
-- You need one of these per *readable* register/entity
My_Bus_1_d <= My_Data_1 when Enable_1 = '1' else (others => '0');
My_Bus_2_d <= My_Data_2 when Enable_2 = '1' else (others => '0');
-- To keep your combinational logic path to a minimum, register each
"My_Bus". This isn't necessary, and does add an additional clock of
latency, but if your timing is marginal, this will help.
S_Regs : process( Reset_n, Clock )
begin
if( Reset_n = '0' )then
My_Bus_1_q <= (others => '0');
My_Bus_2_q <= (others => '0');
elsif( rising_edge(Clock) )then
My_Bus_1_q <= My_Bus_1_d;
My_Bus_2_q <= My_Bus_2_d;
end if;
end process;
-- Then, you need _only_ one of these somewhere in the code to "mux"
the bus together.
for i in BUS_WIDTH_MINUS_1 to 0 loop
OR_BUS(i) <= My_Bus_1_q(i) or My_Bus_2_q(i);
end loop;
end rtl
This is fairly resource intensive, but it is fast, and explicit. To
improve performance, I would suggest registering My_Bus_n as shown -
unless your design has few readable registers - or you can tolerate the
long combinational paths. BTW - if you look closely, you will see that
this only handles the READ portion of your bus. Use a separate bus for
handling writes. Not only will this improve performance, since you
don't have to simulate bus turnaround, but you don't need any muxing at
all for a WRITE bus - just clock enables on the registers. Saves a lot
of grief in the long run.
Good luck!
Article: 96990I have another question regarding the PLB-OPB, the PPC405 reference guide says that the PLB should be used for fast bus transactions and that the OPB is to be used for slower peripherals (GPIOs/UART etc.). My question is as follows - If I'm using a PLB-OPB bridge the data from/to the OPB will still go trough the PLB bus so how come it is says the the OPB usage takes some load of the PLB bus ? Thanks, Mordehay.Article: 96991
Hi Altaf, Have you tried the TCL commands ? There are "setPowerUnit" and "setCurrentUnit" commands available. Brendan <the.gaffar@googlemail.com> wrote in message news:1139933650.901422.280010@g44g2000cwa.googlegroups.com... > Hi, > > Thank you for the reply, but I use XPower in the command line mode, > and hence would like to know what command line switch I could use to > improve the precision of the power values shown. > > Altaf >Article: 96992
"rickman" <spamgoeshere4@yahoo.com> wrote in news:1139919710.627526.242240@f14g2000cwb.googlegroups.com: > Good point. I am working on a project that needs to meet the RoHS > standards and one of the parts from our existing product that we can't > use are kapton flex circuits. I have no idea why kapton is on the > list of banned items. Does it have to do with the way it is made? > > David Brown wrote: >> It's also worth pointing out that although people use the term "lead >> free", that's only a part of RoHS and similar directives. There are >> a number of other metals and chemicals banned or limited by RoHS >> which are more poisonous than lead, although they are lower volumes >> in electronics. >> >> The theory is nice - it's a step towards being a bit more >> environmentally friendly. The implementation is a lot more >> questionable "let's set some rules, and a deadline with plenty of >> time, and 'market forces' will find a solution". It would have been >> far better to have graduated commercial incentives - start with >> grants for companies willing to switch over early as "prototypes" for >> the industry, and then move to gradually increasing taxes on leaded >> components and electronics until everyone has switched over. > > I agree that it would have been better to phase in the process, but > that would still have been painful and a LOT more work to manage. > > I think the biggest problem with the mandates is that it mostly and all or nothing proposition. If the board didn't use lead solder, this would reduce most of the lead content on a typical board. It would be very easy to make a board that reduces its lead content by 90% without much impact on existing inventories and designs. The biggest problem is caused by the few parts that are not readily available (in theory or otherwise) that cause the board to be almost but not quite RoHS compliant. I brought up the Altera parts as an example since many of the people in this group might have exactly the same problem. If I use an Altera PLD which I have (and can still buy), that is not leadfree, my board will not be RoHS compliant. I also wonder what they expect us to do with all of our inventory. The big problem is that the manufacturers of the parts needed to be completely RoHS compliant at least a year or maybe even two years ago, so that the distributors could turn their stock and then endusers like most of us could turn our stock. I was seeing passives that were still non RoHS as late as Fall 2005. In some cases, I use one resistor of a reel per run. It takes a long time to burn 5000 parts for some of us. I had a connector manuafacturer tell me that the 5 cent connector I buy from them is not RoHS but that I could get it RoHS if I bought 20000 pieces. I use about 3000/year. Sometimes, I think that the Europeans think that all products are like consumer items that have a product life of a few months or maybe a year (like a PC or cell phone). I have already seen many products being redesigned simply because a key part will not be available in a RoHS compliant package (and would have been otherwise). The manufacturer decides that the part volume isn't worth the effort to modify so they kill it instead. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 96993
Yes, so am I. There are many bugs in ISE 8. I frustated with creating TBW.Article: 96994
Hi Brendan, No I havent tried the TCL settings for XPower Is there some documentation available for this ? Many Thanks AltafArticle: 96995
> Sometimes, I think that the Europeans think that all products are like > consumer items that have a product life of a few months or maybe a year > (like a PC or cell phone). Al, Please don't tarr us all with the European 'politician's brush, they just _don't_ think. A couple of weeks ago someone on sci.electronics.design (I think) posted a link to a presentation that quoted TI's figures, that a worldwide conversion to lead free packages would save about the same amount of lead as in TEN car batteries. The european parliament is a complete waste of time and a huge waste of money. Nial.Article: 96996
Hi Rob,
Check this website
http://www.digilentinc.com/Products/Detail.cfm?Prod=XUPV2P&Nav1=Products&Nav2=Programmable..
On this website, you will find a sample design in the "Quick start"
section..
But I am not sure the about the version of Modelsim that
can be used to simulate..We use Modelsim SE..
--
Parag
Article: 96997radarman wrote: > Check the data sheet for your part. Some parts will allow for true > *internal* tri-states, while others do not. For example, a Xilinx 4000 > series FPGA will do true internal tristates, while neither the Virtex > nor Spartan series FPGA will not. Actually they do have. Spartan2 spartan2E virtex and virtexE they all have BUFT (or TBUFS) parts without BUFTs: virtex2/pro virtex4 spartan3/3E Aurash > > For parts that do support it, you will need to add a line like this > (for VHDL): > > TSTATE_BUS <= My_bits when Enable = '1' else (others => 'Z'); > > Note, you can still do this even in later families, but the compiler > will turn it into a mux - so be careful. If you aren't aware of that > behavior, you can be surprised on large designs with low LUT margins. > > Note, I have seen some IP cores that use an 'OR'ed bus structure to > solve this problem. With an OR type bus, you just drive zeros when not > enabled: > > arcitecture rtl of sample is > > -- To simplify the OR logic, make these the same width. Your > compiler/synthesizer should optimize away bits you don't need - while > still making the correct connections. Just load the registers you DON'T > need with a constant value. > signal My_Bus_1_d, My_Bus_1_q : std_logic_vector( BUS_WIDTH_MINUS_1 > downto 0 ); > signal My_Bus_2_d, My_Bus_2_q : std_logic_vector( BUS_WIDTH_MINUS_1 > downto 0 ); > > -- Don't worry too much about the My_Data_n busses - you can pad the > bus when you feed it to My_Bus_n_d; > signal My_Data_1 : std_logic_vector( 3 downto 0); > signal My_Data_2 : std_logic_vector( 15 downto 0); > > begin > > -- You need one of these per *readable* register/entity > My_Bus_1_d <= My_Data_1 when Enable_1 = '1' else (others => '0'); > My_Bus_2_d <= My_Data_2 when Enable_2 = '1' else (others => '0'); > > -- To keep your combinational logic path to a minimum, register each > "My_Bus". This isn't necessary, and does add an additional clock of > latency, but if your timing is marginal, this will help. > > S_Regs : process( Reset_n, Clock ) > begin > if( Reset_n = '0' )then > My_Bus_1_q <= (others => '0'); > My_Bus_2_q <= (others => '0'); > elsif( rising_edge(Clock) )then > My_Bus_1_q <= My_Bus_1_d; > My_Bus_2_q <= My_Bus_2_d; > end if; > end process; > > -- Then, you need _only_ one of these somewhere in the code to "mux" > the bus together. > for i in BUS_WIDTH_MINUS_1 to 0 loop > OR_BUS(i) <= My_Bus_1_q(i) or My_Bus_2_q(i); > end loop; > > end rtl > > This is fairly resource intensive, but it is fast, and explicit. To > improve performance, I would suggest registering My_Bus_n as shown - > unless your design has few readable registers - or you can tolerate the > long combinational paths. BTW - if you look closely, you will see that > this only handles the READ portion of your bus. Use a separate bus for > handling writes. Not only will this improve performance, since you > don't have to simulate bus turnaround, but you don't need any muxing at > all for a WRITE bus - just clock enables on the registers. Saves a lot > of grief in the long run. > > Good luck! >Article: 96998
Hi Brendan, I was able to get the required result using your suggested method. Many Thanks AltafArticle: 96999
This is the vector diagram for 75% colorbars. Can you explain more about composite sweeps? Thank you, Methi
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