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Hi, I have a Spartan 3 starter board and NET1 ethernet daughter card. I was expecting to use NET1 to connect the starter board to ethernet LAN. According to Xilinx tech support the NET1 card can be used only for transferring data between a PC and the starter board, but not for connection as a host on a LAN. Does anybody have a suggestion on how to make the Spartan 3 starter board a host on a LAN? Also, how can we connect a USB camera device to the Spartan 3 starter board? What hardware and software are required for this purpose? maliArticle: 98626
Antti Lukats wrote: > "Jake Janovetz" <jakeREMOVEjanovetz@REMOVEyahoo.com> schrieb im Newsbeitrag > news:dv4h09$hp6$1@wildfire.prairienet.org... > > I, too, prefer command line tools for many things. Unfortunately, when I > > moved to Windows out of necessity (CAD software mainly), I realized that > > the environment is just CL-hostile. > > > > Customers and clients like to get nicely packaged projects that are easy > > to startup and rebuild. IDEs favor that. > > > > Also, I've taken a new appreciation to well-designed IDEs. They can save > > a lot of time for those of us that spend our day shuffling among dozens of > > tools. I just don't have the bandwidth any more to learn all the options > > and remember them for so many tools and languages. A good IDE is nice. > > Xilinx ISE tools are by far the worst tools I use at the moment. > > > > They should completely ditch their ISE line and build an Eclipse plugin > > for their stuff. Eclipse is a fantastic environment. > > ROTFL - the want do that !! just for 8.1 they did major rework to have what > they is better, so I am pretty sure they will stick with their new GUI for > some while. > > Eclipse is nice, and yes that would real nice if all IDEs would be eclipse > based, but hum I havent ever checked that, I was told that Eclipse is too > slow on linux machines? It is. I (now) use it for Python development. I find the beginning interface to be very slow. After that it runs fine. I am using a P3 Tualatin 1.13Ghz and 512MB of ram. Now I dont think that thing is too slow for an IDE. I havent tried it on my 2.2Ghz AXP. > maybe that guy who told me that (only a few week > ago) needs a real computer and then eclipse will be ok with speed as well. haha, I guess my previous claims substantiate that. > Antti -IsaacArticle: 98627
Paul van der Linden wrote: > Eli Hughes wrote: > >> The QFP devices (VQ100, TQ144 and PQ208) are do-able with some >> practice with a standard soldering iron and some wick. > > How thin should the soldering iron be? Weller has some micro-pencil irons like the EC1302 (vintage) and the WMP (current). They have conical pointed tips for all of these, that essentially go to a real point. You wipe the iron gently down the row of leads, touching both the end of the lead and the solder pad at the same time. If the right amount of solder paste is used (very sparingly) the surface tension will break the bridge of solder as you work down the side. There will be a bridge between the two leads that the soldering iron is on at any one time, but the iron pulls it along as you move. The alignment takes a couple of minutes, then the soldering goes very quickly. > >> Your best best is to get a development board to experiment. If you >> need a standard alone module check out the Avnet Virtex 4 Mini module >> or the devices from Xess. > > The problem with the standard development board, is that they are > expensive (starting from 150 dollar or something). But I think I will > buy one. > > And I was also thinking of the feature, I want to be able to make my > own devices, and using start kits for a final devices isn't right. > I've never used the starter kits, either. JonArticle: 98628
Hi all, Can I create an EDK based system containing both a PPC and MB while connecting debug peripheral to both of them at the same time (via jtag->xmd->gdb) ? (mdm for MB and jtag debug port for PPC). Thanks, Mordehay.Article: 98629
aiiadict@gmail.com wrote: >how about a BGA to DIP converter socket? > >or, a BGA part pre-soldered to a board with >through-holes for attaching connectors, wires, >etc? > > It really won't work. You could put the necessary decoupling capacitors on the adaptor, but what DIP would you use? The original post was talking about 480 pin devices! > > JonArticle: 98630
<sachink321@gmail.com> schrieb im Newsbeitrag news:1142270059.172147.157840@z34g2000cwc.googlegroups.com... > hi > im using digilab XCR development board which has Xilinx XCR3064 > CPLD. > I/O pins in this CPLD are said to be tristate. > but when im trying to use them as tristate > its not working as one? > i mean i want one of the I/O pin to go high impedance but its not? > can any one tell me how can i make I/O pin in CPLD high impedance? > Fitter standard I/O termination is bus keeper. You can select pullup or float. If you float the pins (in the implementaion-fitter properties), you must insure, that no input pin is unconnected and floating. MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 98631
Isaac Bosompem wrote: >> Eclipse is too slow on linux machines? > It is. I (now) use it for Python development. I find the beginning > interface to be very slow. After that it runs fine. I am using a P3 > Tualatin 1.13Ghz and 512MB of ram. Now I dont think that thing is too > slow for an IDE. I havent tried it on my 2.2Ghz AXP. Eclipse is based on Java, so if your JVM hasn't started yet, there will indeed be a very noticeable delay, on any machine. Best regards, BenArticle: 98632
Jim Granville wrote: > You could say core memory still lives on : in FRAM devices = > identical property of magnetic domain storage with destructive read - > only they > are now manufactured on a wafer, with additional process steps to > insert the magnetic domain material, instead of physically wired. FRAMs are not magnetic. They use the ferroelectric effect, which is somewhat of a misnomer. They are like core only in that readout is destructive, but the available FRAM chips handle the rewrite internally. You're probably thinking about MRAMs, which are magnetic. Freescale (formerly Motorola) introduced the MR2A16A 4 Mbit MRAM some time back, but it still doesn't appear to be available through distribution. http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MR2A16A&srch=1 > [ Bubble memory seems to have hit an evolutionary dead end..] Yes. It worked, but it didn't scale down well, and it was very slow. Commercial devices were made by Hitachi, Intel, TI, and Rockwell. The highest density part was the Intel 7114, which was a 4 Mbit part. There have been some reports lately that MRAM won't scale well, and thus may also be a dead end. But I think it's too early to write it off. Many years ago it was claimed that FRAM would be able to achieve comparable densities to DRAM, but that certainly ahs not happened. Currently highest density NAND flash parts are 8 Gbit. FRAM and MRAM thus have only 1/2048 the density of NAND flash, but are fully random access and have fast read and write times. NAND flash is generally only suited to secondary storage applications (like disk). > I also see Intel reckons Ovionic (phase change) memory might yet fly... Samsung and SGS are reportedly working on that as well. Samsung apparently produced samples of a 64 Mbit chip in 2004.Article: 98633
Andy Peters wrote: > PS: Altera's no better. Nor Lattice. Umm, I beg to differ!!! First of all, the project files are all text-based, and we've been using SVN very successfully for Quartus projects. Thanks Altera! Secondly, all intermediate files are created in the 'db' directory, which minimises the pollution of the project directory. Granted, the build process output files (reports, programming files) are in the project directory, but there's only a handful of them and you know you only really need to backup *two* files in that directory. Thirdly, source files are referenced from their original directories. We've used common source directories across multiple projects without any problems. OK, I'm going to completely back down here on SOPC Builder and the NIOS IDE. The only excuse I'm going to make for them is that they are (relatively) immature products and hopefully issues such as directory/source file management will be improved. <RANT> And Eclipse - I *hate* it with a passion, a piece of rubbish and I absolutely refuse to use the editor - even on a 3.2GHz machine with 2GB RAM it's *way* too slow! And IMHO any tool writer these days who uses binary configuration files needs a very strong backhander across the face (pain is not enough, there needs to be some element of humiliation as well). It's just plain lazy, and *more* than just a pain in the butt for the user. </RANT> OK, I've got that off my chest... -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 98634
Jim Granville skrev: > Jake Janovetz wrote: > > I, too, prefer command line tools for many things. Unfortunately, when > > I moved to Windows out of necessity (CAD software mainly), I realized > > that the environment is just CL-hostile. > > > > Customers and clients like to get nicely packaged projects that are easy > > to startup and rebuild. IDEs favor that. > > > > Also, I've taken a new appreciation to well-designed IDEs. They can > > save a lot of time for those of us that spend our day shuffling among > > dozens of tools. I just don't have the bandwidth any more to learn all > > the options and remember them for so many tools and languages. A good > > IDE is nice. Xilinx ISE tools are by far the worst tools I use at the > > moment. > > What about the (radical?) idea of the IDE setting the options, and > then creating a full command line batch file as well. (they must do this > already, in pieces ) > You used to? be able to kinda do that , you just had to read though the log files to find the commands needed to pick the right files and put that in to a .bat file. I generally just have a bat file to do the syn,par,bitgen and promgen. and another bat file to program proms. > In an ideal setup, it would be able to READ the batch files, and > flip the options to match. > > That way, you get full two way movement between GUI and Commandline > operation. > > If Xilinx WERE serious about version control, they would know the > only way to ENSURE an identical build is to remove the GUI from the > loop. > They should provide better support for when a project goes into > "don't break it" maintenance mode. > > -jg -LasseArticle: 98635
langwadt@ieee.org wrote: > Jim Granville skrev: > > >>Jake Janovetz wrote: >> >>>I, too, prefer command line tools for many things. Unfortunately, when >>>I moved to Windows out of necessity (CAD software mainly), I realized >>>that the environment is just CL-hostile. >>> >>>Customers and clients like to get nicely packaged projects that are easy >>>to startup and rebuild. IDEs favor that. >>> >>>Also, I've taken a new appreciation to well-designed IDEs. They can >>>save a lot of time for those of us that spend our day shuffling among >>>dozens of tools. I just don't have the bandwidth any more to learn all >>>the options and remember them for so many tools and languages. A good >>>IDE is nice. Xilinx ISE tools are by far the worst tools I use at the >>>moment. >> >> What about the (radical?) idea of the IDE setting the options, and >>then creating a full command line batch file as well. (they must do this >>already, in pieces ) >> > > > You used to? be able to kinda do that , you just had to read though the > log files to find the commands needed to pick the right files and put > that in to a .bat file. That's what I meant by doing it already in pieces - users should not have to do this stuff, that's a job for the tool designer. The tools KNOW all this information, and the tool designer should do once, what many users must now do, over many projects.... Still, it does reflect the reality that those that code these tools, do not actually _use_ them. -jgArticle: 98636
On Mon, 13 Mar 2006 13:25:55 -0600, Jake Janovetz wrote: > I, too, prefer command line tools for many things. Unfortunately, when I > moved to Windows out of necessity (CAD software mainly), I realized that > the environment is just CL-hostile. You can use Cygwin on Windows to get a Bash or Tcsh shell which you can use to run the same scripts that you would run on a real operating system. It's not quite the same as using Linux but it will allow you to avoid the GUI.Article: 98637
Hello everyone, I managed to snag one of the freebie Xilinx Spartan 3e sample pack boards, and while the board came with ISE 7.1, I discovered the ISE 8.1 Webpack came with a lot of nice extras, like coregen. The problem is that a lot of the IP's in the coregen don't work. I checked the app note about paths with spaces in them, and reinstalled to a folder that didn't have any. (I installed ISE to C:\projects\xilinx). The project I'm working on is in C:\projects\cores. Based on that, it appears the note is no longer applicable. Except that I still see an error message when I try to create certain cores: "ERROR:coreutil:4 - Couldn't open "C:\Projects\FPGA Stuff\Playground\Cores\tmp\_cg\xil_804_9.in" for writing." I also checked the Java memory allocation, and set it to 512Mb, although it doesn't seem to matter. (I saw an app note about memory allocation on NT based systems - and I'm using Windows XP) The weird part is that some things work fine, and others don't. For example, I can create a FIFO, but not a block memory. I can build a floating point unit, but not a MAC. Has anyone else seen this? Thanks, -SethArticle: 98638
Jake Janovetz wrote: >I, too, prefer command line tools for many things. Unfortunately, when >I moved to Windows out of necessity (CAD software mainly), I realized >that the environment is just CL-hostile. www.cygwin.com would be a good starting place. >Also, I've taken a new appreciation to well-designed IDEs. They can >save a lot of time for those of us that spend our day shuffling among >dozens of tools. Bob Perlman wrote: >> A question for the many folks who use the IDE: what does it really buy >> you that the command tools don't? If I'm doing something quick I may fire up the GUI. If I do it a second time, I'll write a makefile. -- Phil HaysArticle: 98639
"radarman" wrote: > "ERROR:coreutil:4 - Couldn't open "C:\Projects\FPGA >Stuff\Playground\Cores\tmp\_cg\xil_804_9.in" for writing." If there is a space between "Projects\FPGA" and "Stuff\...", then some of the tools will break. No spaces, it should work. -- Phil HaysArticle: 98640
Michael Sch=F6berl wrote: > > imho, fpga makers have dropped the ball, by totally ignoring the > > enormous markets of various mixed-signal products; where 5v is VERY > > common...along with generally noisy environments. > > you are right ... not every application needs a high end FPGA! > we even use some of the old Spartan XCS40 - you can still buy them but > ISE support was dropped long time ago :-( Yes, you can get the old parts. I have even seen XC30xx parts on Digikey. But I don't think it is a good use of $$$ using old, expensive parts to get 5 volt tolerance. There are a few current parts that are 5 volt tolerant to some extent. The Xilinx Coolrunner CPLD parts (not II) have a limited number of 5 volt tolerant IO and Lattice has some 5 volt tolerant parts (again a limited number of IO) that just came out in the last couple of years or so. But these are not great parts in other ways. The FPGA market follows the telecom world, which is where their bread and butter come from. They can sell their really large parts there with all the exorbitant markup of the state of the art parts and telecom needs the flexibility of FPGAs to get state of the art designs on their boards with a short turn around. Telecom also drives the speed of the FPGAs which is what makes them use the latest processes without the mods that the ARM CPU makers use to retain 5 volt tolerance. So in the end telecom "owns" the FPGA vendors and the rest of us are just a secondary market.Article: 98641
I tend to use the GUI at this point, but regardless of your opinion of IDE vs command line, I think Xilinx' trend to using binary for the project files shows some cluelessness on their part. The complaints voiced here about the problems with the binary files have bitten me also, and they are truly irritating. Xilinx, please use the registry to store info instead of binary files. JUST KIDDING. It's only slightly stupider than shifting to binary files. Why is it each of the Xilinx software releases seems to be one step forward in some senses and two steps back in others? Why don't they hire some of the experts from this group as a focus group to review proposed changes to their software before they make it worse? Xilinx does a lot of things very well, it's too bad their s/w releases are only so-so. John ProvidenzaArticle: 98642
Hi Jake, the change to .ise project files annoyed me too and gives me the final kick to change to skripted flows. What makes me wonder is that no one in this thread mentiones the XFLOW tool. As I understand it XFLOW can create the basic scripts for different flows. Once the script is created you can edit it and it surely saves you a lot of space in your version control system. Since I'm occupied by some other work at the moment I had no time to test it yet. Does anyone else have experience with the XFLOW tool? Regards EilertArticle: 98643
Hi all, Post-Place & Route Simulation is ok now (I had some warnings due to data glitches but I fixed it and everything works fine). Anyway there is no progress with the board :( Do not know what I could possibly do. It seems without an osci I am really lost. Or someone has an idea? I would be really glad to hear any suggestions! Best, AdaArticle: 98644
Bob Perlman <bobsrefusebin@hotmail.com> writes: > I agree: I use the command line tools, which leaves me free to use any > source control system I want. Ditto. I only use the command line tools, execpt the fpga-editor, and have no problems with CVS. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 98645
Petter Gustad <newsmailcomp6@gustad.com> writes: > Bob Perlman <bobsrefusebin@hotmail.com> writes: > >> I agree: I use the command line tools, which leaves me free to use any >> source control system I want. > > Ditto. I only use the command line tools, execpt the fpga-editor, and > have no problems with CVS. I forgot to say that I use Linux and write my own Makefiles. It takes a little time to set this up for the first time, but after that everything is great. Just cvs checkout, make, and your FPGA contains the new bitstream some time later... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 98646
I received a design from a vendor, which is designed for Virtex 2 FPGA. In the design there are four instances of RAMs, which are of DPRAMs of 16bX4096w each. (In fact, there are no WRITE events to these RAMs throughout simulations.) In the test bench, a FOR loop reads in some ASCII files and pumps into RAMs at beginning of each simulation. Now when I convert this portion into ASIC using library RAMs, how should I take care of this? Thank you for your comments.Article: 98647
fpga schrieb: > Thanks very much, John. My ram size is 256x32 and I want it has 4 read > ports and 3 write ports. > The ram is gonna to be used as the local > vector register file in my vector coprocessor. My vector coprocessor > has different function cores, each has its own local vector register > (LVR). So these LVR need to provide ports to the function unit(2 read > ports, 1 write ports) and ports for transfer LVR data between this > cores (2 read ports, 2 write ports). I choose 2 read ports and 2 write > ports for data transfering because I believe it can bring much better > performance than 1 read port/1 write port design. > > Also, multiple ports RAM (I don't decide the size and ports number yet) > will be used as the register file in superscalar machine. For vector units you can simplify things a lot. For example you could have a scoreboard that keeps track of which of three rams contains the most recent entry. For random access this is unpractical because this logic needs three write ports itself. For a vector unit you can update that register in (the simplest case) three extra clock cycles after each stride. This results in 3+N cycles which usually is a lot better than the 2xN of a multi cycling approach. Kolja SulimmaArticle: 98648
Novice wrote: > I received a design from a vendor, which is designed for Virtex 2 FPGA. > In the design there are four instances of RAMs, which are of DPRAMs of > 16bX4096w each. (In fact, there are no WRITE events to these RAMs > throughout simulations.) > > In the test bench, a FOR loop reads in some ASCII files and pumps into > RAMs at beginning of each simulation. > > Now when I convert this portion into ASIC using library RAMs, how should > I take care of this? > > Thank you for your comments. If it is never written it is rom not ram .... -LasseArticle: 98649
Hi Ada, ask Avnet if there is some DDR controller IP core evaluation bit stream available for the board so that you can check whether DDR memory accesses are possible and correct at all. If they are correct then you know at least that you have to analyze your own controller. Rgds Andr=E9
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