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John, How much is Altera paying you? AustinArticle: 98901
Without EasyPath any production device with any known defect (that is not covered by an errata note) goes into the garbage can. That has been and will remain our policy, and I assume the policy of any reputable IC manufacturer. EasyPath allows us to test only the relevant subset of the chip's functionality (as needed by the specific user). This increases yield for large devices significantly (hardly any gain for small chips), and that higher yield means lower cost to us, and supports a lower selling price. This should be understandable to anybody with a high-school education. Peter AlfkeArticle: 98902
fpga_toys@yahoo.com wrote: <snip> > Assuming Xilinx's yields are not totally tanked, it seems that if they > are willing to sell minimally tested devices for the best possible > prices, then there is a market for 3rd parties to do the testing and > screening, leveraging the volumes and margins over several > products/customers. Hmm - you mean grey market parts, like plagued Intel ? Q: How are these parts labeled, that would be one obvious difference ? Tho that, of course, will not stop the truly dishonest.... -jgArticle: 98903
hi, thanks for the quick replies. the dots werenot completely random. they lined up on my screen. how do i test if i am pushing the memory too much? the theoretical max. speed is 166Mhz. I use 100Mhz. I dont think that should be pushing the limit but is it possible it is? thanks Isaac Bosompem wrote: > Subhasri krishnan wrote: > > Hi all, > > I am having problems debugging my memory controller. My initial idea is > > to capture a frame and display the same frame continuously. But I see > > problems in the pattern captured (some spots with colours that arent > > expected to be there). When I simulate the controller it works as it is > > expected. I understand that the timing has to be right and I modified > > everything so that its alright. The input pattern is a simulated timing > > generator to generate vga timing (640 x 480 @ 60Hz). > > > > I think that the problem lies with an asynchronous fifo used to buffer > > data at 25Mhz. The controller can take data from here at 100Mhz and > > write into memory. Can anyone see a potential problem with this? I use > > an async fifo for output buffering and there is no problem here. Also > > can i use 2 clocks in the same module? some 'always' loops operating at > > 1 clock and the others at another clock? > > > > Can someone think of a test that I do to figure out the problems? I > > tried using different lenght fifos, with and without fifo and digging > > into memory location and can do some minor corrections but I am not > > able to spot any major mistake. > > Any help is greatly appreciated. > > > > > > Thanks > > Subhasri.K > > I am not understanding what you are saying. See if I am correct: > > - You are having trouble with your memory interface (to a framebuffer). > - The memory controller is running at 4x the dot clock (100Mhz) > - There are bad pixels in certain areas? > > If so then I would suggest looking at the VHDL code that is responsible > for reading in the data and placing it into an internal buffer in the > FPGA. The random wrong dots suggest this would be a problem (it could > also suggest that you may be pushing the memory too far). > > -IsaacArticle: 98904
Peter Alfke wrote: > This should be understandable to > anybody with a high-school education. > Peter Alfke hmmm just like putting a yellow sticker on $10m of perfectly good parts, and calling them lemons to justify a sale below cost? I think anybody with a high school education can figure that one out too. It also seems like a perfectly good scam for your production department to take perfectly good tested parts, and ship them under the easypath program for a huge kickback. How can you montor employee fraud with such a dual labeling program with 80% discounts?Article: 98905
Austin Lesea wrote: > Metal, > > Pessimists always claim they are just observing reality. > > You must be working for one of those companies "circling the drain?" > > Really hard to be positive about anything. > > > I see (our) business increasing (a lot), and I see margins that are > good, and getting better, and I see new opportunities popping up all > over the place. And I see the financials that support it. > > You have told all of us how we will need food, shelter, and a few sticks > to burn here in the not so distant future. > > Austin Austin, it is hard to believe that no one at Xilinx has ever reigned you in. Often your posts are useful and technically sound. But concepts of customer interaction and company representation seem to be lost on you. I was not even involved in this thread and I find your post to be insulting as well as totally inappropriate. Your "ad hominem" attacks seem to occur anytime someone makes a technical argument that might be hard to dispute. To be honest, my impression of Xilinx has changed a lot over the last few years, partly due to your postings here. Initially I did not pay a lot of attention to your comments to me or others until I realized that you are actually fairly influential in the company. Now I realize that Xilinx as a whole is not a lot different than the image you present and it bothers me. It bothers me enough that I now have a strong preference for any other FPGA manufacturer. I think the fact that no one at Xilinx seems to have a problem with your posts like this one says a lot about the company.Article: 98906
Are we continuing this thread until John (aka Mr Toy) has made a complete fool of himself ? His ranting is neither coherent nor entertaining or amusing anymore. Peter AlfkeArticle: 98907
Hello, Does anybody out there actually know how to set up HWICAP in EDK? Has anyone ever got this to work? If you've ever looked into this, you know there's very little documentation on how to setup and use HWICAP. Would someone please post a C file instantiating, initializing, and perhaps even reading/writing a frame through ICAP? That would be extremely helpful. I am but a lowely univerisy student, and as such get zero support from Xilinx on these or any other matters. Thanks much, --scottArticle: 98908
OK, I agree. I'm off to doing more useful things. Austin Peter Alfke wrote: > Are we continuing this thread until John (aka Mr Toy) has made a > complete fool of himself ? > His ranting is neither coherent nor entertaining or amusing anymore. > Peter Alfke >Article: 98909
Peter Alfke wrote: > Isn't that obvious? > If the product costs us half as much to make (higher yield), then we > can sell it for half the price, and make the same perent margin. > Margin is always expressed as a percentage. There is no other way. > I really thought that everybody would understand that... > Peter Alfke There is margin and there is ROI (return on investment). In a business that is capital intensive, ROI is as important, if not more important than margin. The fact that Xilinx is fabless does not change the distinction. Your vendor will not charge the same per wafer if you are buying half as many wafers. So in reality doubling the yield will not cut your costs in half.Article: 98910
<fpga_toys@yahoo.com> wrote in message news:1142623881.479071.57680@j33g2000cwa.googlegroups.com... > > Peter Alfke wrote: >> This should be understandable to >> anybody with a high-school education. >> Peter Alfke > > hmmm just like putting a yellow sticker on $10m of perfectly good > parts, and calling them lemons to justify a sale below cost? > > I think anybody with a high school education can figure that one out > too. <snip> So go to college. Specifically, pursue engineering economics or general economics coursework. There is so much more out ther in life than ones own little world. Explore it.Article: 98911
Rick, If I have offended you, I apologize. In fact, if I have offended anyone, I apologize. I intended to poke fun (gently) at Metal's posting. I am an engineer, and I am not in marketing. If that means I am not politically correct: I never pretended to be anything other than honest. Again, I apologize if you found my posting objectionable. I do realize that there are some (not implying you) that have absolutely no sense of humor whatsoever, and for them, all I can say is: don't waste your time reading my posts, you won't like them (as I do have a sense of humor, and I do enjoy life and its challenges). Austin rickman wrote: > Austin Lesea wrote: > >>Metal, >> >>Pessimists always claim they are just observing reality. >> >>You must be working for one of those companies "circling the drain?" >> >>Really hard to be positive about anything. >> >> >>I see (our) business increasing (a lot), and I see margins that are >>good, and getting better, and I see new opportunities popping up all >>over the place. And I see the financials that support it. >> >>You have told all of us how we will need food, shelter, and a few sticks >>to burn here in the not so distant future. >> >>Austin > > > > Austin, it is hard to believe that no one at Xilinx has ever reigned > you in. Often your posts are useful and technically sound. But > concepts of customer interaction and company representation seem to be > lost on you. I was not even involved in this thread and I find your > post to be insulting as well as totally inappropriate. Your "ad > hominem" attacks seem to occur anytime someone makes a technical > argument that might be hard to dispute. > > To be honest, my impression of Xilinx has changed a lot over the last > few years, partly due to your postings here. Initially I did not pay a > lot of attention to your comments to me or others until I realized that > you are actually fairly influential in the company. Now I realize that > Xilinx as a whole is not a lot different than the image you present and > it bothers me. It bothers me enough that I now have a strong > preference for any other FPGA manufacturer. > > I think the fact that no one at Xilinx seems to have a problem with > your posts like this one says a lot about the company. >Article: 98912
Hi all,
i want to connect two fpga by bvci procotol. however, this will use
closed to 100 PINs. So, i plan to fold the interface, like parallel-in
serial-out interface. of course, the other interface of fpga is like
serial-in parallel out interface. this design should use low-PIN count
and can transfer data after handshaking. and the intreface design and
surrounding design have a common clock. that is, the throughput is
decreased by the interface. what idea for this do everybody have ?
thanks a lot ^^
Article: 98913Peter Alfke wrote: > Without EasyPath any production device with any known defect (that is > not covered by an errata note) goes into the garbage can. > That has been and will remain our policy, and I assume the policy of > any reputable IC manufacturer. Ahh ... an oldie moldie zero defect equals quality bigot. I thought all those either retired or got laid off in hard times. I can remember that same mantra in several industries, that all have found that selling defect managment and a profitable seconds line is the very key to improving sales and getting a better ROI for investors. I remember the 1980's when the disk drive industry was going thru that too. Just try and buy a half million zero defect drives today. Maybe some stock holders aught to be asking your board why you are so eager to crush into the can near perfect dies and packaged parts for a single (or small number) of flaws that might easily bring another 10-50% in sales into users perfectly willing to purchase parts with classified flaws they can design around. I'm perfectly willing to design reconfigurable computers with a few routing and LUT failures that we can map around with a defect list keepaway table. I'd be even happy to get them as bare, but mountable die. Anybody else here that would be willing to purchase high end FPGA's for reconfigurable computing with a few minor flaws? Since they are trash to you, can I get several thousand XC4VLX200's at say a 90-95% discount? hmm ... maybe that's to low an offer, and there is a bidding war ready to errupt.Article: 98914
Gabor wrote: > > partgen -i -v > > will generate files for all installed packages (this can be a lot of > files). or > just type > > partgen > > at a command prompt for program usage. Thank you all for the info. I'm now a very happy(ier) camper. :) -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 98915
<fpga_toys@yahoo.com> wrote in message news:1142622269.421494.270850@j33g2000cwa.googlegroups.com... <snip> > I assume that last straw of a jab, means that you decided that an 80% > discount is actually below cost. Hell no.Article: 98916
Peter Alfke wrote: > Are we continuing this thread until John (aka Mr Toy) has made a > complete fool of himself ? Ahh Peter .... you always run away shouting insults just when it's getting fun. > His ranting is neither coherent nor entertaining or amusing anymore. You haven't explained yet why throwing millions of dollars into the trash can provides your stock holders the best possible ROI for money spent on usable silicon with a very viable secondardy market willing to do defect management? In every other industry that's faced valuable high defect product decisions, the've tossed the zero defect bitots out, to push up the bottom line. Hopefully even Xilinx will reach the point that the zero defect incompetents are no longer supportable or promotable. Anything that increases Xilinx's sales without additional costs, can only improve the bottom line, and hopefully for customers lower the prices on other products that have had to carry the burden of the zero defect bigots waste.Article: 98917
I suppose these will be announced quite soon once the Virtex5 manuals become accessible to mortals ... I was intrigued to see in the Proceedings of ISSCC a design for an incredibly fast 64-bit adder in 90nm CMOS, which might in some way be an answer to the complaints about the carry chains in V4 being too slow for practical use. Abstract: A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply. Though it used 311mW for a single adder, which would make it impractical to have more than a few per chip; I suspect from the abstract that it was more an advert for a Xilinx optimisation framework than for the actual component that was optimised. So, what do people want to see? My inner supercomputer designer wants double-precision FPUs, but I suspect they'd be hopelessly interconnect limited; the same almost certainly applies to highly-multiport RAMs suitable for register files, which I'm mentioning because they can be implemented much more cleverly at the ASIC than at the LUT level (long buses with circuits sized to detect small impulses, rather than having to work in the digital realm everywhere). TomArticle: 98918
Subhasri krishnan wrote:
> I am having problems debugging my memory controller. My initial idea is
> to capture a frame and display the same frame continuously. But I see
> problems in the pattern captured (some spots with colours that arent
> expected to be there). When I simulate the controller it works as it is
> expected. I understand that the timing has to be right and I modified
> everything so that its alright.
Verify that by running static timing at 100MHz.
> I think that the problem lies with an asynchronous fifo used to buffer
> data at 25Mhz.
Consider syncing that interface to 100Mhz
and using a synch fifo.
> Also
> can i use 2 clocks in the same module?
Not without working out synchronization at the boundaries.
-- Mike Treseler
Article: 98919John_H wrote: > <fpga_toys@yahoo.com> wrote in message > news:1142622269.421494.270850@j33g2000cwa.googlegroups.com... > <snip> > > I assume that last straw of a jab, means that you decided that an 80% > > discount is actually below cost. > > Hell no. Gee Wiz .... I've got to see your version of the math :) This is really going to be fun!!!Article: 98920
Ray Andraka wrote: > Jim Granville wrote: > >> Austin Lesea wrote: >> > >> -jg >> > > I suspect the truth is closer to being able to customize the FPGA at the > time of application rather than at the time of purchase. That means > they can get more commonality, so that the spares inventory is much > smaller. Of course, there are many reasons to use a FPGA on the lower volume/less price sensistive vehicles. - but the maker will _still_ have to stock physically/electrically compatible modules. - and change FPGA families very carefully... Austin's second set of claims are much closer to reality than his first, which I have put in the 'Austinism' box... :) -jgArticle: 98921
fpga_toys@yahoo.com wrote: >As soon as the chip becomes "hard" with the routing frozen, that >quickly goes away as an option, so that customer test vectors must be >written based for full coverage of the design again (just as with >ASICs). And good coverage BIST becomes difficult again. As a former semiconductor test engineer, the hard part of FPGA production testing is fairly easy to see. It is the interconnect. Everything else looks very easy. Note that the FPGA under test will be reloaded with a different design many times during test. It seems to me that testing by loading BIST designs still makes a lot of sense. Using a BIST design, the RAMs, multipliers, LUTs and registers can be tested quickly. This is the easy part of testing a FPGA. There would be little gain in customizing these tests. >This seems to me that it increases testing complexity and NRE, not >reduce it. That it then requires expensive testers for all testing, >rather than using generic loadable BIST configurations which can be >managed by less expensive test interfaces. Most of the test time and cost for a standard FPGA would be needed to test interconnect. There would be a lot less (several orders of magnitude less) interconnect test time for an EasyPath part, as compared with a standard FPGA. It looks to this former semiconductor test engineer that the test cost of an EasyPath part might be between 30% and 5% of the test cost of a standard FPGA, depend on size of FPGA and lot of things that I know that I don't know. Now add in the effect of yields. This bring me to the amusing realization that Xilinx might well have the same profit margin percentage on an EasyPath tested FPGA than on the same standard tested FPGA selling for five times as much. While this all seems reasonable to me, I've been out of semiconductor test for more than 20 years. YYMV, SRA. -- Phil HaysArticle: 98922
Eric Smith wrote: <snip> >>In which case, using cells for timers eats >>up a $10 chip REAL fast....while the silicon cost for a few 16b hard >>counters on a chip like that would be near-zero... > > > It's not near-zero. The counters themselves may not use up much die > area, but they have to interface to the routing matrix just like > macrocells do, and the routing area is where much of your die area > goes. Add 16 more signals to the routing matrix, and it gets a LOT > bigger. That translates into real dollars. I'd rather spend 1.1x > dollars on 16 macrocells that do whatever I want,than 1.0x dollars > on 16 bits of hardwired stuff (which is more than just 16 flops, since > it may have input and output holding registers, etc.) that almost > certainly doesn't do what I want, because I'll end up having to buy more > macrocells for my own counters anyhow. The point is to do it selectively - like your MAC. If you look at the Xc2C128, the timer-chain there does not have a wide matrix cost, they are intended to do simple /N tasks, freeing up macrocells for more complex roles. So the cost is a few MUX fuses. > > "If only it had 17 bits" > > "If only it had a gate input" > > "If only the prescaler could be set to divide by 17" > > "If only the prescaler would reset when the counter is reset" > or > "If only the prescaler *wouldn't" reset when the counter is reset" > > "If only the PWM mode had complementary outputs to drive my H bridge" > > "If only the PWM mode had an adjustable dead band" > > etc. > > No matter what features you pick, they'll be wrong most of the time. > And if you put ALL the features in, then it will use up a lot of > silicon, and it will STILL be wrong a lot of the time. > > When I use counter-timers in microcontrollers, they rarely do what > I want, so I often end up adding external logic anyhow. And when they > do what I want, or close enough to it that I can do the rest in > firmware, it's because the requirements I'm making of the counter-timer > are really simple. Not the kind of stuff I'm going to put in an FPGA > anyhow. If my requirements can be met by a microcontroller, I'll use > that rather than an FPGA. True, many uC timers are too-simple, and never quite have the right gating paths. But the counter itself with SFR mapping is usefull. Many of our designs use a uC + CPLD, to do 'peripheral IQ extension' A good, simple, example is a Quadrature Conditioner for a 89C52 Timer2. The Timer2 has Up/Dn, but cannot count all 4 quadrants, so a PLD takes a Quad signal IN, and outputs a CLK.DIRN the timer can use. Result is efficent use of HW, and MUCH faster than a SW solution. -jgArticle: 98923
Antti <Antti.Lukats@xilant.com> wrote: > as of using external SATA PHY well that would work, but the problem is > that SATA PHY is pretty much not available at all, you are welcome to > try find one, but I am 99.99% sure you will not get any. OK, that was > situation a year ago, maybe its little easier today. None of these would work? * http://www.siliconimage.com/products/productfamily.aspx?id=3 * http://www.taracom.net/products.html -- ThomasArticle: 98924
Hi There, I need some help getting started with the aurora core. I'm trying to implement a simple serial protocol/data transfer between trasceivers in Rocket IO ML321 board. Can I just use the customized aurora core (generated by Core generator) to implement the protocol. Or, does the core have to be integrated with some other existing design for it work. Alternatively, is a there sample reference design available to demonstrate a simple link. Thx in advance, billu
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