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adventleaf@gmail.com wrote: > Sorry my previous message was incorrect, > "How can BAR0 be written to ( i.e. filled with 1's ) when the STATE > cannot escape from IDLE state since ( Hit is ZERO )? " > > this should be: > How can BAR0 be written to when after IDLE state is BUSY state that is > when FRAME# is de-asserted it goes back to IDLE state? and FRAME# is > de-asserted; is this a STATE lock? > since its in IDLE state and FRAME# is de-asserted? > > -- > young_leaf If you're suggesting that the state after the single-cycle FRAME# signal is an idle state, you are probably mistaken. My recollection is that the FRAME# can - for a single word write - assert for only one cycle with the IRDY# and TRDY# following after that. The state after the FRAME# before the other controls is not an idle state. It's through the IDSEL that the device is identified. The configuration writes will only be made to targets that are identified. If the target is "dead" on the bus, and the PCI configuration cycle is not in the idle state because it started and wasn't finished, the cycle will abort ant _then_ return to the idle state.Article: 99051
J Silverman wrote: > Hi All, > > Ok, you all kinda convinced me on this. After three days of searching for support software and not finding any, I started looking for another way of using a more modern FPGA. I was originally looking at the original Spartan (as they came in PLCC84 packaging) but cannot find any for sale in small quantities. So I started looking for ways on how to use a current FPGA in a breadboard, and I came across this site: > > <http://www.beldynsys.com/quadpacks.htm> > > They have a bunch of boards that will take SMT components and give you the ability to stick them in a breadboard. I was looking at the Q100-80 one and am wondering if that will work for a Spartan3 in VQ100 packaging. I'm not sure if the difference between VTQFP and TQFP is great enough to cause problems when trying to solder it on the board. > > Thanks, J Silverman Or just plug a development board onto your prototype breadboard. Are you using wire-wrap?Article: 99052
They do support reconfiguration like FPGA from Xilinx with the large modules? Is it possible to tear on 3 modules and if it is necessary to replace one of them? On the Atmel site I found (Search results: "partial reconfiguration") only http://www.atmel.com/dyn/resources/prod_documents/DOC3013.PDF in it little example with AND->OR and nothing is said about large projects. On Lattice.com in general found nothing. :(Article: 99053
"Valerios" <carik.valera@gmail.com> schrieb im Newsbeitrag news:1142792528.805964.182350@i40g2000cwc.googlegroups.com... > They do support reconfiguration like FPGA from Xilinx with the large > modules? Is it possible to tear on 3 modules and if it is necessary to > replace > one of them? > On the Atmel site I found (Search results: "partial reconfiguration") > only http://www.atmel.com/dyn/resources/prod_documents/DOC3013.PDF in > it little example with AND->OR and nothing is said about large > projects. > > On Lattice.com in general found nothing. > :( > Atmel can reconfigure any smal portion or all array in runtime there is no limitations LatticeSC has 'fabric config port' so you can access the configuration from the logic, but there is currently not much known to what extent the partial reconfiguration support from Lattice will be available. LatticeSC part are just out, so dont expect there be much about the reconfig of those parts info AnttiArticle: 99054
On 19 Mar 2006 09:36:42 -0800, "Erik Widding" <widding@birger.com> wrote: >If one is a current student that wants to be employable when she >graduates, I offer two pieces of advice. The first is to take as many >writing intensive classes in school as time allows. The second, buy a >copy of Emily Post's "Etiquette", and read the sections that apply to >daily life. Refer back this book when new life circumstances arise and >more of this system needs to be understood. Etiquette, like language, >is simply another formal system that needs to be learned and practiced >to be mastered. > >I really don't care how smart a person is, if he can not play nice with >others (i.e. show respect for) there simply is not room on my team for >such an individual. We find plenty of time for fun and informality at >this office. Much of the work we do is intensely creative. BUT, I do >not believe one can think outside of the system, without understanding >and respecting the system. I have absolutely *no* interest in entangling myself in this thread, except to commend the two paragraphs above to anyone, young or old, who wants to make a serious go of it in engineering. Bob Perlman Cambrian Design WorksArticle: 99055
Hal Murray wrote: >> The -g option doesn't change the code. It adds symbol tables so that >> data addresses and instruction address points to the source and names >> within the source code. > > I'm not familiar with this particular case, but sometimes the > compile-for-debugging option disables some optimizations that > rearrange code enough to confuse the debugger. > That's only a very minor effect with gcc and gdb, since the tools (and the debugging symbols file format) are capable of debugging pretty heavily optimised code. It is standard practice to mix debugging and optimisation (such as -O1 or -O2) during development and testing - indeed, for many targets, the generated assembly code is clearer with -O1 than no optimisation. You are right in theory, of course, and there may be some minor changes when -g is enabled, but not much.Article: 99056
Hi, Yes I will try using the synchronous fifo (one of my last options). Are sync fifos usually used as a buffer between 25Mhz and 100Mhz clock domains? I think I can use some counters and fifo flags to generate triggers. You mentioned that the boundaries have to be synchronized. what are the boundaries that you are talking about? Please do explain this. By the way, my clocks are from a DCM (25Mhz and 100Mhz generated with clock in from an external oscillator of 50Mhz) . Thanks Subhasri.K Mike Treseler wrote: > Subhasri krishnan wrote: > > > I am having problems debugging my memory controller. My initial idea is > > to capture a frame and display the same frame continuously. But I see > > problems in the pattern captured (some spots with colours that arent > > expected to be there). When I simulate the controller it works as it is > > expected. I understand that the timing has to be right and I modified > > everything so that its alright. > > Verify that by running static timing at 100MHz. > > > I think that the problem lies with an asynchronous fifo used to buffer > > data at 25Mhz. > > Consider syncing that interface to 100Mhz > and using a synch fifo. > > > Also > > can i use 2 clocks in the same module? > > Not without working out synchronization at the boundaries. > > > -- Mike TreselerArticle: 99057
I suggest an approach where everything runs off the same clock (100 MHz?). The synchronous FIFO then becomes very simple, just a state machine that controls the two BlockRAM ports, one for writing, one for reading. All the mysterious trickery of asynchronous FIFO flag control disappears, since everything happens on common clock edges. In general, using multiple clocks should always be the tool of last resort. Synchronous, single-clock designs are far easier to create and especially to debug. Peter Alfke, Xilinx Appplications.Article: 99058
fpga_toys@yahoo.com wrote: > Hal Murray wrote: > >>Xilinx isn't stupid. They will retest or recycle, whichever is >>less expensive (more profitable) overall. > > > Stupid isn't the right word. Complacent with their margins is probably > a better descripton. It's why they are only a $1.3B company instead of > $10-40B dollar company like Sun Microsystems or Microsoft which are > similar ages. But in quite different fields, so impossible to compare. > The founders had some great ideas 21 years ago, and other > than incremental refinement, the real innovation in both the business > plan and technology has been lacking a bit. Maybe Virtex 5 will turn all that around ? > The high margins and high > costs hinder the growth of their market. This makes interesting reading http://i.cmpnet.com/siliconstrategies/2006/03/isupplitables.gif and quite a contrast to Austin's original arm waving :) Seems that yes, Xilinx is the largest Programmable Logic company, (which is not trivial, so applaud them for that ), but no, their growth is BEHIND the Fabless group's average of 10.4%, at a modest 3.7%. Adding $59M in revenue. [Still, it IS positive :) ] Also the Fabless numbers seem to exclude larger companies ASIC flows, so the true ASIC market is rather larger again. ( eg IBM Microelectronics has a large chunk of ASIC flow in that revenue.... ) So, design starts in ASIC do seem to be falling, but the revenues seem to be growing faster than the programmable logic business ? Not an easy pill for the spin merchants at Xilinx to digest ? :) > > http://www.shareholder.com/visitors/dynamicdoc/document.cfm?CompanyID=SUNW&documentID=1014&PIN=&resizeThree=no&Scale=100&Keyword=type%20keyword%20here&Page=25 > > http://72.14.203.104/search?q=cache:YsLX3NJSemkJ:www.microsoft.com/msft/download/10K%25202005.doc+microsoft+form+10k+2005&hl=en&gl=us&ct=clnk&cd=1 > > My Idea of making Xilinx successful would be to once again aggressively > push the state of the art and grow the company into several related > markets That would bring their revenues into the 20B range inside this > decade. > > Reconfigurable computing as a market for Xilinx could have been grown > to something in the $50B range by today, but they got stuck in their > view of their business plan. I believe some new management, a > restructured technology development program, and one could turn Xilinx > around this year, and get it back on track as a $50B company over the > next decade ... or better. Why not take them a sound business plan, I'm sure they would listen ? They could seed this with some easypath FPGAs, and see how quickly you really can grow the RC sector..... Programmable Logic has some fundamental limits, that will relegate it to a niche business. To hit $50B, you are talking about another Intel, or another Samsung, and that would need truly radical changes. -jgArticle: 99059
Jim Granville wrote: > > Stupid isn't the right word. Complacent with their margins is probably > > a better descripton. It's why they are only a $1.3B company instead of > > $10-40B dollar company like Sun Microsystems or Microsoft which are > > similar ages. > > But in quite different fields, so impossible to compare. Nothing could be farther from the truth. Sun's strength was it's SPARC prococessor line which allowed it to grow as a high end systems company without being a MS/Intel clone. Had Xilinx embraced RC as a systems company, it would have leveraged it's strengths into a high dollar market. I believe that is still possible with Xilinx before it's core patents expire. Or inspite of Xilinx, using an A-Team competitor with an agressive technology plan. I have several different roadmaps that I've been developing over the last several years. Today is the right time to start a new tech industy, as we are just on the back side of a very deep tech slump, that should progress into a boom cycle. All the core technologies, operating systems, processors, FPGAs/CPLDs are mature products that have been incrementally refined for two decades. The time is ripe to innovate hard, as we did between 1978 thru 1987, and in the process use strong vision to take the industry to the next level.Article: 99060
Hi all, i am looking for VHDL instantiation of BRAMs and LUT memories .i copied those instantiations from libraries of Virtex-4 and Spartan-3E. But still they are not getting synthesized and implemented.Can someone suggest me where to look for these instantiations or can some one send me codes for BRAMs and LUT memories in Virtex-4.i need them urgently. thanks Regards RamakrishnaArticle: 99061
Peter Alfke wrote: > So, as long as you guys are interested in learning from us older folks, > let's stay with "King's English", or the American derivative. As Texas governor Miriam Amanda "Ma" Ferguson is reported to have said, "If the King's English was good enough for Jesus, it's good enough for us."Article: 99062
That is a pretty neat piece of software, good work. -IsaacArticle: 99063
Thanks . I am going to redo the design with synchronous fifos to see if that works. Peter Alfke wrote: > I suggest an approach where everything runs off the same clock (100 > MHz?). The synchronous FIFO then becomes very simple, just a state > machine that controls the two BlockRAM ports, one for writing, one for > reading. > All the mysterious trickery of asynchronous FIFO flag control > disappears, since everything happens on common clock edges. > In general, using multiple clocks should always be the tool of last > resort. Synchronous, single-clock designs are far easier to create and > especially to debug. > Peter Alfke, Xilinx Appplications.Article: 99064
Hello, I never actually implemented FIR filters in FPGAs. But, if I am able to assume, I would say that FIR filters take up a SIGNIFICANT amount of space in an FPGA. E.g. 20th-order FIR filter, 16 bit, would require at the very least 320 FFs. Then there is all the combinationnal logic that will be employed to multiply the output of each 16bit-delay element by its respective tap (at least the taps can be hardcoded). And finally there is the 16 bit accumulator register at the output. I am sure that I am oversimplifying the realization of the FIR filter; there must be some major details that I am overlooking. And there is also optimization techniques that the FPGA device probably offers that I have not mentionned. Still, I feel that the above description does give a good description on the realization of FIR filters. Would that be accurate? I mean that FIR filters (or IIR filers) do take up a considerable chunck of FPGA space ? Thx in advance -RogerArticle: 99065
I disagree in several ways: 1. 320 FFs are not much anymore, when FPGAs have tens and even hundreds of thousands of FFs. 2. Modern FPGAs have dedicated multipliers and accumulators that are very fast 3. FPGAs are fast,but often the application does not need that speed, and then the complexity (cost) can be reduced by time-multipexing. Peter Alfke, Xilinx ApplicationsArticle: 99066
In article <1142791123.168300.83030@i40g2000cwc.googlegroups.com>, "Antti" <Antti.Lukats@xilant.com> wrote: > http://www.simple-solutions.de/de/products/index.php Arrgh, if i only knew german.. But from the pictures it looks like the right sort of stuff. Volume for me is only a few.. this is going to be a hobby project, nothing big for resale.Article: 99067
In the bottom left corner are two flags. If you do not mind the Union Jack of the colonial past,, I have clicked it for you. http://www.simple-solutions.de/en/products/index.php Peter AlfkeArticle: 99068
On 18 Mar 2006 06:31:46 -0800, "Jakob" <franzjakob@gmail.com> wrote: >Hello Everyone, > >I am currently investigating my options for designing the power supply >part for an imaging application. The FPGA that I had in mind, because >of its small footprint and its availibility was the XC3S400. Because I >can't and don't want to make any assumptions about the utilisation of >the device at this point, I will probably have to design for the worst >case. >>From http://www.xilinx.com/products/design_resources/power_central/ I >figured that I will probably need around 3A for the core, something >like 2A for the I/O and a low-ripple 0.3A for the auxilliary rail. >Because I am a software engineer gone electronics, my knowledge on >power supply design is rather limited at this stage. >The device itself will be battery powered at around 11.6V, and I would >like the power supply part to be as small as possible. The efficiency >is also not that crucial, as long as I won't have to provide cooling. >Because its only a prototype cost is not an issue (within reason). Also >I might need to add, that the 11.6V could be quite noisy as there are >DC motors connected to it. My first shot was the TPS75003 from TI as it >has all three rails integrated. However, it only operates on <6.5V Vin. >I've had a look at the other manufacturers and feel a bit lost know. >Because some other parts of my design will also require 5V, should I >step down from 11.6V to 5V and then use something like the TPS75003? Or >would it be better to have four rails all going down from 11.6V. What >are my best options to keep the design small? Which bits do I need to >be careful about? > >Any suggestions on the design or where I could get some additional >information would be greatly appreciated. Hi Jakob, You *must* use a switching supply if you are to avoid a heatsink given the constraints you mention. IMO, the physically smallest solution will have one switching DC/DC converter and a linear reg for each rail. If you are a "software engineer gone electronics" then I recommend buying a DC/DC converter module instead of rolling your own with a controller chip, mosfets, inductors, low ESR caps and so forth. The disadvantage is that it costs more. The advantage is that you can get it to work. You should be able to find a few dozen modules that would meet your requirements here: http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=analog&familyId=462 Regards, AllanArticle: 99069
Hi all, i am wondering whether conv_integer(unsigned(value)) function is synthesizable or not,right now i would like use this function both on synplify pro and synopsys,but i am not sure whether it is synthesizable or not?please let me know if anyone tried to systhesize this function before. thanks, Regards Ramakrishna BachimanchiArticle: 99070
John_H, its not that i'm saying the "after the single-cycle FRAME# signal is an idle state", what i mean is how can we follow state machine design (as described in Appendix B of PCI Spec 3.0) to accomodate a Configuration Read/Write.... --- young_leafArticle: 99071
Roger Bourne wrote: > Hello, > > I never actually implemented FIR filters in FPGAs. But, if I am able to > assume, I would say that FIR filters take up a SIGNIFICANT amount of > space in an FPGA. > E.g. 20th-order FIR filter, 16 bit, would require at the very least 320 > FFs. Then there is all the combinationnal logic that will be employed > to multiply the output of each 16bit-delay element by its respective > tap (at least the taps can be hardcoded). And finally there is the 16 > bit accumulator register at the output. > I am sure that I am oversimplifying the realization of the FIR filter; > there must be some major details that I am overlooking. And there is > also optimization techniques that the FPGA device probably offers that > I have not mentionned. > > Still, I feel that the above description does give a good description > on the realization of FIR filters. Would that be accurate? I mean that > FIR filters (or IIR filers) do take up a considerable chunck of FPGA > space ? > > Thx in advance > -Roger > 20 Tap FIR filters don't occupy all that much room in FPGAs, especially the modern parts which have quite a bit more logic resources than earlier chips. First, most times we can run the clock at a multiple of the sample rate, which allows us to time share the hardware either by using the same multiplier for several tap coefficients, or by using several clock cycles to accomplish the multiplies (distributed arithmetic takes that a step further to postpone the shift-adds). A brute force full parallel implementation will be the largest, but for 20 taps, even that is not all that large, especially if you take advantage of the embedded multipliers present in most of the current families. Look at the multipliers and distributed arithmetic pages on my website for a bit of a tutorial: http//:www.andraka.comArticle: 99072
HiRaymond, Raymond wrote: > I found a possible answer to my problem at the Answer Database. > I should unzip the opb_mdm_v2_01_a.zip to the pcores folder in my > project, update > the coreversion in the MHS file from 2.00.a to 2.01.a and make the > project use/point to these > files instead of the default ones. > > But how do I make the project point to these files instead of the > default ones? The local pcores directory will be searched first - anything in there will override the defaults. You'll want to do a "make clean" in the project directory to force a complete rebuild, after making a change like this. Regards, JohnArticle: 99073
bachimanchi@gmail.com wrote:
> Hi all,
> i am wondering whether conv_integer(unsigned(value)) function is
> synthesizable or not,right now i would like use this function both on
> synplify pro and synopsys,but i am not sure whether it is synthesizable
> or not?please let me know if anyone tried to systhesize this function
> before.
>
>
> thanks,
>
>
>
> Regards
> Ramakrishna Bachimanchi
>
It is, but not the best way. Use the ieee.numeric_std package instead.
It has a to_integer function that does the same thing without the
troubles of non-standard libraries, and conflicting definitions that you
get using std_arith and its bretheren.
Article: 99074
bachimanchi@gmail.com wrote:
> i am wondering whether conv_integer(unsigned(value)) function is
> synthesizable or not,
It is, but I prefer to_integer.
http://groups.google.com/groups/search?q=vhdl+to_integer+unsigned+memory
-- Mike Treseler
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