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-Ive tried unchecking the EQUIVALENT_REGISTER_REMOVAL property in xilinx specific options, -Ive tried the KEEP attribute -Ive tried BOTH at the same time -Ive tried portmapping to FDCE -Ive verified that the xst file contains -EQUIVALENT_REGISTER_REMOVAL NO, -Ive tried googling on this issue with little success -Ive tried ALOT of other things, ...still the XST removes equivalent registers.. Im using spartan3 fpga and wasted 2 days now trying to find how to stop xst from bothering me. Any help out here? Thanks..Article: 99201
Phil Hays wrote: > Why test at die level at all? Economics. Packaging costs money. > Why test at package level at all? Full testing at wafer sort isn't > realistic, and die damage during packaging happens. And for some, such a damn if you do, and damn if you don't is a purfectly good excuse to do nothing. Life isn't purfect. Finding solutions I find more valuable than finding restrctions and excuses. > Something quite like this was tried. Some very good reasons not to do > it were found, the hard way. "Human beings, who are almost unique in > having the ability to learn from the experience of others, are also > remarkable for their apparent disinclination to do so." (Douglas > Adams) One of the most remarkable forms of success, is the difficult challenges offered from failures. The cost of chipping away at this problem could be relatively small, one or two engineers for a few years adding a very small complexity addition to production die. When success materializes, the savings are substantial. > Power supply measurement requires an ammeter per power supply per die, > or some way to switch an ammeter between measurement points, like > relays. I'd love to hear your plan. It always comes down to V=IR and there are plenty of designs/products that do current sensing well, even if an external reference standard is required. Maybe one of the ATE functions is to calibrate on die standards, and pass that to the rack manager. > Some things can't be implemented on wafers. Disk drives, relays, > precision resisters, ... None of which are needed on die for self testing.Article: 99202
Btw.. I should tell you how I know its the xst doing this: I look at the post-synthesis simulation model..Article: 99203
Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is 10.709. Should Virtex-4 be definitively excluded or are there some tricks to achieve that challenge? Cheers MehdiArticle: 99204
Erik, You to are a guest here, as is every other poster and reader. Sending the poster an email suggesting a behavior is one thing. Objecting to the tech speak is another. The lynching party that developed however went far beyond that, and that is what was a gross failure in this forum.Article: 99205
John Bass fpga_toys@yahoo.com wrote: >Phil Hays wrote: >> Why test at die level at all? Economics. Packaging costs money. >> Why test at package level at all? Full testing at wafer sort isn't >> realistic, and die damage during packaging happens. > >And for some, such a damn if you do, and damn if you don't is a >purfectly good excuse to do nothing. Life isn't purfect. Finding >solutions I find more valuable than finding restrctions and excuses. If you don't understand the problem, you are not very likely to come up with a solution. >> Something quite like this was tried. Some very good reasons not to do >> it were found, the hard way. "Human beings, who are almost unique in >> having the ability to learn from the experience of others, are also >> remarkable for their apparent disinclination to do so." (Douglas >> Adams) > >One of the most remarkable forms of success, is the difficult >challenges offered from failures. I'm sure Douglas Adams would agree. But you wouldn't like it. >> Power supply measurement requires an ammeter per power supply per die, >> or some way to switch an ammeter between measurement points, like >> relays. I'd love to hear your plan. > >It always comes down to V=IR Ever figure out what current a wafer full of die would draw? Now for the fun part. How to get all that current to all the die without too much voltage drop? Oh, and what if one die is in latchup? >and there are plenty of designs/products >that do current sensing well, even if an external reference standard is >required. Maybe one of the ATE functions is to calibrate on die >standards, and pass that to the rack manager. I thought you were not going to use an ATE. >> Some things can't be implemented on wafers. Disk drives, relays, >> precision resisters, ... >None of which are needed on die for self testing. As long as test coverage is way less than 50%, sure. -- Phil HaysArticle: 99206
Hello, (newbie) Question: At the intermediate nodes, between biquad-structures in a cascaded biquad structure IIR filter design approach (employing the fixed point approach), the resolution of the (extended) accumulator (of the output) must be scaled down to the width of the data bus, Rigth? (Internal musing: that would require a fixed point divider, I wonder how many cycles divison takes?) The scaling-down to the original databus width is required because the next biquad filter in the cascaded structure is expecting an input of n bits. n being the number the number of bits in the databus. m being the number of bits of the coefficients. Correct? Would/Can that cause problems ? ( that perphaps are not obvious to me rigth now). Are there any tools (freeware) that permit to cascade structures?Article: 99207
Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : "Payload compatible only"), so no hope for OTU-2 I think. We have to wait Virtex-5 family ?Article: 99208
For those who are interested, SUN released Open SPARC today: http://opensparc-t1.sunsource.net/download_hw.html Verilog RTL, verification and simulation tools included. Cheers. -- PabloBleyerKocik /"Person who say it cannot be done pablo / should not interrupt person doing it." @bleyer.org / -- Chinese proverbArticle: 99209
"Roger Bourne" <rover8898@hotmail.com> wrote in news:1142959299.253735.139210@v46g2000cwv.googlegroups.com: > Hello, > > (newbie) Question: > At the intermediate nodes, between biquad-structures in a cascaded > biquad structure IIR filter design approach (employing the fixed point > approach), the resolution of the (extended) accumulator (of the output) > must be scaled down to the width of the data bus, Rigth? > Yes, this is usually the case > (Internal musing: that would require a fixed point divider, I wonder > how many cycles divison takes?) Why a division? For example, if I have a number in 1.63 format (1 sign bit, 63 fractional bits, I can either round or truncate the result to 1.31 format. > > The scaling-down to the original databus width is required because the > next biquad filter in the cascaded structure is expecting an input of n > bits. n being the number the number of bits in the databus. m being the > number of bits of the coefficients. Correct? Yes > > Would/Can that cause problems ? ( that perphaps are not obvious to me > rigth now). The quantitizer (the process that shortens the fix point word) is going to have a very small effect. > Are there any tools (freeware) that permit to cascade structures? > Almost all filter programs assume cascade structures. I don't know much about the free ones. I use QEDesign 1000 (www.mds.com) whicj is very good. One of the advantages of QED is that the programmer is a very good DSP guy. This is not generally the case. Matlab is also very popular for filter design. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 99210
Roger Bourne wrote: > Hello, > > (newbie) Question: > At the intermediate nodes, between biquad-structures in a cascaded > biquad structure IIR filter design approach (employing the fixed point > approach), the resolution of the (extended) accumulator (of the output) > must be scaled down to the width of the data bus, Rigth? Right. Or, since this _is_ an FPGA group, the data bus must be scaled up to match the resolution of the accumulator. > > (Internal musing: that would require a fixed point divider, I wonder > how many cycles divison takes?) Lopping off bits doesn't necessarily mean scaling the numbers down numerically. If you view your numbers as integers then throwing away the least significant 16 and keeping the most significant 24 could be seen as a divide operation -- but if you view your numbers as fractional it's just disregarding some bits. In either case it doesn't require a divider -- you're simply wiring up the most significant bits which may or may not involve changing the apparent amplitude of the result by integer factors of two. > > The scaling-down to the original databus width is required because the > next biquad filter in the cascaded structure is expecting an input of n > bits. n being the number the number of bits in the databus. m being the > number of bits of the coefficients. Correct? Should you wish to hold the input of the next filter to n bits then yes, you have to do something with that extra-wide data bus coming out of preceding filters. > > Would/Can that cause problems ? ( that perphaps are not obvious to me > rigth now). > Are there any tools (freeware) that permit to cascade structures? > It can/will cause problems with precision, but if you can analyze what happens inside a filter section you can analyze what happens in between sections. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 99211
Antti <Antti.Lukats@xilant.com> wrote: > let me know if you manage to get any SATA PHY Ok, here's the thing. They have limited amount of samples, so they won't sell/give those to anyone but high volume cases. I've asked about when/if they expect to get new batch of chips/samples, and if it's possible to buy from them when/if they do. -- ThomasArticle: 99212
leaf wrote:
> i use Quatus-II software for my waveform analysis is it possible there?
>
Quartus has no vhdl or verilog simulator,
however a quartus subscription includes Modelsim
which is probably what you need.
-- Mike
Article: 99213The new Xilinx Platform USB cable does work under Linux. You apparently read some out-dated information. GHEDWHCVEAIS@spammotel.com wrote: > Hi, > > > > Concerning the new Xilinx Platform USB cable I read that it does not > work under Linux, so here the only option would be to boot the notebook > with Windows to get that going. > > > > TIA > > Guenter >Article: 99214
Robin Bruce wrote:
> I was wondering if anyone here knows the technique that the Xilinx
> floating-point square-root core employs to get its results. I ask
> because we've got a unit that does the same job with near-identical
> latency and clock speed but uses far less resource (330 slices, versus
> Xilinx's 624 slices for single-precision accuracy).
> Interestingly my paper on this unit was rejected from FCCM on the
> grounds that "more recent
> developments in the field of square root calculation" have been made.
Perhaps someone other than Xilinx has a better one.
> Could anyone cast any light on what these are? The algorithm I used is
> 400 years old, but why should that make any difference if it provides
> the correct answer for less resource use?
No difference at all if your goal is to
use a square root on an fpga. If your
goal is research existing algorithms
and find a better one, then do that.
> If anyone knows of a unit that provides pipelined single-precision
> square-root calculations over the full range possible inputs, I'd be
> interested to hear about it.
Here's some related discussion:
http://groups.google.com/groups?q=vhdl+square+root
-- Mike Treseler
Article: 99215Take two ... bad google day ... Phil Hays wrote: > If you don't understand the problem, you are not very likely to come > up with a solution. Quite true. > >> Something quite like this was tried. Some very good reasons not to do > >> it were found, the hard way. "Human beings, who are almost unique in > >> having the ability to learn from the experience of others, are also > >> remarkable for their apparent disinclination to do so." (Douglas > >> Adams) > > > >One of the most remarkable forms of success, is the difficult > >challenges offered from failures. > > I'm sure Douglas Adams would agree. But you wouldn't like it. You probably will not like the contradiction that it poses either: a) Experienced team A works diligently, ending in a heroic failure b) Team B offers regular help, which is turned down c) after the failure is complete, Team B completes the project quickly. Should Team B have accepted the failure as hard fact that the problem had no viable solution, and also failed by failing to try? (IE learning from Team A's failure) In 30 years of being self employed I've made about 20% of my income from taking over failed projects with a low bid no risk flat fee proposals to management ... no delivery, no payment. All I have at risk is my time and my reputation to always succeed on those projects. Several of those projects were taken from experienced teams that I offered friendly help on a regular basis, and was turned down. Others I took after one or more other companies failed to deliver what the client needed, often with sharp adivice that I would be doomed to repeating the cycle. > Ever figure out what current a wafer full of die would draw? Now for > the fun part. How to get all that current to all the die without too > much voltage drop? Oh, and what if one die is in latchup? yep ... and did you notice the part of the proposal about using on wafer power control for each die? > I thought you were not going to use an ATE. Did you notice the part of the proposal about using ATE for screening dangrous defects, like shorted power nets? > >> Some things can't be implemented on wafers. Disk drives, relays, > >> precision resisters, ... > > >None of which are needed on die for self testing. > > As long as test coverage is way less than 50%, sure. You have already given up if you think that. The explict idea behind defect managment is functional issolation by designing for 100% test coverage at some level of detail. Either a route, FF, LUT, buffer, or other resource fails testing, or is presumed operational, and to be screened if necessary by using redundant logic in the system level design initially. I suspect that this will be an itterative process of incremental refinement over a long period of time, maybe at first only saving 40-60% of the reject yield, and possibly progressing to nearly all. I suspect one of the most important parts of the process will be design refinements to prevent/issolate the failure impacts on future designs, increasing both the primary and secondary yields in the long term. One interesting form of "success" includes not reaching the entire objective, but leaving a carefully documented road map of the challenges, assumptions, and proposed solutions along the way so that those that follow have a better defined path to chip away at. Now, I don't know how much of Xilinx's yield is scrap today, or would be scrap at the end of 6 months, a year or two years. I do suspect the number will steadily decrease using design for defect management strategies. I do know the "cost" to Xilinx to sell scrap die and packaged product is pretty low, if it comes with a long term partnership to provide engineering input to increase yields for both zero defect, and managed defect segments. The long term promise of such a program is for each to act in good faith to increase revenues for both partners as the process matures. I believe that I can create products which are defect aware using the largest Xilinx parts, that presumably also have the largest percentage of rejects. I'm willing to invest the engineering into developing a recovery process, if Xilinx is willing to provide scrap material, and include in that partnership an agreement to share data and design suggestions to improve yeilds. As the recovery process becomes profitable, there is certainly incentives on both parties part to share that windfall. That's a pretty low risk deal for Xilinx if they are crushing scrap in die and packaged form today.Article: 99216
fpga_toys@yahoo.com wrote: > I'm willing to invest the engineering into developing a > recovery process, if Xilinx is willing to provide scrap material, and > include in that partnership an agreement to share data and design > suggestions to improve yeilds. As the recovery process becomes > profitable, there is certainly incentives on both parties part to share > that windfall. That's a pretty low risk deal for Xilinx if they are > crushing scrap in die and packaged form today. I'm willing to consider the same for other FPGA vendors as well.Article: 99217
I posted on here a few hours ago but haven't seen the response so I'll try again. My theory is that if you are relying on the mapper to swap out TBUFs for logic, that somehow messes with the register removal. I think this option has some issues anyway; using it you think you're optimizing when really you're shooting yourself in the foot because it doesn't leave enough registers for the IOBs. I'm just grateful Xilinx is finally starting to migrate the optimization to the mapper state -- the place where things like IOB register needs can be considered.Article: 99218
Hi all,
i am using the following code for BRAMs and i copied these
instantiations from virtex-4 libraray.But still i am getting an error
message when i am trying to implment it using xilinx ise7.1 on
virtex-4 fpga.It is giving an error message like .ngd build failed.Can
anyone help me in solving this problem.
thanks,
Regards
Ramakrishna
---------------------------------------------------------------------------------------------------
--
-- Title : LocalRAM
-- Design : LocalRam
-- Author : Khaleel
-- Company : George Mason University
--
---------------------------------------------------------------------------------------------------
--
-- File : LocalRAM.vhd
-- Generated : Sat Dec 3 15:23:33 2005
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {LocalRAM} architecture {LocalRAM}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
Library unisim;
use unisim.all;
entity LocalRAM is
port(
Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Wea : in STD_LOGIC;
Web : in STD_LOGIC;
En : in STD_LOGIC;
GRE : in STD_LOGIC;
selq : in STD_LOGIC;
Ain : in STD_LOGIC_VECTOR(31 downto 0);
Bin : in STD_LOGIC_VECTOR(31 downto 0);
A_addr : in STD_LOGIC_VECTOR(8 downto 0);
B_addr : in STD_LOGIC_VECTOR(8 downto 0);
Bout : out STD_LOGIC_VECTOR(31 downto 0);
A_M : out STD_LOGIC_VECTOR(31 downto 0);
Data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end LocalRAM;
--}} End of automatically maintained section
architecture LocalRAM of LocalRAM is
component RAMB16_S36_S36
-- synthesis translate_off
generic(
INIT_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
INITP_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- synthesis translate_on
port (
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0);
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA: in STD_ULOGIC;
ENB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC
);
end component;
Signal Aout : STD_LOGIC_VECTOR(31 downto 0);
Signal Plow : STD_LOGIC_VECTOR(3 downto 0);
Signal Pout : STD_LOGIC_VECTOR(3 downto 0);
Signal Bin1 : STD_LOGIC_VECTOR(31 downto 0);
begin
Data_out <= Aout when GRE = '1' else (others => 'Z');
A_M <= Aout;
Plow <= "0000";
Bin1 <= Aout when selq = '1' else Bin;
Local_RAM : RAMB16_S36_S36
-- synthesis translate_off
generic map (
INIT_00 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INITP_00 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
SRVAL_A => X"0000000000",
SRVAL_B => X"0000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
-- synopsys translate_on
port map (
DOA => Aout,
DOB => Bout,
DOPA => Pout,
DOPB => Pout,
ADDRA => A_addr,
ADDRB => B_addr,
CLKA => CLK,
CLKB => CLK,
DIA => Ain,
DIB => Bin1,
DIPA => Plow,
DIPB => Plow,
ENA => EN,
ENB => EN,
SSRA => Rst,
SSRB => Rst,
WEA => WEA,
WEB => WEB
);
-- enter your statements here --
end LocalRAM;
Article: 99219
I posted a few hours ago but it has yet to show so I'll try again. Most
modern square root algorithms do multiple bits per clock cycle. There
was a great paper out of Thailand (I believe) a few years back with a
very simple square root algorithm that does two bits per clock cycle. I
was unable to locate the paper but I did find some C code I used to
test it. Using it I was able to do a fine FP square root operator using
half the resources of Xilinx and having half the latency for both
pipelined and unpipelined versions. I actually think I could cut the
latency in half again if I worked at it and used just a few more
resources to do two adds in a clock cycle. If anyone recognizes the C
code below, please post the source!
DWORD n = 90; //input 8 bits worth: 90 should give 9r9
DWORD bl = sizeof(n)*8;//bitlen
DWORD hibit = 1<<(bl-1);
WORD s = 0;
DWORD r = 0;//actually sizeof(s) + sign bit
for(int i = (bl>>1)-1;i >=0; i--){
if(!(r & hibit)){
r = (r<<2) | (n>>(i<<1)&3);
r -= ((s<<2) | 1);
}
else{
r = (r<<2) | (n>>(i<<1)&3);
r += ((s<<2) | 3);
}
if(!(r & hibit))
s = (s<<1) | 1;
else
s = s<<1;
}
if((r & hibit)) r += ((s<<1) | 1);
Article: 99220Allan Herriman wrote: > > Of course! I was thinking that the decision to add the extra > (2^48-2e14) would have to take place prior to the register, but now I > realise that it can be pipelined, which makes it possible to get it to > run at 200MHz. > The thing I like most about this technique is that you can hit exact coarse decimal steps ( e.g. 1 kHz ) with a VERY short phase accumulator, enabling high precision lookups without any phase truncation. Note that for sin lookup applications, you'll want to do the correction such that the phase bits off to the sine generation logic don't exceed your modulus on the correction cycle. The earliest reference I've seen applying this technique to a sine output DDS is the Rockland/Wavetek decimal DDS patent: US Patent 3,735,269 Jackson 1973 Which is stamped on the back of my Wavetek 5130A, a classic direct analog mix-divide decade bucket architecture with the lower decade buckets replaced by the decimal DDS. > > This may complicate downstream processing, e.g. use of CORDIC to > generate a sinusoid. > The neat thing about CORDIC's is that the units of angular measure can be whatever you want, and are not restricted to the classic 2*Pi Binary Angular Measure (BAM) encoding - just fix up the arctan table to match your desired units. With a short phase accumulator, it is also practical to pre-compute the rotation decisions and store them in a lookup table. Thanks to Ray for pointing that out to me a couple times when I was stuck on the notion of a BCD CORDIC; but it never quite sunk in until after I looked at implementing it. Another useful trick is to preserve the top two or three bits of the accumulator as pure binary to do quadrant/octant folding of the sin/cos functions- often seen in the BCD DDS ASIC's of yore. ( or more bits if you want binary weighted phase modulation ) BrianArticle: 99221
fpga_toys@yahoo.com wrote: > fpga_toys@yahoo.com wrote: > >>I'm willing to invest the engineering into developing a >>recovery process, if Xilinx is willing to provide scrap material, and >>include in that partnership an agreement to share data and design >>suggestions to improve yeilds. As the recovery process becomes >>profitable, there is certainly incentives on both parties part to share >>that windfall. That's a pretty low risk deal for Xilinx if they are >>crushing scrap in die and packaged form today. > > > I'm willing to consider the same for other FPGA vendors as well. Sounds simple - become an EasyPath customer! You can make your own bit streams ( IIRC, two are allowed ? ), and thus get die that are in a 'possibly faulty, but partially proven' bin, and expand from there..... -jgArticle: 99222
Guru's I want to take the RTL schematic generated by XST to LATEX doc. Basically I need an .eps file. When I tried to copy the RTL schematic from XST and paste to MAYURA DRAW or TPX program, nothing gets copied. Can some kind soul helps in getting .eps file for latex. Thanks in advance SantArticle: 99223
hello guys can i get complte code for a 16 bit risc processor written
in VHDL, i have developed code for it but im not sure whether it is
correct can any one correct my code
-HEADER FILE INTILISATION
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--ALU INPUT DECLARATION
entity pro is
port(a,b:in std_logic_vector(7 downto 0);
s: in std_logic_vector(3 downto 0);
y: out std_logic_vector(9 downto 0)
);
end pro;
--ALU ARCHITECHURE MODULE
architecture project of pro is
signal temp:std_logic_vector(9 downto 0);
begin
process(a,b,s)
begin
--ACCORDING TO CONTROL SIGNAL
--ARTHMATIC OR LOGICAL FUNCTION SELECTION
case s is
when "0000"
=> temp<=a+b;
when "0001"
=> temp<=a-b;
when "0010"
=> temp<=a*b;
when "0100"
=> temp<=a and b;
when "0101"
=> temp<=a or b;
when others
=>temp<=a xor b;
end case ;
end process;
--PRINT OUTPUT
y<=temp;
end project;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity CPU is
port (
PADDR : out std_logic_vector(31 downto 0);
PDATA : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
PORTA_IN : in std_logic_vector(7 downto 0);
PORTA_OUT : out std_logic_vector(7 downto 0);
PORTA_OE_L : out std_logic_vector(7 downto 0);
PORTB_IN : in std_logic_vector(7 downto 0);
PORTB_OUT : out std_logic_vector(7 downto 0);
PORTB_OE_L : out std_logic_vector(7 downto 0);
PORTC_IN : in std_logic_vector(7 downto 0);
PORTC_OUT : out std_logic_vector(7 downto 0);
PORTC_OE_L : out std_logic_vector(7 downto 0);
PORTD_IN : in std_logic_vector(7 downto 0);
PORTD_OUT : out std_logic_vector(7 downto 0);
PORTD_OE_L : out std_logic_vector(7 downto 0);
DEBUG_W : out std_logic_vector(7 downto 0);
DEBUG_PC : out std_logic_vector(10 downto 0);
DEBUG_INST : out std_logic_vector(15 downto 0);
DEBUG_STATUS : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of CPU is
-- component definitions
component IDEC is
port (
INST : in std_logic_vector(11 downto 0);
ALU_ASEL : out std_logic_vector(1 downto 0);
ALU_BSEL : out std_logic_vector(1 downto 0);
ALU_ADDSUB : out std_logic_vector(1 downto 0);
ALU_BIT : out std_logic_vector(1 downto 0);
ALU_SEL : out std_logic_vector(1 downto 0);
WWE_OP : out std_logic;
FWE_OP : out std_logic;
ZWE : out std_logic;
DCWE : out std_logic;
CWE : out std_logic;
BDPOL : out std_logic;
OPTION : out std_logic;
TRIS : out std_logic
);
end component;
component ALU is
port (
ADDSUB : in std_logic_vector(1 downto 0);
BIT : in std_logic_vector(1 downto 0);
SEL : in std_logic_vector(1 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
CIN : in std_logic;
COUT : out std_logic;
DCOUT : out std_logic;
ZOUT : out std_logic
);
end component;
component REGS is
port (
WE : in std_logic;
RE : in std_logic;
BANK : in std_logic_vector(1 downto 0);
LOCATION : in std_logic_vector(4 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end component;
-- type/constant definitions
constant STATUS_RESET_VALUE : std_logic_vector(7 downto 0) := x"18";
constant OPTION_RESET_VALUE : std_logic_vector(7 downto 0) := x"3F";
constant INDF_ADDR : std_logic_vector(2 downto 0) := "000";
constant TMR0_ADDR : std_logic_vector(2 downto 0) := "001";
constant PCL_ADDR : std_logic_vector(2 downto 0) := "010";
constant STATUS_ADDR : std_logic_vector(2 downto 0) := "011";
constant FSR_ADDR : std_logic_vector(2 downto 0) := "100";
constant PORTA_ADDR : std_logic_vector(2 downto 0) := "101";
constant PORTB_ADDR : std_logic_vector(2 downto 0) := "110";
constant PORTC_ADDR : std_logic_vector(2 downto 0) := "111";
constant PORTD_ADDR : std_logic_vector(2 downto 0) := "111";
-- signal definitions
signal inst : std_logic_vector(15 downto
0);
signal inst_k : std_logic_vector(7 downto 0);
signal inst_fsel : std_logic_vector(4 downto 0);
signal inst_d : std_logic;
signal inst_b : std_logic_vector(2 downto 0);
signal tmr0 : std_logic_vector(1 downto 0);
signal pc,next_pc : std_logic_vector(31 downto
0);
signal pc_load_stack : std_logic_vector(10 downto
0);
signal pc_write : std_logic_vector(10 downto
0);
signal stacklevel : std_logic_vector(1 downto 0);
signal stack1,stack2 : std_logic_vector(10 downto
0);
signal porta_dout : std_logic_vector(7 downto 0);
signal portb_dout : std_logic_vector(7 downto 0);
signal portc_dout : std_logic_vector(7 downto 0);
signal portd_dout : std_logic_vector(7 downto 0);
signal porta_din : std_logic_vector(7 downto 0);
signal portb_din : std_logic_vector(7 downto 0);
signal portc_din : std_logic_vector(7 downto 0);
signal portd_din : std_logic_vector(7 downto 0);
signal dbus,sbus : std_logic_vector(7 downto 0);
signal sbus_swap : std_logic_vector(7 downto 0);
signal sbus_mux_out : std_logic_vector(7 downto 0);
-- inst decode
signal regfile_sel,special_sel : std_logic;
signal fileaddr_indirect : std_logic;
signal fileaddr_mux1 : std_logic_vector(6 downto 0);
signal fileaddr_mux0 : std_logic_vector(6 downto 0);
signal istris,isoption : std_logic;
signal fwe,wwe,zwe,dcwe,cwe : std_logic;
signal bdpol,status1 : std_logic;
signal bd,trisa,trisb,trisc,trisd :
std_logic_vector(7 downto 0);
signal skip : std_logic;
-- alu
signal alu_asel,alu_bsel : std_logic_vector(1 downto 0)
;
signal alu_addsub : std_logic_vector(1 downto 0)
;
signal alu_bit : std_logic_vector(1 downto 0)
;
signal alu_sel : std_logic_vector(1 downto 0)
;
signal alu_z,alu_dcout,alu_cout : std_logic ;
signal alu_a,alu_b : std_logic_vector(7 downto 0)
;
signal alu_out : std_logic_vector(7 downto 0);
signal regfile_we,regfile_re : std_logic;
signal regfile_in,regfile_out : std_logic_vector(7 downto 0);
signal fileaddr : std_logic_vector(6 downto 0);
begin -- architecture
u_regs : REGS
port map (
WE => regfile_we,
RE => regfile_re,
BANK => fileaddr(6 downto 5),
LOCATION => fileaddr(4 downto 0),
DIN => regfile_in,
DOUT => regfile_out,
RESET => RESET,
CLK => CLK
);
DEBUG_PC <= pc(10 downto 0);
DEBUG_INST <= inst;
-- *********** REGISTER FILE Addressing ****************
p_regfile_we_comb : process(regfile_sel,fwe,alu_asel,alu_bsel)
begin
regfile_we <= regfile_sel and fwe;
regfile_re <= '1'; -- not used
end process;
p_fileaddr_dec_comb : process(fileaddr,isoption,istris)
begin
regfile_sel <= '1'; -- everything else;
special_sel <= '0';
if (fileaddr(4 downto 3) = "00") and (isoption = '0') and (istris =
'0') then
special_sel <= '1'; -- lower 8 addresses in ALL BANKS 1 lut
end if;
end process;
p_dbus_comb : process(alu_out)
begin
dbus <= alu_out;
regfile_in <= alu_out;
end process;
p_paddr_comb : process(next_pc)
begin
PADDR <= next_pc(31 downto 0);
end process;
p_inst_assign_comb : process(inst)
begin
inst_k <= inst(7 downto 0);
inst_fsel <= inst(4 downto 0);
inst_d <= inst(5);
inst_b <= inst(7 downto 5);
end process;
p_bdec_assign_comb : process(inst_b,bdpol)
variable bdec : std_logic_vector(7 downto 0);
begin
-- 1 lut
bdec := "00000001";
case inst_b is
when "000" => bdec := "00000001";
when "001" => bdec := "00000010";
when "010" => bdec := "00000100";
when "011" => bdec := "00001000";
when "100" => bdec := "00010000";
when "101" => bdec := "00100000";
when "110" => bdec := "01000000";
when "111" => bdec := "10000000";
when others => null;
end case;
if (bdpol = '1') then
bd <= not bdec;
else
bd <= bdec;
end if;
end process;
p_inst : process(CLK,RESET)
begin
if (RESET = '1') then
inst <= "0000000000000000";
elsif CLK'event and (CLK = '1') then
if (skip = '1') then
inst <= "0000000000000000"; -- force NOP
else
inst <= PDATA;
end if;
end if;
end process;
p_skip_comb : process(inst,alu_z,fwe,special_sel,fileaddr)
begin
-- SKIP signal.
-- We want to insert the NOP instruction for the following
conditions:
-- we have modified PCL
-- GOTO,CALL and RETLW instructions
-- BTFSS instruction when aluz is HI
-- BTFSC instruction when aluz is LO
skip <= '0';
if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) =
PCL_ADDR) then skip <= '1'; end if;
if (inst(11 downto 10) = "10") then skip <= '1'; end if;
if (inst(11 downto 8) = "0110") and (alu_z = '1') then skip <=
'1'; end if; -- BTFSC
if (inst(11 downto 8) = "0111") and (alu_z = '0') then skip <=
'1'; end if; -- BTFSS
if (inst(11 downto 6) = "001011") and (alu_z = '1') then skip <=
'1'; end if; -- DECFSZ
if (inst(11 downto 6) = "001111") and (alu_z = '1') then skip <=
'1'; end if; -- INCFSZ
end process;
sbus_swap <= sbus(3 downto 0) & sbus(7 downto 4);
port_in : process(CLK,RESET,PORTA_IN,PORTB_IN,PORTC_IN)
begin
-- the input registers don't exist in the real device,
-- so if you read an output we have introduced a clock delay.
if (RESET = '1') then
porta_din <= (others => '0');
portb_din <= (others => '0');
portc_din <= (others => '0');
portd_din <= (others => '0');
elsif CLK'event and (CLK = '1') then -- comment this out for
combinatorial ip
porta_din <= PORTA_IN;
portb_din <= PORTB_IN;
portc_din <= PORTC_IN;
portd_din <= PORTD_IN;
end if;
end process;
p_port_reg : process(CLK,RESET)
begin
if (RESET = '1') then
trisa <= "11111111"; -- default tristate
trisb <= "11111111"; -- default tristate
trisc <= "11111111"; -- default tristate
trisd <= "11111111"; -- default tristate
porta_dout <= x"00";
portb_dout <= x"00";
portc_dout <= x"00";
portd_dout <= x"00";
elsif CLK'event and (CLK = '1') then
if (fwe = '1') and (fileaddr(2 downto 0) = PORTA_ADDR) then
if (istris = '0') and (special_sel = '1') then
porta_dout <= dbus;
elsif (istris = '1') then
trisa <= dbus;
end if;
end if;
if (fwe = '1') and (fileaddr(2 downto 0) = PORTB_ADDR) then
if (istris = '0') and (special_sel = '1') then
portb_dout <= dbus;
elsif (istris = '1') then
trisb <= dbus;
end if;
end if;
if (fwe = '1') and (fileaddr(2 downto 0) = PORTC_ADDR) then
if (istris = '0') and (special_sel = '1') then
portc_dout <= dbus;
elsif (istris = '1') then
trisc <= dbus;
end if;
end if;
if (fwe = '1') and (fileaddr(2 downto 0) = PORTD_ADDR) then
if (istris = '0') and (special_sel = '1') then
portd_dout <= dbus;
elsif (istris = '1') then
trisd <= dbus;
end if;
end if;
end if;
end process;
-- ********** PC AND STACK *************************
p_stack_comb : process(stacklevel,stack1,stack2)
begin
pc_load_stack <= stack1; -- default
case stacklevel is
when "00" => pc_load_stack <= stack1;
when "01" => pc_load_stack <= stack1;
when "10" => pc_load_stack <= stack2;
when "11" => pc_load_stack <= stack2;
when others => null;
end case;
end process;
p_stack_reg : process(CLK,RESET)
begin
if (RESET = '1') then
stack1 <= (others => '0');
stack2 <= (others => '0');
elsif CLK'event and (CLK = '1') then
if (inst(11 downto 8) = "1001") then
case stacklevel is
when "00" => stack1 <= pc(10 downto 0);
when "01" => stack2 <= pc(10 downto 0);
when others => null;
end case;
end if;
end if;
end process;
p_stack_level : process(CLK,RESET)
begin
if (RESET = '1') then
stacklevel <= "00";
elsif CLK'event and (CLK = '1') then
stacklevel <= stacklevel;
if (inst(11 downto 8) = "1001") then
case stacklevel is
when "00" => stacklevel <="01"; -- 1st call
when "01" => stacklevel <="10"; -- 2nd call
when "10" => stacklevel <="10"; -- already 2, ignore
when "11" => stacklevel <="00"; -- broke
when others => null;
end case;
elsif (inst(11 downto 8) = "1000") then
case stacklevel is
when "00" => stacklevel <="00"; -- broke
when "01" => stacklevel <="00"; -- go back to no call
when "10" => stacklevel <="01"; -- go back to 1 call
when "11" => stacklevel <="10"; -- broke
when others => null;
end case;
end if;
end if;
end process;
end rtl;
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library IEEE;
use IEEE.std_logic_1164.all;
entity keyboard is
port (
Key_0: in STD_LOGIC;
Key_1: in STD_LOGIC;
Key_2: in STD_LOGIC;
Key_3: in STD_LOGIC;
Key_4: in STD_LOGIC;
Key_5: in STD_LOGIC;
Key_6: in STD_LOGIC;
Key_7: in STD_LOGIC;
Key_8: in STD_LOGIC;
Key_9: in STD_LOGIC;
RESET: in STD_LOGIC;
ACKA: in STD_LOGIC;
INTA: out STD_LOGIC;
CODE: out STD_LOGIC_VECTOR (3 downto 0)
);
end keyboard;
--}} End of automatically maintained section
architecture keyboard of keyboard is
signal INT: std_logic;
begin
-- <<enter your statements here>>
process(Key_0,Key_1,Key_2,Key_3,Key_4,Key_5,Key_6,Key_7,Key_8,Key_9,Key_0,
ACKA, RESET)
begin
if(RESET='1') then
INT<='1';
CODE<="0000";
else
if(INT='1' and (ACKA='1' or ACKA='H')) then
if(Key_0='1') then
CODE<="0000";
INT<='0';
elsif(Key_1='1') then
CODE<="0001";
INT<='0';
elsif(Key_2='1') then
CODE<="0010";
INT<='0';
elsif(Key_3='1') then
CODE<="0011";
INT<='0';
elsif(Key_4='1') then
CODE<="0100";
INT<='0';
elsif(Key_5='1') then
CODE<="0101";
INT<='0';
elsif(Key_6='1') then
CODE<="0110";
INT<='0';
elsif(Key_7='1') then
CODE<="0111";
INT<='0';
elsif(Key_8='1') then
CODE<="1000";
INT<='0';
elsif(Key_9='1') then
CODE<="1001";
INT<='0';
else
INT<='1';
end if;
elsif(INT='0' and ACKA='0') then
INT<='1';
end if;
end if;
end process;
INTA<=INT;
end keyboard;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.pkg_xilinx_prims.all;
entity RISC5X_XIL is
port (
I_PRAM_ADDR : in std_logic_vector(31 downto 0);
I_PRAM_DIN : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
I_PRAM_WE : in std_logic;
I_PRAM_ENA : in std_logic;
PRAM_CLK : in std_logic;
--
IO_PORTA_IO : inout std_logic_vector(7 downto 0);
IO_PORTB_IO : inout std_logic_vector(7 downto 0);
IO_PORTC_IO : inout std_logic_vector(7 downto 0);
IO_PORTD_IO : inout std_logic_vector(7 downto 0);
O_DEBUG_W : out std_logic_vector(7 downto 0);
O_DEBUG_PC : out std_logic_vector(10 downto 0);
O_DEBUG_INST : out std_logic_vector(11 downto 0);
O_DEBUG_STATUS : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of RISC5X_XIL is
signal porta_in : std_logic_vector(7 downto 0);
signal porta_out : std_logic_vector(7 downto 0);
signal porta_oe_l : std_logic_vector(7 downto 0);
signal portb_in : std_logic_vector(7 downto 0);
signal portb_out : std_logic_vector(7 downto 0);
signal portb_oe_l : std_logic_vector(7 downto 0);
signal portc_in : std_logic_vector(7 downto 0);
signal portc_out : std_logic_vector(7 downto 0);
signal portc_oe_l : std_logic_vector(7 downto 0);
signal portd_in : std_logic_vector(7 downto 0);
signal portd_out : std_logic_vector(7 downto 0);
signal portd_oe_l : std_logic_vector(7 downto 0);
signal paddr : std_logic_vector(31 downto 0);
signal pdata,pin : std_logic_vector(15 downto 0);
signal pram_addr : std_logic_vector(10 downto 0);
signal pram_din : std_logic_vector(11 downto 0);
signal pram_dout : std_logic_vector(11 downto 0);
signal pram_we : std_logic;
signal pram_ena : std_logic;
signal debug_w : std_logic_vector(7 downto 0);
signal debug_pc : std_logic_vector(10 downto 0);
signal debug_inst : std_logic_vector(15 downto 0);
signal debug_status : std_logic_vector(7 downto 0);
signal doa_temp : std_logic_vector(11 downto 0);
signal dob_temp : std_logic_vector(11 downto 0);
component CPU is
port (
PADDR : out std_logic_vector(31 downto 0);
PDATA : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
PORTA_IN : in std_logic_vector(7 downto 0);
PORTA_OUT : out std_logic_vector(7 downto 0);
PORTA_OE_L : out std_logic_vector(7 downto 0);
PORTB_IN : in std_logic_vector(7 downto 0);
PORTB_OUT : out std_logic_vector(7 downto 0);
PORTB_OE_L : out std_logic_vector(7 downto 0);
PORTC_IN : in std_logic_vector(7 downto 0);
PORTC_OUT : out std_logic_vector(7 downto 0);
PORTC_OE_L : out std_logic_vector(7 downto 0);
PORTD_IN : in std_logic_vector(7 downto 0);
PORTD_OUT : out std_logic_vector(7 downto 0);
PORTD_OE_L : out std_logic_vector(7 downto 0);
DEBUG_W : out std_logic_vector(7 downto 0);
DEBUG_PC : out std_logic_vector(10 downto 0);
DEBUG_INST : out std_logic_vector(15 downto 0);
DEBUG_STATUS : out std_logic_vector(7 downto 0);
-- out_DATA : out std_logic_vector(15 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end component;
begin
u0 : CPU
port map (
PADDR => paddr,
PDATA => pdata,
O_PRAM_DOUT => pin,
PORTA_IN => porta_in,
PORTA_OUT => porta_out,
PORTA_OE_L => porta_oe_l,
PORTB_IN => portb_in,
PORTB_OUT => portb_out,
PORTB_OE_L => portb_oe_l,
PORTC_IN => portc_in,
PORTC_OUT => portc_out,
PORTC_OE_L => portc_oe_l,
PORTD_IN => portd_in,
PORTD_OUT => portd_out,
PORTD_OE_L => portd_oe_l,
-- DEBUG_W => debug_w,
-- DEBUG_PC => debug_pc,
-- DEBUG_INST => debug_inst,
-- DEBUG_STATUS => debug_status,
RESET => RESET,
CLK => CLK
);
p_drive_ports_out_comb :
process(porta_out,porta_oe_l,portb_out,portb_oe_l,portc_out,portc_oe_l)
begin
pin<= I_PRAM_DIN;
for i in 0 to 7 loop
if (porta_oe_l(i) = '0') then
IO_PORTA_IO(i) <= porta_out(i);
else
IO_PORTA_IO(i) <= 'Z';
end if;
if (portb_oe_l(i) = '0') then
IO_PORTB_IO(i) <= portb_out(i);
else
IO_PORTB_IO(i) <= 'Z';
end if;
if (portc_oe_l(i) = '0') then
IO_PORTC_IO(i) <= portc_out(i);
else
IO_PORTC_IO(i) <= 'Z';
end if;
if (portd_oe_l(i) = '0') then
IO_PORTD_IO(i) <= portd_out(i);
else
IO_PORTD_IO(i) <= 'Z';
end if;
end loop;
end process;
p_drive_ports_in_comb : process(IO_PORTA_IO,IO_PORTB_IO,IO_PORTC_IO)
begin
O_PRAM_DOUT <= pin;
porta_in <= IO_PORTA_IO;
portb_in <= IO_PORTB_IO;
portc_in <= IO_PORTC_IO;
portd_in <= IO_PORTC_IO;
end process;
end RTL;
Plain Text Attachment [ Download File | Save to Yahoo! Briefcase ]
--HEADER FILE INTILI SATION
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.pkg_xilinx_prims.all;
--There are three memory blocks in each of the risc devices.
--The program memory and data
--memory have separate buses so that concurrent
---access can occur and is detailed in this section. The
--EEPROM data memory block is detailed in
--"Data EEPROM and Flash Program Memory".
--Additional information on device memory may be found
--The data memory is partitioned into multiple banks
--which contain the General Purpose Registers and the
--Special Function Registers. Bits RP1 (Status<6>) and
--R-P0 (Status<5>) are the bank select bits.
--REGISTER INPUT OUTPUT DECLARATION
entity REGS is
port (
WE : in std_logic;
RE : in std_logic;
BANK : in std_logic_vector(1 downto 0);
LOCATION : in std_logic_vector(4 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end;
--
architecture RTL of REGS is
constant WIDTH : natural := 8;
constant OP_REG : boolean := false;
type slv_array is array (natural range <>) of
std_logic_vector(WIDTH-1 downto 0);
signal ram_out : slv_array(4 downto 0);
signal wen_int : std_logic_vector(4 downto 0);
signal sel : std_logic_vector(2 downto 0);
signal final_addr : std_logic_vector(6 downto 0);
--constant WIDTH : natural := 8;
--constant OP_REG : boolean := false;
-- following required for simulation model only
constant nwords : integer := 2 ** 7;
type ram_type is array (0 to nwords-1) of std_logic_vector(WIDTH-1
downto 0);
signal ram_read_data : std_logic_vector(WIDTH-1 downto 0);
--shared variable ram :ram_type := (others => (others => 'X')); --
helps debug no end!
shared variable ram :ram_type := (others => (others => '0'));
begin -- architecture
-- ram mapping
-- bank location
-- xx 00xxx special registers
-- xx 01xxx common 8 to all banks
-- 00 1xxxx 16 bank 0
-- 01 1xxxx 16 bank 1
-- 10 1xxxx 16 bank 2
-- 11 1xxxx 16 bank 3
DOUT<= DIN;
p_wen_comb : process (BANK,LOCATION,WE)
variable addr : std_logic_vector(3 downto 0);
begin
addr := (BANK & LOCATION(4 downto 3));
wen_int <= (others => '0');
case addr(3 downto 1) is
when "001" => wen_int(0) <= WE; -- bank0
when "011" => wen_int(1) <= WE; -- bank1
when "101" => wen_int(2) <= WE; -- bank2
when "111" => wen_int(3) <= WE; -- bank3
when others => null;
end case;
if (LOCATION(4 downto 3) = "01") then
wen_int(4) <= WE; -- common
end if;
SEL <= BANK & LOCATION(4);
end process;
--pragma translate_off
--The PIC16F87XA devices have a 13-bit program
--counter capable of addressing an 8K word x 14 bit
--program memory space. The risc
--devices have 8K words x 14 bits of Flash program
--memory,
p_remap : process(BANK,LOCATION)
variable addr : std_logic_vector(3 downto 0);
begin
addr := (BANK & LOCATION(4 downto 3));
final_addr <= "0000000";
case addr is
when "0001" => final_addr <= "0000" & LOCATION(2 downto 0);
when "0101" => final_addr <= "0000" & LOCATION(2 downto 0);
when "1001" => final_addr <= "0000" & LOCATION(2 downto 0);
when "1101" => final_addr <= "0000" & LOCATION(2 downto 0);
-- bank #0
when "0010" => final_addr <= "0001" & LOCATION(2 downto 0);
when "0011" => final_addr <= "0010" & LOCATION(2 downto 0);
-- bank #1
when "0110" => final_addr <= "0011" & LOCATION(2 downto 0);
when "0111" => final_addr <= "0100" & LOCATION(2 downto 0);
--bank #2
when "1010" => final_addr <= "0101" & LOCATION(2 downto 0);
when "1011" => final_addr <= "0110" & LOCATION(2 downto 0);
-- bank #3
when "1110" => final_addr <= "0111" & LOCATION(2 downto 0);
when "1111" => final_addr <= "1000" & LOCATION(2 downto 0);
when others => null;
end case;
end process;
end RTL;
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