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On Fri, 17 Mar 2006 13:25:59 -0800, "J Silverman" <g1powermac@yahoo.com> wrote: >Hi All, > >I was able to get a bunch of Xilinx XC3042 FPGAs from a dealer and am >trying to find if there is any support software out there still for the >chip. I looked at the current ISE offerings from Xilinx, but none state >they support the XC3042. Does anyone know of anything for the XC3042? > >Thanks, J Silverman First, take Peter's advise. Second read this: http://www.fpga-faq.org/FAQ_Pages/0009_Xilinx_sw_versions.htm Third, take Peter's advise. Cheers, Philip FreidinArticle: 99026
Hi all, In the Virtex-4 UG (ug070.pdf) page 121 it's clearly written that it's possible to inverse the control pins (active high or low) but I failed to find how. In the list of the BRAM primitive attributes (P122) there is no mention of any attribute which permits these inversions. Thanks in advance for answers. Cheers MehdiArticle: 99027
Is this it? <http://www.xilinx.com/webpack/classics/index.htm>Article: 99028
>Conversely, what really happens to the devices not originally allocated >to easypath which have single errors. Are they crushed and returned to >the sandbox? Or do they get a second chance at proving their worth, on >the easypath tester? Why does it matter to this discussion? Xilinx isn't stupid. They will retest or recycle, whichever is less expensive (more profitable) overall. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 99029
>The -g option doesn't change the code. It adds symbol tables so that >data addresses and instruction address points to the source and names >within the source code. I'm not familiar with this particular case, but sometimes the compile-for-debugging option disables some optimizations that rearrange code enough to confuse the debugger. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 99030
Hello Vladimir, DQS/DQ/DM-placement is important. The DDR interface requires correct placement of the LEs and routing to the IOB. Quartus does this only for the DQ-pins specified in the datasheet (even it would maybe be possible for other pins as well by the hardware, but the software does not support this). In my design I had mixed up some DM and DQ-pins (I believed that are handled equally when I made the layout, but this is not the case) -> 3 of my 32 DQ pins are not recognized as DQ pins and the design does not compile. (I found a workaround for the prototypes, but require a layout-change for mass-production...) Regards, Thomas www.entner-electronics.com <v_mirgorodsky@yahoo.com> schrieb im Newsbeitrag news:1142694593.123202.188480@v46g2000cwv.googlegroups.com... > Hello group, > > I have an issue with porting my high-speed DDR interface to Altera > Cyclone II device. As far as datasheet says, Altera Cyclone II device > does not have any dedicated circuitry to support DDR signaling in its > Input/Output blocks for DQ pins. The only thing present in hardware is > the clock delay circuitry on DQS pins. All other DDR logic is > implemented using LUT's and triggers from adjacent Logic Array > Blocks. So, it seams that we have only DQS pins location fixed, > whenever all other DDR pins may float within the selected IO bank. Is > that right? If yes, then what is the reason to denote certain pins on > the Altera Cyclone II package as dedicated pins for DQ input/outputs? > > With best regards, > Vladimir S. Mirgorodsky >Article: 99031
I write a diploma on Partial Reconfiguration. Noticed circumstance that Partial Reconfiguration is used only on Xilinx FPGA. Does support Partial Reconfiguration other producers FPGA? If yes, who yet?Article: 99032
"Valerios" <valerios@chb.net.ua> schrieb im Newsbeitrag news:1142770744.124805.123520@i39g2000cwa.googlegroups.com... >I write a diploma on Partial Reconfiguration. Noticed circumstance that > Partial Reconfiguration is used only on Xilinx FPGA. Does support > Partial Reconfiguration other producers FPGA? If yes, who yet? > 1 Atmel FPGA are fully runtime reprogrammable 2 new LatticeSC i think is also anttiArticle: 99033
Hal Murray wrote: > Xilinx isn't stupid. They will retest or recycle, whichever is > less expensive (more profitable) overall. Stupid isn't the right word. Complacent with their margins is probably a better descripton. It's why they are only a $1.3B company instead of $10-40B dollar company like Sun Microsystems or Microsoft which are similar ages. The founders had some great ideas 21 years ago, and other than incremental refinement, the real innovation in both the business plan and technology has been lacking a bit. The high margins and high costs hinder the growth of their market. http://www.shareholder.com/visitors/dynamicdoc/document.cfm?CompanyID=SUNW&documentID=1014&PIN=&resizeThree=no&Scale=100&Keyword=type%20keyword%20here&Page=25 http://72.14.203.104/search?q=cache:YsLX3NJSemkJ:www.microsoft.com/msft/download/10K%25202005.doc+microsoft+form+10k+2005&hl=en&gl=us&ct=clnk&cd=1 My Idea of making Xilinx successful would be to once again aggressively push the state of the art and grow the company into several related markets That would bring their revenues into the 20B range inside this decade. Reconfigurable computing as a market for Xilinx could have been grown to something in the $50B range by today, but they got stuck in their view of their business plan. I believe some new management, a restructured technology development program, and one could turn Xilinx around this year, and get it back on track as a $50B company over the next decade ... or better. Or any of the A-team FPGA companies, and buy Xilinx at a discount for pennies on the dollar in 5 years.Article: 99034
I'm also a programmer, as working in front of computer day and day, my right hand is so tired and get some pain. So I tried to mouse in both hands. I find that it is really an efficient way to release pains. At first I switched the mouse buttons in windows control panel, but it taken me several steps to finish it, and I can't flip the cursor, so I made a utility. With it I can switch mouse buttons and flip the cursor immediately by pressing a hotkey. I gave it a name: "Ambidexter Mouse", do you want to have a try: www.ambidexter-mouse.comArticle: 99035
Check out Digilent's CPLD boards. Yes, they are some of the smaller versions, but they are still better than a 3042 - and you can use the webpack to program them. (they have a standard Parallel 3 style JTAG port) http://www.digilentinc.com/Products/Detail.cfm?Prod=CMOD&Nav1=Products&Nav2=Accessory Note, these boards are in a 40-pin DIP package - so you can breadboard them, and then socket them later in a PCB. At $18/each you almost can't go wrong. I haven't used one myself, as I was able to snag a Spartan 3e sample pack - but the specs on these chips are not bad. I'm seriously toying with one since I need voltage translation anyway, and I could throw some logic in as a bonusArticle: 99036
It was there in ISE 7.1 but now I've upgraded to ISE 8.1 SP2 and it's gone. What's happened to it? It's even more difficult to tell if a compilation has finished or found an error. Why can't there be an audible warning that a compilation has finished?Article: 99037
In article <1142694775.663304.303780@e56g2000cwe.googlegroups.com>, fpga_toys@yahoo.com wrote: > What historical resources do we have for preserving early FPGA > development? > What web sites and peoples blogs are archiving this information? > > Prior generations left a rich legacy of paper records, but so much of > the early digital generation is being lost. We were lucky to get early > Unix sources archived in the public domain. > > What should be we tring to get released and archived to preserve the > legacy of early FPGA tools? > > Has someone managed to get sources reconstructed for early Altera and > Xilinx tools and possibly released since they have little to no > commercial value these days, and great historical value? The problem you have is the entire concept of copyright/patents have changed the playing field. My generation, a book was a book was a book. This generation, everything is a potential lawsuit.Article: 99038
Hal Murray wrote: > Why does it matter to this discussion? > > Xilinx isn't stupid. You are assuming facts that are not in evidence. ;^)Article: 99039
Hello everyone In the last couple of months, I have become very interested in CPU design. Specially the ones that you can actually build and fire up right on your kitchen table (i.e. the ones you can get into a decent FPGA). I have read the classic texts on the subject (Enoch Hwangs book, Jan Grays articles and scanned all code I could find on OpenCores, to name a few). What I am still missing is some real-world design examples. You know, things like L1 and L2 caches, TLB and all that stuff. Things that differs PicoBlaze from ARM9 :) While ago, I saw a recommendation here in the group about few books that taught state-of-the-art techniques. It contained references to things like the newest ARM, Intel and AMD CPUs. Unfortunately, I cannot find the post anymore. Any idea which book or books it was? (any general recommendation is also very welcome) regards - BurnsArticle: 99040
How is a PCI target FSM related to a configuration read/write? Considering that FRAME# is asserted for one clock cyle only. during config read/write... when FRAME# is asserted target is expected to latch the Address/Command respectively. because after that FRAME# will be de-asserted and DATA/Byte_Enable follows. Now with regards to the Target State Machine: consider the transition of IDLE state to B_BUSY state ( as Describe in Appendix B PCI Spec 3.0 ) it will only to B_BUSY state when FRAME# is asserted and there's a Hit on address decode. Consider this Hit signal: Hit <= ( PCI_AD_REG = BAR0 ) AND MEM_EN else '0'; How can BAR0 be written to ( i.e. filled with 1's ) when the STATE cannot escape from IDLE state since ( Hit is ZERO )? Are my statements incorrect? -- young_leafArticle: 99041
Sorry my previous message was incorrect, "How can BAR0 be written to ( i.e. filled with 1's ) when the STATE cannot escape from IDLE state since ( Hit is ZERO )? " this should be: How can BAR0 be written to when after IDLE state is BUSY state that is when FRAME# is de-asserted it goes back to IDLE state? and FRAME# is de-asserted; is this a STATE lock? since its in IDLE state and FRAME# is de-asserted? -- young_leafArticle: 99042
Hi All, Ok, you all kinda convinced me on this. After three days of searching for support software and not finding any, I started looking for another way of using a more modern FPGA. I was originally looking at the original Spartan (as they came in PLCC84 packaging) but cannot find any for sale in small quantities. So I started looking for ways on how to use a current FPGA in a breadboard, and I came across this site: <http://www.beldynsys.com/quadpacks.htm> They have a bunch of boards that will take SMT components and give you the ability to stick them in a breadboard. I was looking at the Q100-80 one and am wondering if that will work for a Spartan3 in VQ100 packaging. I'm not sure if the difference between VTQFP and TQFP is great enough to cause problems when trying to solder it on the board. Thanks, J SilvermanArticle: 99043
Yes! Thanks, I am sure I would have found it (eventually). You do have to register. We like to keep track of folks who are using these tools. Austin ghelbig@lycos.com wrote: > Is this it? > <http://www.xilinx.com/webpack/classics/index.htm> >Article: 99044
I realize that all the 'freebees' are long gone now, but are there any vendors selling them? Or something *really* similar? For something I'm working on, a small simple board like that would be just perfect. And yes, i know i could make my own, but if i can get a few pre-made, it would be easier then setting up to make just 4 or 5 boards.Article: 99045
In article <1142778956.384637.87990@g10g2000cwb.googlegroups.com>, burn.sir@gmail.com wrote: > Hello everyone > > > In the last couple of months, I have become very interested in CPU > design. Specially the ones that you can actually build and fire up > right on your kitchen table (i.e. the ones you can get into a decent > FPGA). I have read the classic texts on the subject (Enoch Hwangs book, > Jan Grays articles and scanned all code I could find on OpenCores, to > name a few). What I am still missing is some real-world design > examples. You know, things like L1 and L2 caches, TLB and all that > stuff. Things that differs PicoBlaze from ARM9 :) > > While ago, I saw a recommendation here in the group about few books > that taught state-of-the-art techniques. It contained references to > things like the newest ARM, Intel and AMD CPUs. Unfortunately, I cannot > find the post anymore. > > Any idea which book or books it was? > > (any general recommendation is also very welcome) > > > regards > - Burns Might look at Leon3. I think that is what you had in mind.Article: 99046
Rick, -snip- > I am not the one that you attacked. When I initially said I find your > post insulting, I didn't mean it insulted me. OK. I understand. You were (attempting) to point out that I may be out of line. Thanks. Feel free to email me directly with such comments. I appreciate them (really). Posts to the group such as yours can be interpreted differently (wrongly in this case by me). I meant that it appeared > to be insulting the person you were responding to. What you call > gentle poking was really a way of demeaning his comments and attacking > him on a personal level without offering a single factual response to > his statements. > > Do you not see what I mean? Most certainly. -snip again- > You may not take disrespect, but you are quick to dish it out. Go back > to the post from Metal and your reply and tell me how you expect > someone reading it to consider that a respectful post. I do not disagree with you: the gentle poking is sometime angry prodding. It is also open to interpretation. The story of getting the donkey's attention comes to mind. Where one draws a line is subjective. As I said, if you feel the need to alert me, go ahead directly. People do. I am certainly not perfect. I can always improve. -snip some more- > I don't see how you calling "foul" has anything to do with your reply > to Metal and how it appeared disrespectful. You weren't calling foul, > you were dismissing his statements as being unimportant enough to even > deserve a real reply as well as appearing to insult him on a more > personal level. > > Just look at all the rambling, irrelevant statements you have made in > this reply. I think it is clear that you consider your own opinions > far more valuable than anyone's comments on how you are perceived. I will chalk this up to your feeling that I am missing the intent of your orginal post. I've explained why I missed it, and I have told you how others let me know their personnal opinions of my posts. That I used a 2X4 to get the donkey's attention (getting back to the analogy above) may seem extreme to you. Perhaps it was. A posting to me directly with constructive criticism is completely different than one to a newsgroup which can (and does) appear to be a public attack. In fact, any posting in public forum with a negative tone is potentially looked at as a direct attack. Think about that for a moment. > Enough said. Take my comments or leave them. I don't think I can add > anything further that might be useful. I have taken them. And, I see now your point now. It was useful. It can be even more useful in the future. Thanks for taking the time to try to get through to me. In future, just email me directly: when that happens, I know the intent is not to publicly achieve some unknown goal, but to tell me directly what you think (there are more donkey's than you think out there in need of 2X4's). You may notice that sometimes I will retract, or apologize, seemingly out of the blue. These are times I have either reconsidered the post I made myself, or received comments from others. Again, if I can't admit I am sometimes wrong, then I am a real fool, not someone who is just one occasionally. AustinArticle: 99047
Jeff Brower wrote: > Well I can feel the heat building... but I would venture to say that > several of the engineering Yahoo Groups, plus my own engineers, have > taught me there really is an emerging consistency and 'normalness' to > the shorthand. If key tech words, names, and acronyms are misspelled, > then yes that's bad and not excusable. Everything engineers do is language based. Whether it is the use of english (or other popularly used formal and well documented language) for technical communication, or the use of a formal language for description / implementation of a design. Both of these are rules based systems. If one has had a lifetime (or even just a few years) of experience with the first and has been incapable of mastering (or unwilling to master) it, I am unlikely to believe that he will be capable or willing to do the same with the later. The minimal effort necessary to write and speak with precise language that the original poster saved was far less than the effort required by the average reader to understand the his post. Multiply that by the dozens or even hundreds of people that read that post, and it is simply not economically efficient to use the informal language. When I play the role of employer I get to make the economic argument, as I am paying both the writer and the reader(s). When this is not the case, and I am only responsible for one party, this becomes a simple issue of respect; an issue of respect for my and / or another's time. Respect... the momentum of my diatribe is that of freight train barreling out of control... Simple good manners are the way that we show respect to others. Manners, like the use of precise language, should not be turned on and off at will. I simply don't buy the argument that one is capable of doing this for two reasons. The first is that one often does not know until after the fact if the use of the informal language or the ignoriance of good manners will be a source of offense. The second is that the "unimportant" situations provide practice so that the important situations go appropriately. If one is a current student that wants to be employable when she graduates, I offer two pieces of advice. The first is to take as many writing intensive classes in school as time allows. The second, buy a copy of Emily Post's "Etiquette", and read the sections that apply to daily life. Refer back this book when new life circumstances arise and more of this system needs to be understood. Etiquette, like language, is simply another formal system that needs to be learned and practiced to be mastered. I really don't care how smart a person is, if he can not play nice with others (i.e. show respect for) there simply is not room on my team for such an individual. We find plenty of time for fun and informality at this office. Much of the work we do use intensely creative. BUT, I do not believe one can think outside of the system, without understanding and respecting the system. For the record I am a 32 years old. Good language and good manners are ageless. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 99048
Zefant LC3E from http://www.simple-solutions.de/de/products/index.php is similar, it has a less LEDs on board but additional 512MB sram compared to the sample plack board. I am just playing with that board right now, but ASFAIK there will be no volume shipping before April AnttiArticle: 99049
GaLaKtIkUs™ wrote: > Hi all, > In the Virtex-4 UG (ug070.pdf) page 121 it's clearly written that it's > possible to inverse the control pins (active high or low) but I failed > to find how. In the list of the BRAM primitive attributes (P122) there > is no mention of any attribute which permits these inversions. > > Thanks in advance for answers. > Cheers > > Mehdi Although I haven't designed with the Virtex-4 explicitly (mine have been Virtex series II and prior, Spartan 2, 2E, 3, 3E) The inversion is *probably* done automatically for the control signals (not the address or data) through a dedicated mux for normal or inverted logic as the signal enters the BlockRAM. This will not be done through an attribute but through the logic optimization process. Just use inverted logic and note that your results don't add an extra inverter in your completed logic path.
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