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Uwe Bonnes wrote: > > Xilinix has a library of old ISE versions to download. Look araound... Oldest one available is 6.1, and Xilinx website is overloaded or I don't know what, but I'll keep trying. Thanks.Article: 94776
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1137527273.880427.178480@o13g2000cwo.googlegroups.com... > Antti, each of these devices comes from its own wafer. > We do not mix different device sizes on the same wafer. > Regarding speed: > Spartan3E never claimed to be faster than Spartan3. Both use the same > technology. > For S3E, low cost was the primary objective. > The S3E data sheet says: > ...to meet the need of cost-sensitive consumer applications... > ...more logic per I/O... > ...new features improve system performance... > ...more functionality and bandwidth per dollar... > > That's as close as any data sheet will ever come to stating: > "This is not meant to be a speed demon". > Peter Alfke > Hi Peter, no problems even there are missing 10% speed (maybe there isnt I have not finsihed the testing) I just was silently hoping to see higher in-fabric clock speeds I was trying to figure out what are the max clocks that the S3e can work so I tried it out, so for time being the fastest clock am able to use in S3e is about 380MHz, maybe it would work a little higher also but I am not able to produce a higher clock yet :( at first measuremens I got readings like 899MHz but that was a hoax - bad experiment. 380MHz is verified stable working - in S3 -4 speed the similar number is 420MHz so here the 10% decrease I was then looking at max-toggle rate for S3e, and timings specs and did not find any that info so was wondering a little whats up -- Antti Lukats http://www.xilant.comArticle: 94777
Thanks for the replys. It turns out that the funkiness is on a shared DSOCM BRAM... each processor's DSOCM bus hooks into a dual-ported BRAM, when I noticed this is how I had set it up months ago, I made the change for them to share a PLB BRAM instead. Now there is no odd behavior. So, as much as I'd like to know what was going on with that OCM bus, I'll probably have to just move forward with the new stable system. Maybe when I get a break, I will either chipscope or simulate that odd behavior. There is probably a lot I don't understand about the DSOCM business, maybe I forgot to set something somewhere... Anyway, thanks for the replys, they were all appreciated. JoeyArticle: 94778
"Peter Alfke" <peter@xilinx.com> wrote in message news:1137520894.534736.226480@g44g2000cwa.googlegroups.com... > Fred, I agree. I was thinking in terms of external SRAM, where timing > is so much easier and faster. > If the external RAM has to be SDRAM (does it really, is the required > depth so large?), it might make sense to convert the transfer to blocks > of data, assembled in a BlockRAM. > Then there is the question of allowed latency. > Peter Alfke > I don't think I would use the block memories since they're another interface to mess around with. Also if written in Verilog or VHDL it would be a more portable piece of code. It all depends on resources and if the design is close to the limit when there are some spare block RAMs. The fact there's a FIFO creates more latency than any FPGA design can ever add!Article: 94779
Antti, if you want to test or compare the internal fabric speed, you can just build a ring oscillator inside, divide the frequency down in a couple of flip-flops, and observe the frequency on the output pin. Build the oscillator out of a reasonable chain with only one inversion in it. That way you can include or exclude certain routings, carry chains, etc. And the frequency counter gives you tremendous accuracy and resolution. Peter AlfkeArticle: 94780
Hal Murray wrote: > >A second is a simple logic analyzer. Of course, the hard part here is > >writing a Windows (or Mac OS X or Linux) host program. > > USB seems like the obvious choice, but I don't think any of the low cost > demo boards support that. Getting data from the analyzer hardware to the host computer isn't a problem. It's cooking up a nice display on said host computer that's the problem, at least for me. I plead "Hardware guy, your Honor." I will say that it was easier to get my HID stuff working on Mac OS X than it was on Windows. -aArticle: 94781
I already saw the message from Antti about '|' char on German keyboard. So I
installed WebPack 8.1 with some trepidation...
Sadly, *seems* that on XP SP2 with Italian keyboards almost NO control key
works.
Can some other guy verify this ?
I cannot write '@', '#', '[', ']', '{', '}'.. Imagine write verilog code!
CTRL-F doesn't work, also...
It doesn't work even in "float mode". Tried on three different machines,
at work and at home. Machines used different keyboards, and different levels
of update of XP.
Probably someting very stupid is going on... otherwise, Webpack 8.1 editor
(even with SP1) is useless, for an Italian user.
If this it's real... really makes me think Xilinx should honestly re-examine
its internal development process.
I noticed also many other annoying little things:
- "Ctrl" keys doesn't work also: forget about Ctrl-F to find some text.
- In float mode, "Replace" IS in the Edit menu (but NO quick icon), and
Ctrl-H doesn't work
- In float mode, "Find" is IS NOT in the Edit menu (but IS present as an
icon), and Ctrl-F doesn't work.
- Menu windows are sloooooooow... before appearing, a black filled rectangle
appears, then text comes. This on all the machines I tried. Fast machines.
- TAB sequence is screwed in the "New Source Wizard"... try writing a pin,
the press TAB to enter the following one... surprise! need to grab the
mouse.
All of this in the first ten minutes of playing. Very sad.
Sometimes I wonder if Xilinx developers really try to USE what they do, or
are they "just" using blind regression testing scripts in search of the last
1% of performance.
Performance is important, yes, but first address the "mundane" tasks!
Xilinx, usually your support is really second to none. It's one of the
reasons I prefer Xilinx over the A guys.
Please release an hotfix.... do not ask us Italian guys to wait months for
the next service pack...
Meanwhile, back to 7.1SP4, waiting for the next 3 service packs for 8.1 to
reach an "honest" level... Sigh.
Article: 94782"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1137531685.472446.151180@o13g2000cwo.googlegroups.com... > Antti, if you want to test or compare the internal fabric speed, you > can just build a ring oscillator inside, divide the frequency down in a > couple of flip-flops, and observe the frequency on the output pin. > Build the oscillator out of a reasonable chain with only one inversion > in it. > That way you can include or exclude certain routings, carry chains, > etc. > And the frequency counter gives you tremendous accuracy and resolution. > Peter Alfke > hehe, ;) this is the way I am doing it for some already !!! this is great tool to measure things with virtually any accuracy .. I am using Pentium cycle counter to measure frequencies on such FPGA systems that do not have any known reference clock, I have a speical multichannel jtag-bscan connected freqency measurement ip core and analyzer host software, BTW it is included in the Spartan3e sample pack standalone utility to measure the silicon oscillator :) there are some tricks with the ring oscillator, for repeatable results it should be (r)LOC ed to primitives that produces always same routing, also some 'variants' tend to swing at too high frequency so high that it doesnt get a single flip flop to toggle even if there is direct route and one single load. so I have different oscillators, a good one for Spartan3/e is a "2 LUT delay" oscillator, it runs at around 400MHz in S3/e the output is divided by 2 in the same slice and only divied by 2 output is used. on Virtex-4 this oscicllator is unuseable - runs to fast, so some more LT delays need to be in chain to get useable frequency. AnttiArticle: 94783
"Antonio Pasini" <removethis_pasini.a@tin.it> schrieb im Newsbeitrag
news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
>I already saw the message from Antti about '|' char on German keyboard. So
>I installed WebPack 8.1 with some trepidation...
>
> Sadly, *seems* that on XP SP2 with Italian keyboards almost NO control key
> works.
>
> Can some other guy verify this ?
>
> I cannot write '@', '#', '[', ']', '{', '}'.. Imagine write verilog
> code! CTRL-F doesn't work, also...
>
> It doesn't work even in "float mode". Tried on three different machines,
> at work and at home. Machines used different keyboards, and different
> levels of update of XP.
>
> Probably someting very stupid is going on... otherwise, Webpack 8.1 editor
> (even with SP1) is useless, for an Italian user.
>
> If this it's real... really makes me think Xilinx should honestly
> re-examine its internal development process.
>
> I noticed also many other annoying little things:
>
> - "Ctrl" keys doesn't work also: forget about Ctrl-F to find some text.
> - In float mode, "Replace" IS in the Edit menu (but NO quick icon), and
> Ctrl-H doesn't work
> - In float mode, "Find" is IS NOT in the Edit menu (but IS present as an
> icon), and Ctrl-F doesn't work.
> - Menu windows are sloooooooow... before appearing, a black filled
> rectangle appears, then text comes. This on all the machines I tried. Fast
> machines.
> - TAB sequence is screwed in the "New Source Wizard"... try writing a pin,
> the press TAB to enter the following one... surprise! need to grab the
> mouse.
>
> All of this in the first ten minutes of playing. Very sad.
>
> Sometimes I wonder if Xilinx developers really try to USE what they do, or
> are they "just" using blind regression testing scripts in search of the
> last 1% of performance.
>
> Performance is important, yes, but first address the "mundane" tasks!
>
> Xilinx, usually your support is really second to none. It's one of the
> reasons I prefer Xilinx over the A guys.
>
> Please release an hotfix.... do not ask us Italian guys to wait months for
> the next service pack...
>
> Meanwhile, back to 7.1SP4, waiting for the next 3 service packs for 8.1 to
> reach an "honest" level... Sigh.
>
>
Hi
after verifying the hot keys in 'flaot mode' I was a bit 'breathing' as it
is a workaround, until I tried the
|
in float mode - and that doesnt work in float mode either - so we can say it
is confirmed the ISE 8.1 built in editor is useless for non US keyboard
users :(
well I still use my notepad.exe trick to copy the | into clipboard when I
need it, but I guess others are defenetly not willing to use this kind of
workarounds
Antti
Article: 94784
Praveen wrote:
> When exactly should the PCI arbiter remove the GRANT signal of a
> particular device
Zara wrote:
> According to PCI 2.1, grant should be removed when FRAME is asserted.
I don't have 2.1 handy, but I'm looking at 2.2, which AFAIK didn't change
the arbitration signifcantly. Certainly it does NOT suggest that
GNT should be removed when FRAME is asserted, although that is allowed.
GNT can be deasserted on any cycle, but if the bus is idle, there needs
to be a one cycle delay before asserting a different device's GNT.
If GNT is deasserted and FRAME is asserted on the same clock, the
device retains the bus until the transaction completes (just as if
GNT is deasserted during the transaction).
But the arbiter shouldn't automatically remove GNT whenever FRAME is
asserted, unless you want to limit the device's bus occupancy. Once
GNT is deasserted, the device is only allowed to stay on the bus
for the duration of the latency timer. So if no other device is
requesting the bus, it's usually better to leave GNT asserted
("bus parking").
Article: 94785Antti Lukats wrote: > I have following chips for testing: > > 100e > 250e > 500e > > are all of them from the same wafer ?? > > ROTFL that would be nice design, make one wafer and cut smaller pieces for > smaller FPGAs > > hm that may not be impossible actually... just make whole wafer full of the > fabric interlaced with IOB > then cut out different rectangles and get different sized FPGAs If they did mix parts on a wafer, it would be complete parts of specific sizes, not something that can be diced up in various ways. That's called a shuttle run or multi-project wafer (MPW). It's normally done for test chips or very low volume production. I wouldn't expect that Xilinx would be doing that even for ES silicon, though they might well do it for pre-ES design testing. EricArticle: 94786
Marc Guardiani wrote: > A note to anyone who tries to use ISE 7.1 and CPLDs: make sure to > either download the patch for 7.1 (no SP or SP1) or the latest service > pack. This is needed to correct a problem where the CPLD is programmed > with all outputs inverted. Xilinx does not directly list this problem > with 7.1 on their download page. See > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21168 > If this link does not work, search the Xilinx help system for "7.1 cpld > inverted". > > Marc ..and don't use ISE 8.1 either.... See the thread Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1 tho Antti has found a side-door work-around.... Seems those in Xilinx never _actually_ PGM Real CPLD devices ?!! With this low level of focus on CPLDs, is Xilinx about to dump their CPLD line ? [ it seems to be the orphan on the resouce allocations ]? They still leave off the smallest CR2 devices from their Web store too... [All the signs of 'last one leaving turn off the lights ? ] Pity, some looked like nice devices.. -jgArticle: 94787
Hi Adam, > I tried that and I didn't find anything specific for gates, just LUTs > and logic elements. Am I missing something? Er... yes, namely the marketing-gate count. The smallest design unit either in a Xilinx or an Altera FPGA is the LUT. Until around 2002 both Altera and Xilinx used a marketing-department-driven equivalent ASIC gate count. Since the metrics used by Altera and Xilinx for these gate counts were not the same, there was a horrendous amount of confusion, bickering, name-calling, etc, etc. Thus, here on comp.arch.fpga this gate count equivalent was quickly dubbed 'marketing gates'. With the introduction of the Cyclone and Stratix FPGA's, Altera dropped the 'equivalent ASIC gates' formula, since every ASIC engineer laughed his/her head off when presented with these figures. I don't know why Xilinx still sticks with the number - but whatever figure you see in ISE, it's WRONG. So, I suggest that you simply ignore that equivalent gate count stuff. If you need to retarget your design to an ASIC, get a copy of Synplicity's or Mentor's tools, pick the library you need, and see what comes out. Best regards, BenArticle: 94788
hi all, I look the spec of the raggestone board, and i have a few questions : - which boards are currently available for the rhs and lhs header ? Is there a ram board availbale ? -is the jtag connector is compatible with the digilent programming cable ? -is the mode pin (mode 0 1 & 2) are available ? -is there some drivers and example of pci core freely available ? thanks, Xavier.Article: 94789
"Drily Lit Raga" <midicad2001@yahoo.com> schrieb im Newsbeitrag news:1137474383.369314.144310@g43g2000cwa.googlegroups.com... > As I mentioned in another thread, I received a project from a > consultant who supplied the design files, in fact everything. I'm > thinking there MUST be a way to simply program the device (XC95144XL) > from the JEDEC file, but after rummaging around for an hour I could NOT > figure this out! > > Am I missing something besides my brain? > > Thanks, > > DLR > Hi what is the name of the JEDEC file you used? I tested with file named: "bypass_lpt.jed" when I got similar problems, but after renaming to top.jed nothing changed (that is same problem...) well the 'double click' trick still works so its not a major issue AnttiArticle: 94790
<xavier.tastet@gmail.com> schrieb im Newsbeitrag news:1137537526.341234.213560@o13g2000cwo.googlegroups.com... > hi all, > I look the spec of the raggestone board, and i have a few questions : > > - which boards are currently available for the rhs and lhs header ? Is > there a ram board availbale ? > -is the jtag connector is compatible with the digilent programming > cable ? > -is the mode pin (mode 0 1 & 2) are available ? > -is there some drivers and example of pci core freely available ? > thanks, Xavier. > John will answer some of the questions, but for the PCI part as of special agreement Enterpoint can bundle our Ebook "DIY Logic Analyzer" with the Raggestone sales (no extra payments) with the book resources is also a PCI connected logic analyzer ip core that can be used as starting point for developing testing PCI on the RS1 board the onboard JTAG is Cable IV 2mm header so if you use some 3rd party programmer with 2.5mm or flying wires then you need an adapter to the 2mm connector AnttiArticle: 94791
Gentlemen, The issue that Antti is complaining about is indeed an issue but not one related to the ability of iMPACT to program CPLDs (which it can do just fine, thank you) but due to a bug (yes, a bug) that was revealed when the JEDEC file used was named "bypass.jed". It so happens that that name (for no good reason - that's why it's a bug) indicated that iMPACT should treat that device as if no JEDEC file was assigned and therefore only allowed the erase, readback and other functions associated with only BSDL files. We will fix that problem - but for now, avoid using JEDEC files named "bypass" Thanks. Jim Granville wrote: > Marc Guardiani wrote: >> A note to anyone who tries to use ISE 7.1 and CPLDs: make sure to >> either download the patch for 7.1 (no SP or SP1) or the latest service >> pack. This is needed to correct a problem where the CPLD is programmed >> with all outputs inverted. Xilinx does not directly list this problem >> with 7.1 on their download page. See >> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21168 >> >> If this link does not work, search the Xilinx help system for "7.1 cpld >> inverted". >> >> Marc > > ..and don't use ISE 8.1 either.... > > See the thread > Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1 > tho Antti has found a side-door work-around.... > > Seems those in Xilinx never _actually_ PGM Real CPLD devices ?!! > > With this low level of focus on CPLDs, is Xilinx about to dump their > CPLD line ? [ it seems to be the orphan on the resouce allocations ]? > > They still leave off the smallest CR2 devices from their Web store > too... [All the signs of 'last one leaving turn off the lights ? ] > > Pity, some looked like nice devices.. > > -jg > >Article: 94792
Drily, If all that want you to do is program a CPLD you can take the JEDEC file from 4.1i and use it in 8.1i iMPACT to program the CPLD. If you want to regenerate the JEDEC file then you need to get the 4.1i version of ISE and recompile everything (I believe the last archived version in 4.2iSP3). If you want to migrate a complete project from 4.1i to 8.1i, I suggest you contact the Xilinx hotline and open up a case. My guess is that it may require starting from the original source files and running 8.1i ISE on those (in which case you only need the actual original source and not the project file). Hope that helps. Drily Lit Raga wrote: > As I mentioned in another thread, I received a project from a > consultant who supplied the design files, in fact everything. I'm > thinking there MUST be a way to simply program the device (XC95144XL) > from the JEDEC file, but after rummaging around for an hour I could NOT > figure this out! > > Am I missing something besides my brain? > > Thanks, > > DLR >Article: 94793
Hey, Mabe this helps. this is primarily for APEX devices but it will give you some idea http://www.altera.com/literature/an/an110.pdfArticle: 94794
It doesn't work even if you create a new project in 8.1 with the design and constraint files?Article: 94795
Great news for the pci starting point which could be very interesting :) In this ip core we can connect external data bus to the board to monitor it, or it monitors the pci bus itself ? I check my digilent cable, and the pin assignement is not the same, some adaptation will be easy to do. X.Article: 94796
Xavier Raggedstone1 comes free with a programming cable PROG2. The mode pins are connected together and go through a 0R resistor to 0V so not easy to change. Boards that are now available for the DIL headers: ADC_AD7927 200KHZ - 16 channel ADC based on Analog Devices AD7927 RS232 RS485 PS2 - Mouse and keyboard LED Array LED 4 Digit LED Dot Matrix USB1.1 - Interface only (core needs to be implemented in FPGA) LVDS oscillator module (0.6 inch DIL) - Being tested shortly available assuming ok. Capable of going to 700MHz although I don't the Spartan-3 will like it that high. There isn't a RAM board yet but there is a slowish 4MBit RAM chip that will fit the DIL on the LHS. A RAM module is being looked at and coming soon. We are waiting for some faceplate/cable assemblies for some of these so stock is a bit patchy at present. This status should improve within the next few weeks and after that I expect them to be fully available. Coming in the next batch are Ethernet Phy, IDE, Video Codec, 5V tolerant I/O to name a few. I don't have the full list with me so those are just the ones I can remember. These should be available in 4-8 week time frame assuming no design issues. PCI Core - The Xilinx core works with our board and Jungo supply drivers for that core. Not free I'm afraid. I believe at least one of our customers has got the opencores PCI working as well. I don't know the driver status on this core. We have not tried it so I can't comment further. We are also at the testing stage on our own native PCI/OPB Bridge Interface and a driver for XP is being written for it. Linux to follow. A limited version/license will be offered free with Raggedstone1 when we are happy with it's performance. Higher feature level versions will be available too at an extra cost but low usage licenses won't be too expensive. John Adair Enterpoint Ltd. - Exhibiting at DATE2006. http://www.enterpoint.co.uk <xavier.tastet@gmail.com> wrote in message news:1137537526.341234.213560@o13g2000cwo.googlegroups.com... > hi all, > I look the spec of the raggestone board, and i have a few questions : > > - which boards are currently available for the rhs and lhs header ? Is > there a ram board availbale ? > -is the jtag connector is compatible with the digilent programming > cable ? > -is the mode pin (mode 0 1 & 2) are available ? > -is there some drivers and example of pci core freely available ? > thanks, Xavier. >Article: 94797
Don't need to do it see my other post. If you real want to use then Digilent cable then we have an adaptor module for 6x1 digilent style or if you want to make a board with a 6x1 2mm that too. We have it for our Broaddown2/MINI-CAN products that use 6x1 heads. John Adair Enterpoint Ltd. - Some to be home of Broaddown4. The Ultimate Virtex-4 PCI-E Development Board. http://www.enterpoint.co.uk <xavier.tastet@gmail.com> wrote in message news:1137540056.542843.66450@z14g2000cwz.googlegroups.com... > Great news for the pci starting point which could be very interesting > :) > In this ip core we can connect external data bus to the board to > monitor it, or it monitors the pci bus itself ? > > I check my digilent cable, and the pin assignement is not the same, > some adaptation will be easy to do. > X. >Article: 94798
john, I've just check the jungo website ans they said : "In Linux and Windows CE versions - Driver is operational for 60 minutes after re-starting it." about the free windriver. the full driver is about 800 $... snif snif :'( I'll carrefully check the website during the next week :) thanks, Xavier.Article: 94799
Kees, Kees Bakker wrote: > John Williams wrote: > > >>tony.p.lee@gmail.com wrote: >> >>> Is it true that uCLinux does not have protected kernel memory? >>>A simple programming loop index comparision error can wipe out the >>>system memory including kernel. >> >>Yes, that's true. The "uC" in uClinux implies no MMU, so no memory >>mapping or protection. > > That's not true for uClinux in general. If your target has MMU uClinux > can/will use it. > Take a look at the uClinux source tree and you'll find all kinds of > targets with or without MMU. I'm afraid that's not correct. The uClinux source tree has all those arches in it because it is a direct import of the most recent 2.4 kernel (current 2.4.31). The only real difference between a vanilla linux kernel tree, and a uclinux kernel tree is the directory linux-2.4.x/mmnommu. For uClinux builds (when NOMMU is defined), this subdir is built, rather than linux-2.4.x/mm. Simple as that, the rest is essentially arch-specific details. uClinux only giveth - it taketh not away from the regular kernel :) For 2.6, uClinux no-MMU support is in the mainline kernel - linux-2.6.x/mm/nommu.c It is possible to run uClinux on MMU hardware, such as i386 and ARM - the MMU is just not enabled, and everything runs in a flat address space. The ARM noMMU maintainer has done some interesting work comparing uClinux vs regular Linux on an MMU-enabled ARM CPU - he found that context switch time was an order of magnitude better using uClinux than regular Linux: http://opensrc.sec.samsung.com/document/uc-linux-04_sait.pdf Anyway this is all going way OT for c.a.fpga Regards, John
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