Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I agree and I too am annoyed. Why did they change it to binary?Article: 91776
I'm studying the idea of compressing a Virtex 2 bitstream for storage in non-Xilinx FLASH as well as microprocessor-based FPGA loading. I wonder if anyone knows of statistics on what compression ratios can be attained for designs of various degrees of complexity. The design I am looking at will compress to about 100K from 500K (using WinZIP as a benchmarking tool). Utilization is moderate and it does not have lots of ROM initializations in the bitstream. Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91777
Rick North wrote:
> I agree and I too am annoyed. Why did they change it to binary?
We didn't get a resolution to this discussion last time it came up...
the following was pasted from
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/463e8ef573f4d6dc/5c9c56139ab0ab9e
http://tinyurl.com/aaluz
] I'm guessing it wasn't paranoia, because they provide a way to import
] and export information to/from the new binary .ise file:
]
] http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21067
]
] My WAG is that they mistakenly thought they needed to go binary to
] improve the speed of the GUI (which can be sluggish with large
] projects, even on a decently fast machine).
Now that I've had months to thinking on it, maybe it was paranoia -
they just had to get over it because customers complained. Doubt we'll
ever know.
Have fun,
Marc
Article: 91778"sharpa17@gmail.com" wrote: >Is there a way to add files to a Xilinx ISE 7.1 project with a script >file or the command line instead of using the "Add Source ..." option >in the Project menu? Learn how to write makefiles, and use gnu make. Then don't worry about Xilinx GUIs again, excluding the tools that should be graphical: FPGAeditor and FloorPlanner. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 91779
There are three things here.. what don't you understand?? They are both basic concepts 1/ GBUFs (global clock buffers) are for driving internal clock nets. 2/ if it looks like a clock then its ok... 3/ clock out = any bit of a binary divide by n counter. What's so hard about any of those ? If you are finding English difficult.. I would suggest finding a translator :-) If you don't understand the basics of digital logic.. get a book and learn... FPGAs are no different to a PCB with its logic... only its smaller, faster and bugs are easier to fix. (mostly) Simon "Marco" <marcotoschi@nospam.it> wrote in message news:dl1opq$88v$1@nnrp.ngi.it... > > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:43745f0f@news2.actrix.gen.nz... > > It doesn't really matter how you create it.. as long as its in the right > > phase for what you need to do... just try to avoid outputting the output > > of > > a GBUF. > > I think the best output is a divide of one of the system (internal)clocks. > > > > Simon > > > > > > Sorry Simon, but I don't have understood. > > Could you explain please? > > Thanks > Marco > >Article: 91780
Well you did buy "value ram" :-) Don't forget that this sort of memory is designed for a PC and may not nessasariarly be as good as you (or even they) claim. If you want a better idea have a lot at toms hardware or one of the other PC testing sites. You will see they don't recommend anything but good quality RAM if you want performance. Sloppy timings are easy to get away with these days as SDRAM has timings in the EEPROM so you can make it work and the average consumer won't every know. If you are working anything above the 133 and trying to get top performance, then value ram might not be a good solution. Even working at exactly 100% might be bad... PC's have cache so no one ever expects the RAM to be 100% Simon "Jonathan Schneider" <jon@jschneider.tenreversed> wrote in message news:m264qyjmu5.fsf@jschneider.tenreversed... > Some weeks ago I posted a question, the answer turned out to be a > dodgy SDRAM controller. Any that's working well now [runs out and hugs > tree]. > > However at the time I suspected Kingston ValueRAM which turned out to > be unfounded. However there is something very strange about them. They > seem to be built, not only using re-painted chips but having them two > high. The modules we thought had sixteen chips (plus prom) in fact has > thirty two when you look more closely. A few pins don't connect > between the two decks and there seems to be a wafer in between. > > Of course this does put twice the capacitive loading on the control > lines which wouldn't help if we wanted to run at a decent speed. Am I > being paranoid are do they do some sort of re-manufacturing using > dodgy chips by perhaps fusing data lines on bad chips to end up with a > module that works properly ? > > JonArticle: 91781
Actually.. its not the PCI or USB that will kill you.. its the hard disk write speed. 28 Mbytes/sec to 58Mbytes/sec Simon "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1131713514.31956.0@nnrp-t71-02.news.uk.clara.net... > I'll add to that and say that the USB controller in the PC is probably > sitting on a PCI bus or at least affected by the traffic on it. Also worth > saying fastest USB is 480 MBit/s excluding overheads and 32bit/33MHz PCI is > 1056 MBit/s excluding overheads. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message > news:43746c57$0$355$da0feed9@news.zen.co.uk... > >> Hi > >> Does anyone have some advice for the fastest say to get many MBytes of > >> data from a Spartan3 fifo to the hard disk of a PC via usb. I assume > >> that it is a combination of the best USB interface next to the FPGA and > >> perhaps a USB chipset in the PC that can do some very clever DMA. > >> I don't want to mess with custom RAID stuff I just want to dump it to a > >> standard hard disk & controller. > >> Any pointers appreciated. > >> Colin > > > > > > Colin, > > > > I think a PCI interface capable of bus mastering will still be faster than > > a USB2.0 interface. > > > > The PCI performance is slightly un-deterministic as it depends what else > > is > > on your bus, but from what I've read here over the years I think 80MB/s is > > a reasonable expectation. > > > > I half remember reading that although USB 2.0 gives you 460(?) Mb/s that > > this doesn't directly translate ~ 460/8 MB/s of data through-put (ie > > 60MB/s). > > > > > > Nial. > > > > > > ------------------------------------------------------------- > > Nial Stewart Developments Ltd > > FPGA and High Speed Digital Design > > www.nialstewartdevelopments.co.uk > > > >Article: 91782
I have some troubles with english... sorry. Google translator is not very good. If I have understood I must avoid using a GCLK out pin. Instead I can use which pin I desire, right? Clock frequency is not a trouble. Many Thanks MarcoArticle: 91783
Martin wrote: > I'm studying the idea of compressing a Virtex 2 bitstream for storage in > non-Xilinx FLASH as well as microprocessor-based FPGA loading. I wonder if > anyone knows of statistics on what compression ratios can be attained for > designs of various degrees of complexity. The design I am looking at will > compress to about 100K from 500K (using WinZIP as a benchmarking tool). > Utilization is moderate and it does not have lots of ROM initializations in > the bitstream. I see you are following my lead: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/2045bb02ac582720 My latest baby: XC2VP50, about half FFs (& 2/3 slices) used. gzip -9 reduces the file size from 2.322M to 498k. I think that amount of compression is typical for most designs. I haven't seen anything much worse than that. I recommend avoiding Windows compression utilities (such as WinZip) because sometimes the decompression will need to take place on a small microcontroller. Something like gzip has the added benefit of being open source. Regards, AllanArticle: 91784
I was wondering what anyone else's experience ahs been with getting hold of Virtex4 FX 20 and 60 devices (The ones with the up to 10 GBPs MGTs). I have had 3 of the XC4VFX60-10FF672CES2 (That is engineering sample stepping 2) devices on order since May this year, originally with a 6 week lead time. I have had constant series of delays for no clear reasons given by our local agent (I'm in Australia). Xilinx won't talk directly, everything has to go through this agent MEMEC, the sole authorized distributer for Xilinx in Oz. They are either unwilling or don't have the info themselves. I get given snippets about speed of the MGTs , yield problems, new speed grade desiginations but no real info. The Xilinx website has nothing but its totally positive marketing hype. To add insult to injury I was due to get my chips late October. At this time MEMEC was bought by AVNET, all the puchase orders with xilinx were reraised under the AVNET banner but they stuffed up and reraised at the current market leadtime of 16 weeks odd! I have a fully designed (12 layer) PCB which is fully populated with a big blank where the FPGA is to go and its seriously delaying our whole project. The project also relies on the 10 GBPs serial data rate capability of the V4 RocketIOs. Do any of you people not so far away from the source as I am know what the story is with the FX devices? Should I be redesigning my sytem to use external SERDES and not rely on the V4 FXs coming along. I spoke to one of the hard to find parts specialists in the US and they said the engineering sample V4 devices are free in the US. I'm paying $1300 each for them is this true? When I looked at going back one step to the Viretex2 pro X 10 GBPs devices I find all reference to the -5 10 GBPS devices has totally vanished from the Xilinx datasheets. What's going on here? Paul RArticle: 91785
John Adair schrieb: > As to compliance you probably find it is either the capacitive load, or the > trace length from the connector that don't meet the specification. The plain fact that there is a level translator present is a violation of the specification. Section 4.4.3.4: "It is specifically a violation of this specification for expension boards to: * Attach any pull-up resistors or other discrete devices to the PCI signals, unless they are placed *behind* a PCI-to-PCI bridge." > We have > never seen or heard of an issue with our own boards when using bus switches > in the PCI interface. This seems to be general consensus. The PCI-spec just is to old to foresee todays voltage level problems. When the spec was written they could not imagine any good use for discrete devices on the signals but they were allready seeing abusive use of discrete devices in prototypes. So the board forbid them. Kolja SulimmaArticle: 91786
"Paul R" <paul_p_roberts@bigpond.com> schrieb im Newsbeitrag news:eBEdf.16405$Hj2.13728@news-server.bigpond.net.au... > I was wondering what anyone else's experience ahs been with getting hold of > Virtex4 FX 20 and 60 devices (The ones with the up to 10 GBPs MGTs). I have > had 3 of the XC4VFX60-10FF672CES2 (That is engineering sample stepping 2) > devices on order since May this year, originally with a 6 week lead time. I > have had constant series of delays for no clear reasons given by our local > agent (I'm in Australia). Xilinx won't talk directly, everything has to go > through this agent MEMEC, the sole authorized distributer for Xilinx in Oz. > They are either unwilling or don't have the info themselves. I get given > snippets about speed of the MGTs , yield problems, new speed grade > desiginations but no real info. The Xilinx website has nothing but its > totally positive marketing hype. To add insult to injury I was due to get my > chips late October. At this time MEMEC was bought by AVNET, all the puchase > orders with xilinx were reraised under the AVNET banner but they stuffed up > and reraised at the current market leadtime of 16 weeks odd! > > I have a fully designed (12 layer) PCB which is fully populated with a big > blank where the FPGA is to go and its seriously delaying our whole project. > The project also relies on the 10 GBPs serial data rate capability of the V4 > RocketIOs. Do any of you people not so far away from the source as I am know > what the story is with the FX devices? Should I be redesigning my sytem to > use external SERDES and not rely on the V4 FXs coming along. I spoke to one > of the hard to find parts specialists in the US and they said the > engineering sample V4 devices are free in the US. I'm paying $1300 each for > them is this true? > > When I looked at going back one step to the Viretex2 pro X 10 GBPs devices I > find all reference to the -5 10 GBPS devices has totally vanished from the > Xilinx datasheets. What's going on here? > > Paul R > Hi Paul, As mr Murphy is still so things go wrong. It is clear that more than expected has gone wrong with V4. I was considering using V4MGT in a design where we needed proof of concept proto in July 2005 and full working proto within a few months after that. As of the information from disties that schedule looked tight but possible. Luckily our project delayed anyway so it wasnt a problem for us that V4 MGTs delayed. Memec was sold early 2005, but the final sales required a US court decision (about possible violation of Anti-monopoly laws) - so the somewhat unclear time surely did not make the communication with the disties any better. If your product needs to use non-ES FX60 silicon, then you can not ship it before end of Q3 2006. If that doesnt fit your schedule, then you need to look for alternatives. If you could start shipping of the product based on working ES silicon then the timing looks better. I also do not know if the 10GB is the problem making part of the current silicon, but some MGT ES silicon defenetly is available as of today. But your chances to get right now (without leadtime) from disti are NIL. FPGA manufacturers (and their disties) do not have official or unofficial 'samples' programme. Not in US not in Australia. That doesnt mean that it is not possible to get samples. I guess some key customers defenetly get them, and sometimes others as well. In your case, well here is what I would do: Take a screenshot of the PCB that designed with FX60, add some short description of the project, and send that to xilinx direct. With a simple promise that the PCB goes to fabrication the same day you receive fedex tracking # for the parcel with FX sample that is on the way to you. You may have to provide additional info about the intended use, etc, but my bet is that if Xilinx actually has ready some silicon in the package that you need you will get it. Antti BTW nice to see interest in V4 in Australia ! I always wanted to visit AU - it will come true next tuesday but unfortunatly only 1 hour in Sidney airport transit lounge :(Article: 91787
Paul I'll join Antti and say that you want to find out your support FAE at whatever flavour of Avnet you have out there. Silicon allocation when parts are short does tend to go large customers first but if you can make a good case sometimes doors will open. Not particularly giving things away I believe things are being done to ease the shortages but do talk to your FAE for the detail. If your redesigning for external serdes I believe the LX and SX parts are now not bad to get hold off in the main. John Adair Enterpoint Ltd. - Soon to be home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Paul R" <paul_p_roberts@bigpond.com> wrote in message news:eBEdf.16405$Hj2.13728@news-server.bigpond.net.au... >I was wondering what anyone else's experience ahs been with getting hold of > Virtex4 FX 20 and 60 devices (The ones with the up to 10 GBPs MGTs). I > have > had 3 of the XC4VFX60-10FF672CES2 (That is engineering sample stepping 2) > devices on order since May this year, originally with a 6 week lead time. > I > have had constant series of delays for no clear reasons given by our local > agent (I'm in Australia). Xilinx won't talk directly, everything has to go > through this agent MEMEC, the sole authorized distributer for Xilinx in > Oz. > They are either unwilling or don't have the info themselves. I get given > snippets about speed of the MGTs , yield problems, new speed grade > desiginations but no real info. The Xilinx website has nothing but its > totally positive marketing hype. To add insult to injury I was due to get > my > chips late October. At this time MEMEC was bought by AVNET, all the > puchase > orders with xilinx were reraised under the AVNET banner but they stuffed > up > and reraised at the current market leadtime of 16 weeks odd! > > I have a fully designed (12 layer) PCB which is fully populated with a big > blank where the FPGA is to go and its seriously delaying our whole > project. > The project also relies on the 10 GBPs serial data rate capability of the > V4 > RocketIOs. Do any of you people not so far away from the source as I am > know > what the story is with the FX devices? Should I be redesigning my sytem to > use external SERDES and not rely on the V4 FXs coming along. I spoke to > one > of the hard to find parts specialists in the US and they said the > engineering sample V4 devices are free in the US. I'm paying $1300 each > for > them is this true? > > When I looked at going back one step to the Viretex2 pro X 10 GBPs devices > I > find all reference to the -5 10 GBPS devices has totally vanished from the > Xilinx datasheets. What's going on here? > > Paul R > >Article: 91788
That depends if you have a RAID array but certainly a restriction on signle disk systems. "Simon Peacock" <simon$actrix.co.nz> wrote in message news:4376e6b2@news2.actrix.gen.nz... > Actually.. its not the PCI or USB that will kill you.. its the hard disk > write speed. 28 Mbytes/sec to 58Mbytes/sec > > Simon > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in > message news:1131713514.31956.0@nnrp-t71-02.news.uk.clara.net... >> I'll add to that and say that the USB controller in the PC is probably >> sitting on a PCI bus or at least affected by the traffic on it. Also >> worth >> saying fastest USB is 480 MBit/s excluding overheads and 32bit/33MHz PCI > is >> 1056 MBit/s excluding overheads. >> >> John Adair >> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development >> Board. >> http://www.enterpoint.co.uk >> >> >> "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message >> news:43746c57$0$355$da0feed9@news.zen.co.uk... >> >> Hi >> >> Does anyone have some advice for the fastest say to get many MBytes of >> >> data from a Spartan3 fifo to the hard disk of a PC via usb. I assume >> >> that it is a combination of the best USB interface next to the FPGA >> >> and >> >> perhaps a USB chipset in the PC that can do some very clever DMA. >> >> I don't want to mess with custom RAID stuff I just want to dump it to >> >> a >> >> standard hard disk & controller. >> >> Any pointers appreciated. >> >> Colin >> > >> > >> > Colin, >> > >> > I think a PCI interface capable of bus mastering will still be faster > than >> > a USB2.0 interface. >> > >> > The PCI performance is slightly un-deterministic as it depends what >> > else >> > is >> > on your bus, but from what I've read here over the years I think 80MB/s > is >> > a reasonable expectation. >> > >> > I half remember reading that although USB 2.0 gives you 460(?) Mb/s >> > that >> > this doesn't directly translate ~ 460/8 MB/s of data through-put (ie >> > 60MB/s). >> > >> > >> > Nial. >> > >> > >> > ------------------------------------------------------------- >> > Nial Stewart Developments Ltd >> > FPGA and High Speed Digital Design >> > www.nialstewartdevelopments.co.uk >> > >> >> > >Article: 91789
Phil Hays <Spampostmaster@comcast.net> writes: > Learn how to write makefiles, and use gnu make. Then don't worry > about Xilinx GUIs again, excluding the tools that should be > graphical: FPGAeditor and FloorPlanner. I agree strongly! Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 91790
hi, im trying to use the i2c opensource IPCore to control my CMOS image sensor through i2c interface. The sensor can only work as a i2c slave. it does not contain any pullups internally for scl/sda, so i add them with in the FPGA ( spartan 3 ). i dont use any external resistors for this. Is this acceptable? when monitored by the chipScope logic analyzer, it seems like the sensor does not acknowlege when i write the device address Plus write bit. im sure the device address i sent is correct. the sensor im using is KAC-9630 from Kodak. Please let me know if someone can figure this out. Thank You. CMOSArticle: 91791
Thank you so much Peter. We are using the 4:1 rule. Regards, Ajay Peter Alfke wrote: > Yes, I agree. > Inside the chip, we make sure that the delay tolerances on a global > clock are less than the min delay clock-to-Q, and we can guarantee > that, since delays track inside the chip. > Between chips, the min delay is important since the clock delay > differences are determined by the pc-board, and the transmitting device > may also have nothing in common with the receiving device (neither > temperature nor processing, although probably voltage). > > That's why source-synchronous design is now popular (sending the clock > together with the data) and IDELAY in Virtex-4 gives you the ability to > delay clock or data by a precise amount, so that you can achieve > near-optimal relative timing. > Peter AlfkeArticle: 91792
Most I2C pullups are in the region of 2k ohm or so (maybe less). That's far lower than the pullups inside most Xilinx parts (typically 25k - 50k). There are excellent app notes at Philips (the inventors of I2C) on this. http://www.semiconductors.philips.com/markets/mms/protocols/i2c/ Cheers PeteSArticle: 91793
hi, im in the need to implement the following scenario. there will be several PC's with each having a modem and a telephone connection. No PC has the internet access. All PC's should have the ability to connect to any other PC by just dialing the corresponding telephone number. After connected, they need to communicate using the TCP/IP protocol. ( i.e i need to use Sockets in the communication.). PC's will have Windows Me/98 as the O/s. (this is similar to what happens with hyperterminal, but i think the difference is the protocol used in the communication.) Is this scenario possible? Please give me a starting point. Thnak You. CMOSArticle: 91794
Can any one donate me a xilinx FPGA based development kit. I need it , because my previous FPGA pins are not working. I was using a SPARTAN XCS10 , but this fpga is no more available. thanxArticle: 91795
While this is not the right group to ask, I guess I can give you a starting point. Possible it is - I am doing it routinely even on a single system, having two completely independent tcp/ip subsystems engaged in a ppp connection, the one of the two asking for IP address and the other supplying it. However, this is done under DPS (which I have written) and was used while I tested my tcp/ip implementaton. Whether you can make the MS system behave like an ISP responding point when called I don't know (I am not familiar with windows etc. stuff). Hope this helps a litle. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 91796
I've some good news to relay on the ISE 8.1 front... I got a beta recently on a DVD... It installed flawlessly on a Knoppix Debian (4.02 I believe) machine. New 2.6 kernels don't seem to be a problem, unlike the horrific installation difficulties of ISE 7.1 with recent distros. More good news... Webpack ISE 8.1 includes Coregen, and ... wait for it... FPGA EDITOR!!! (this was mentioned in the previous articles, but I think it deserves more celebration :-) Plus the ISE 8.1 Webpack now supports the ISIM simulator under Linux, which can now do mixed mode VHDL/Verilog simulations. I'm guessing the Webpack release will be just before Christmas. JohnArticle: 91797
CMOS wrote: > hi, > > im trying to use the i2c opensource IPCore to control my CMOS image > sensor through i2c interface. The sensor can only work as a i2c slave. > it does not contain any pullups internally for scl/sda, so i add them > with in the FPGA ( spartan 3 ). i dont use any external resistors for > this. Is this acceptable? > > when monitored by the chipScope logic analyzer, it seems like the > sensor does not acknowlege when i write the device address Plus write > bit. im sure the device address i sent is correct. the sensor im using > is KAC-9630 from Kodak. Please let me know if someone can figure this > out. Xilinx do not guarantee a minimum pullup current. They used to (IIRC the value was 25uA) but this led to problems with designers thinking they could use the pullups in lieu of resistors on their boards and running into problems with leakage current and poor risetimes. You should read the I2C specification. It will make it pretty clear you're doing something wrong. (In general, you should read specifications *before* you design your system.) Chipscope is good for looking at what is going on inside the chip. I suggest you use an oscilloscope instead. Regards, AllanArticle: 91798
> I recommend avoiding Windows compression utilities (such as WinZip) > because sometimes the decompression will need to take place on a small > microcontroller. Something like gzip has the added benefit of being > open source. Agreed. I just started looking into this and using WinZIP is a lazy first step to get a sense of proportion. My gut feeling is that it would be perfectly safe to allocate space equivalent to 50% of the uncompressed bitstream. If less is used, fine. The problem I have is that the design is likely to change after the product is released...so, I can't nail down the configuration file at this stage of the game. I'm tempted to start with RLE. It would be easy to implement a decompressor with a small uC and limited register/ram resources. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91799
> > I'm tempted to start with RLE. It would be easy to implement a > decompressor with a small uC and limited register/ram resources. Did bitstream compression in my last project. Used LZW. RLE didn't improve so much vs. "internal" xilinx compression. For many reasons we had to reconfigure FPGA very quickly; with some care to code, was blazingly fast. Here are some compression ratios on that design: CAMERA_COMP.BIN 97944 uncompressed After LZW compression: BIT SIZE 10 73475 11 65442 12 62865 13 58795 14 57687 Google Groups around with "compressing Xilinx bitstreams some test data" or retrieve the thread clicking here: http://tinyurl.com/arusq
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z