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Hi everyone. I am designing a new board with FPGA. I have many memory devices but 3 of them (sram, flash and RTclk) will be connected to the same bus. The fact is that RTclk has 5 bits address bus and 8 bits data bus. I would like to be sure of not having Fanout problems (in just 10 lines of bus). I think I have to check input capacitance of the memory devices and output capacitance of FPGA and viceversa to apply the following formula toh= (MCi+Co)*K, with k depending on Roh. Could you explain how to get Roh and toh. I would like to work with 65MHz, probably 100MHz. Thank you for any helpArticle: 91876
hi jvdh.. we r also facing the same problem.. we r using coolrunner 3 xcr3256 chip in our project.. the output pins r stuck at 0 v,, where we can find the SP4 .. what else we need to care in synthesis options for working the code properly.. thanking u in advance. jvdh wrote: > Downloading and installing SP4 from the Xilinx site eventually solved > my problems... > > johannesArticle: 91877
With the static IP packet, I mean that you try to send out exactly the same IP packet that your sample uses. Instead of implementing an entire IP stack, you could use Ethereal to capture a good packet, look at the hex dump, and copy it exactly in your VHDL code. Then repeatedly send out that packet. If you don't see your packet on Ethereal, but you see the sample, there must be a difference. Put your scope probes between the PHY and the FPGA to watch the digital signals. Compare between the two. Check the preamble, bit order, timing, CRC. Also, don't forget to pad your data if it's too short.Article: 91878
Is anyone else having problems with the ISE service pack 4 installer
crashing on Linux (any flavour)? SP2 worked all right for me, but it
seems they broke something in SP4. Anyways, to work around this, I
wrote a ten line shell script to replace Xilinx's setup program. Sorry
it doesn't display any marketing propaganda while installing.
cheers,
aaron
#!/bin/sh -x
#
# replace Xilinx's 'setup' with file and set the XILINX variable
appropriately
#
XILINX= some path to install to
install (){
if [ ! -x `dirname $2` ]; then
mkdir -p `dirname $2`;
fi
cp -f $1 $2
}
for i in `cat idata/add.mnf`; do
install add/$i $XILINX/$i
done
for i in `cat idata/replace.mnf`; do
install replace/$i $XILINX/$i
done
Article: 91879Bob Perlman wrote: > Would it be possible to do just the opposite, and create a high-level > language that lets a digital designer write efficient, > high-performance software the same way he'd design hardware? Because > I'd like to become an expert programmer without expending much effort. Wouldn't everyone .. experience gained without the pain, effort and study. John Expert \Ex*pert"\ ([e^]ks*p[~e]rt"), a. [F. expert, L. expertus, p. p. of experiri to try. See Experience.] Taught by use, practice, or experience, experienced; having facility of operation or performance from practice; knowing and ready from much practice; clever; skillful; as, an expert surgeon; expert in chess or archery. [1913 Webster]Article: 91880
>> So how do we see what data is
>> coming out from the PHY.
>> Please advice ?
>
> With a fast digital oscilloscope ?
or an optiview:
http://www.flukenetworks.com/us/LAN/Handheld+Testers/OptiView/Features/Capture+Filter+Decode.htm
-- Mike Treseler
Article: 91881PeteS wrote: > To expand on Rene's comment, there's no way around RoHS compliance > **anywhere**. Long term, yes. But, I'm not sure that I agree in terms of a mid-2006 hard deadline (which is a ridiculous idea IMHO). As a small manufacturer, if I have to choose between a potential support and reliability nightmare from a shift to RoHS and simply not offering affected product in the EU, I'd go for option #2. New designs can be executed for RoHS compliance from the start, but few small to medium manufacturers are going to go through the trouble, expense and liability of redoing whole product lines unless a non-trivial portion of their business is in the EU. While the EU is an important market, the potential downside of a hasty transition is significantly more severe than the alternative. Logistically, we've seen billion-dollar companies who supply us with components tell us that they will not have RoHS compliant parts available until "sometime in 1Q06". Clearly, migrating a design to RoHS parts in haste --with barely a few months of testing before shipping-- would be a horrendously bad idea. My prediction is that the EU will have to soften the rules a bit because a full transition to 100% compliance by all entities that move product into the region is quite literally impossible. Few legislated hard deadlines, such as this one, ever execute exactly as written. Logistically, it is impossible for the EU to even approach the orders-of-magnitude in potential regulatory work that this will create. The whole thing, if executed by the letter of the law, could be quite damaging to business in general. Something's got to give. Or not. Who knows? It'll be interesting to watch. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91882
Krzysztof Przednowek wrote: > Hi, > Thanks for answers. > >> 1) does the board worj when you use Avnet ref design image ? >> > There was no reference design for PCI included. But I believe board > works. Everything else works fine. Currently I'm workin on some kind of > PCI monitor, to see what is going on. The board works fine for me anyway ... (tried it in two different PCI mother board both 5V and 3.3v) SylvainArticle: 91883
Ajay wrote: > Hi All, > > If any of you folks know how, to calculate the best case timing > parameters for a Xilinx FPGA (for eg: Global clock to out -- the pin to > pin output parameter ) ? > > Googling through the archives , I came across this post from Austin > Lesea posted in 2001. > > Article: 37740 > "We did not tend to specify minimums (although we do now, more and more > in the > newer parts) because it wasn't supposed to matter. Now that it does, > we do > provide that information once the process is stable (the part is in > manufacturing as a regular product, not ES material)...." > > But the device data sheets for a very much in production device like > Virtex-II Pro doesn't provide any best case /Min values for the clock > to out parameter. > > Also ,Another document that gives a lot of info. about approximating > the best case timing is the xcell article > http://www.xilinx.com/xcell/xl21/xl21-40.pdf . But, is this document > relevant for the latest Xilinx FPGAs ? > > > Thanks, > Ajay > Using the "-s min" command line option on trce may get you closer to what you're looking for. It uses an "absolute minimum" speed file, if available for that device family, to run the timing analysis. RussArticle: 91884
On Tue, 15 Nov 2005 22:30:43 GMT, "Martin" <0_0_0_0_@pacbell.net> wrote: >PeteS wrote: > >> To expand on Rene's comment, there's no way around RoHS compliance >> **anywhere**. > >Long term, yes. But, I'm not sure that I agree in terms of a mid-2006 hard >deadline (which is a ridiculous idea IMHO). > >As a small manufacturer, if I have to choose between a potential support and >reliability nightmare from a shift to RoHS and simply not offering affected >product in the EU, I'd go for option #2. New designs can be executed for >RoHS compliance from the start, but few small to medium manufacturers are >going to go through the trouble, expense and liability of redoing whole >product lines unless a non-trivial portion of their business is in the EU. >While the EU is an important market, the potential downside of a hasty >transition is significantly more severe than the alternative. > >Logistically, we've seen billion-dollar companies who supply us with >components tell us that they will not have RoHS compliant parts available >until "sometime in 1Q06". Clearly, migrating a design to RoHS parts in >haste --with barely a few months of testing before shipping-- would be a >horrendously bad idea. > >My prediction is that the EU will have to soften the rules a bit because a >full transition to 100% compliance by all entities that move product into >the region is quite literally impossible. Few legislated hard deadlines, >such as this one, ever execute exactly as written. Logistically, it is >impossible for the EU to even approach the orders-of-magnitude in potential >regulatory work that this will create. The whole thing, if executed by the >letter of the law, could be quite damaging to business in general. >Something's got to give. Or not. Who knows? Remember there is quite a lot of stuff, especially the sort of things that big FPGAs go into, that is currently outside the scope of Rohs - this has not been well covered in the press. Included categories consumer electronics, household appliance, IT/telecom, toys or tools, so most test/lab type equipment is not covered. There are also currently specific exemptions for network infrastructure, and servers Source : http://www.dti.gov.uk/sustainability/weee/RoHS_Regs_Draft_Guidance.pdfArticle: 91885
Newman, Do you know if it is possible to peek/poke the memory via XMD - BRAM or cache memory (ultra-controller mode) without halting the PPC? I heard reading the BRAM can crorrupt it. -TonyArticle: 91886
This is problem:
FPGA - Virtex2
and proces
process
begin
if(i1='1') then
go <= '0';
write <= '0';
reset <= RESET_ACTIVE;
wait until clk'event and clk = '1';
reset <= not(RESET_ACTIVE);
wait until done = '1';
i1<='0';
end if;
end process;
While I sinthesize I have an error : Same wait conditions expected in
all Multiple Waits.
If I take off wait until done = '1' - all is working.
In Xilinx site there are no answer. Please help.
Article: 91887rules wrote: > This is problem: > FPGA - Virtex2 > and proces > > process > begin > if(i1='1') then > go <= '0'; > write <= '0'; > reset <= RESET_ACTIVE; > wait until clk'event and clk = '1'; > > reset <= not(RESET_ACTIVE); > wait until done = '1'; > i1<='0'; > end if; > > end process; > > While I sinthesize I have an error : Same wait conditions expected in > all Multiple Waits. > If I take off wait until done = '1' - all is working. > In Xilinx site there are no answer. Please help. > Incase of multiple wait statements within a single process, the wait condition must be the same for each occurance (what the error message says). Read the "Multiple Wait Statements Descriptions" topic in the XST Users Guide. Chap 6 : VHDL Language Support > Sequential Circuits. It will give you what you need to know. http://toolbox.xilinx.com/docsan/xilinx7/books/docs/xst/xst.pdf Kunal@XilinxArticle: 91888
Fairly simply put, this is not synthesizable VHDL. What you have here is something that is legal VHDL that can be simulated, but cannot be synthesized. Synthesis supports only a limited subset of the VHDL language, namely, VHDL (or verilog) code that maps to real hardware. Hardware consists of flip-flops, combinational logic (logic gates), and a small number of other things (tristate buffers, etc...). For VHDL code to be synthesizable, the code must describe behaviour that is consistent with these hardware elements. Your code does not... My guess is that this is part of a testbench. A digital circuit (i.e. one that is to be implemented in an FPGA) has inputs that come in from outside the FPGA, and outputs that are driven out of the FPGA. The "stuff" between the inputs and outputs are described using VHDL (or verilog) and then synthesized. When you want to simulate that code, it is necessary to provide signals for the inputs to the digital circuit. These signals can also be generated using VHDL. The code that generates these signals is called a testbench, and is not synthesized (since it is not part of the circuit being implemented in the FPGA), and hence does not need to restrict itself to the synthesizable subset of VHDL. It looks like this may be some portion of such a testbench. Digital circuits usually have a "reset" input; often called "reset". To simulate such a circuit, it would be necessary to generate a pulse on the reset input, which seems to be what this code is doing. Avrum "rules" <rulllesss@rambler-dot-ru.no-spam.invalid> wrote in message news:fKadnRDOoaqkFefeRVn_vA@giganews.com... > This is problem: > FPGA - Virtex2 > and proces > > process > begin > if(i1='1') then > go <= '0'; > write <= '0'; > reset <= RESET_ACTIVE; > wait until clk'event and clk = '1'; > > reset <= not(RESET_ACTIVE); > wait until done = '1'; > i1<='0'; > end if; > > end process; > > While I sinthesize I have an error : Same wait conditions expected in > all Multiple Waits. > If I take off wait until done = '1' - all is working. > In Xilinx site there are no answer. Please help. >Article: 91889
tony.p.lee@gmail.com wrote:
>Newman,
>
> Do you know if it is possible to peek/poke the memory via XMD - BRAM
>or
>cache memory (ultra-controller mode) without halting the PPC?
>
>I heard reading the BRAM can crorrupt it.
>
>-Tony
>
>
>
From Xilinx Answer 8181:
1. If Distributed RAMs or SRL16s are used in the design, reading back
those LUTs could destroy the contents within if the WE is asserted while
the readback is being performed on those frames.
2. The configuration logic takes over the address lines to the BRAMs, so
those RAMs cannot be accessed or written to while readback of the BRAM
frames is in progress.
IIRC, the BRAM contents themselves don't get trashed provided the WE is
not asserted, but any reads done by the user logic while a readback is
in progress have corrupted data. In other words, you can't use the
bitstream readback while that BRAM is also being used by the PPC.
However, the PPC is probably only using one port on the BRAM. If that
is the case, you could add logic to read back the contents through the
second user port on the BRAM.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91890Tony, Good question! Unfortunately I do not have an answer. In general, poking may present a problem without some type of semaphore protection. I've never used the cache memory in ultra-controller mode. I've observed some strange behavior when peeking memory when the PPC is running. I never was sure whether it was a limitation of the PPC jtag emulation scheme, issues of the BRAM interconnect methodology employed, or pilot error. -NewmanArticle: 91891
you may want to send a length field before the data field too. Simon "ashwin" <achiluka@gmail.com> wrote in message news:1132070251.957774.135520@g47g2000cwa.googlegroups.com... > Hi Arlet > The format i used for the ethernet frame is this: WIth the least > significand bit transferred first. I have a 4 bit interface from fpga > to PHY so i will transfer least significand nibble of each byte every > clock cycle. > > 7 bytes of x"55"; > 1 byte of x"d5"; > 6 bytes of dest MAC address > 6 bytes of source MAC address > DATA -- 40 bytes > 4 bytes of FCS > > What do you mean by static IP packet. Does it include preamble and CRC > too? > The PHY converts the data into MLT-3 signal which is like a sinusoid. > Its hard to decode manually what data is being sent out. > > Ashwin > > > > Arlet wrote: > > Ethereal has no problems showing non-IP packets when it catches them. > > > > Are you sending the correct preamble and SFD ? Do you see the link > > blink on the PC whenever you send something ? Manually copy a static IP > > packet bit by bit in your VHDL code, and send that as a test packet. > > Compare your version with the sample bit file by looking at PHY signals > > with a scope. >Article: 91892
> Remember there is quite a lot of stuff, especially the sort of things that > big FPGAs go into, that is currently outside the scope of Rohs - this has > not been well covered in the press. It's worst than this. The press has little to do with it. The standard itself is nebulous and inconclusive. Some aspects of it are almost comical (no formal way to ascertain compliance...but you can go to jail and be fined up to UK$5,000 for a violation). The real problem is that it has setup a "pass the buck" scenario, as we say on this side of the pond. Resellers ask distributors, who ask manufacturers who ask component manufacturers, for RoHS compliance guarantees. The lack of clarity and apparent intransigence of the system makes resellers and distributors fearful of anything other than "yes, absolutely, it is RoHS compliant". There is no amount of technical maneuvering that can convince someone in fear of a stiff fine and imprisonment that anything other than total compliance is safe. Again, it'll be interesting to watch and see what happens come the middle of next year. To be on-topic. It took our very large distributor almost a month to come up with an RoHS-compliant part number to replace a Virtex 2 we've been using in a design for a couple of years. It surprised me that it took that much work. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 91893
Much depends on the drive that can be provided by the FPGA, so I would need to know the specific device. The effective output resistance depends on the driver characteristics. Note that at those frequencies, terminating the lines is not optional with a distributed bus, and impedance controlled address / data / control would be an exceedingly good idea. Cheers PeteSArticle: 91894
Hi there i am using an old virtex FPGA. My design runs well in post place and routed functional simulation. However it does not on the FPGA and the SDF anotated simulation doesn't either. I get tons of setup violations regarding LUT and Block RAMs. I tried to constain harder like to 25ns whereas my clock period is 30ns but it wont work. The RAMs are not input and not output registered. I need them to be if possible. Why does the place and route tool does not notice that the RAM timing can not be met? 2nd problem: Right now the generate post place and route simulation tool fails. I get an error which i cannot solve: Release 6.3.03i - netgen G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application netgen from file "pcim_top.ncd". "pcim_top" is an NCD, version 2.38, device xcv300, package bg432, speed -6 Loading device for application netgen from file 'v300.nph' in environment /opt0/eda/xilinx/linux/xilinx. Loading constraints from file "pcim_top.pcf"... ERROR:Anno:207 - 6 block(s) were unexpanded, including the following: 'HAL_INST/initiator_inst/rsp_fifo_inst/full2_inst' (TYPE=equal) 'HAL_INST/initiator_inst/rsp_fifo_inst/full3_inst' (TYPE=equal) 'HAL_INST/initiator_inst/rsp_fifo_inst/full4_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty2_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty3_inst' (TYPE=equal) 'HAL_INST/initiator_inst/cmd_fifo_inst/empty4_inst' (TYPE=equal) Unexpanded blocks usually result from incomplete or erroneous configuration of the corresponding components in the .ncd file. ERROR:NetListWriters:528 - Unsuccessfull design annotation. any idea? I am using ISE 6.3. SImulator is cadence ncsim. Thank you so much iam quite desperate.Article: 91895
No. There are no async inputs to my state machine, and only one clock. The problem has been clearly identified as a bad behaviour of PART only of the state machine. That part seems to pickup extra clock edges. I still believe that the problem lies in the shape/reflection/etc.. of the clock. The part of the state machine that fails runs (badly) on itself, no external interaction. Thanks for the comment.Article: 91896
OK. Thanks for the comments. I made a typing mistake about the value of C. C is actually 100 pF with 100 ohms --> 10 nS. But I fully aggree with you about the characteristic impedance --> R should be more like 50 ohms and C 200 pF. The 100 ohms value was the first approach. Aggree on all your comments about series or parallel terminations, and 2-bit counter. I discovered yesterday that the (discrete) driver used for the clock is a 74LVC2244, meaning the presence of an embedded 30 ohms series resistance (OUUPS) in the outputs. Of course, the waveshape at line end with a series termination of 30 ohms at the beginning of the line and a 100ohm/100pF parallel termination at the end must be inadequate, or maybe prone to crosstalk from other lines. I had no chance yet to look at the waveform due to very poor accessibility of the point. Next step is to swap the 74LVC2244 with a standard 74LVC244 (no series resistance in the outputs), tune the RC termination and watch the result. Thanks for all the comments. By the way, was I right saying that there is no way to specify an input hysteresis on the Spartan3 inputs ? A. BeaujeanArticle: 91897
Hi ! I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior. When I go through steps synthesis, P&R and .bit generation every thing is ok. If I launch impact or if I swap to another windows application and back to ISE, all green marks go back to ? and ISE launches the wholel flow !!!! It is a big waste of time ! Does anyone has a clue ? Just one point, there was a ISE 6.3 install on this computer which was not removed correctly. Thank you. Stéphane.Article: 91898
For all of you that asked if we could do better on carriage we now have a low cost option for selected EEC countries. US and New Zealand may be added at a later date once we sorted out how duty collection would operate. Details are on the website on the relevant product pages. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost XC3S400 Development Board. http://www.enterpoint.co.ukArticle: 91899
Any ideas what causes (or better how to avoid) the following crash: Internal Error: Sub-system: FYGR, File: fygr_list_of_labs.cpp, Line: 2934 (atom_id1 >= 0) && (atom_id1 <= m_max_atom_id) && (atom_id2 >= 0) && (atom_id2 <= m_max_atom_id) (Fitter pre-processing) Quartus II Version 5.1 Build 176 10/26/2005 SJ Web Edition Regards, Martin
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Compare FPGA features and resources
Threads starting:
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