Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hey there, I have asked this question in another forum as well but that forum has gone into the 2nd page and I am not sure how many people would bother going to the next page. Anyways, I am trying to implement IIR filter in VHDL. And for that purpose, I need to use Fixed point arithematic. Now, I came accross the VHDL Fixed point packages available at: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html But I am not sure how to use them? I mean how to compile them? where to copy these downloaded files and then how to compile them? using modelsim? but do I need to start a new ISE project and add all these files, if yes, where to create the project folder? So, basically my question (atm) is that how to use these VHDL packages (a kind of a general question)? I gave a little bit of description about what I am doing coz i thought jus in case.......?? Any comments/suggestions at all are welcome, Thanks very much, KamiArticle: 133751
On 7=D4=C213=C8=D5, =C9=CF=CE=E77=CA=B125=B7=D6, "kami" <kamran.wad...@yaho= o.co.uk> wrote: > Hey there, > I have asked this question in another forum as well but that forum has > gone into the 2nd page and I am not sure how many people would bother goi= ng > to the next page. > > Anyways, I am trying to implement IIR filter in VHDL. And for that > purpose, I need to use Fixed point arithematic. > > Now, I came accross the VHDL Fixed point packages available at: > > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html > > But I am not sure how to use them? I mean how to compile them? where to > copy these downloaded files and then how to compile them? using modelsim? > but do I need to start a new ISE project and add all these files, if yes, > where to create the project folder? > > So, basically my question (atm) is that how to use these VHDL packages (a > kind of a general question)? > > I gave a little bit of description about what I am doing coz i thought ju= s > in case.......?? > > Any comments/suggestions at all are welcome, > Thanks very much, > Kami if you use modelsim, just vcom the pkg file first then your other design files I think is just fine.Article: 133752
Il 07/07/2008 17.26, timinganalyzer ha scritto: > Hi All, > > I am pleased to announce this new version of the TimingAnalyzer. The > scripting interface has been added in this version, so users can > develop scripts to draw simple and complex timing diagrams, generate > test vectors, or add new features to the program. Please take it as a constructive comment. You asked for them, here they are. And, of course, this is just my $0.02. I tried hard to use it, on a real design I'm doing now. **Please reconsider your choice of click behaviour** I second Rickman comments. I think he's right. For a Windows user, at least for me, it's so terribly annoying and irritating. I tried yesterday for one hour, and again this morning. I keep adding an unwanted edge just by clicking, keep missing pressing that pesky ESC key to deselect what I don't want... I give up. Even if I see the program has features I would need and like, it's simply too much irritating to use. Yes, I know there's so much things behind, the fact that's is in beta, etc, etc... but GUI is the *first* and *most* important thing in this programs! Otherwise, back to paper and pencil and hand made equations. Please change this design choice, I think a lot of people will simply stop using it *before* even seeing there's so much more functionality. Please add a choice for Windows users to behave as is common accepted practice today on Windows. In any case, looks promising, and I wish you a good success. Choice is always good.Article: 133753
On Jul 12, 12:16 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >On Jul 11, 9:02 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >> >On Jul 11, 2:40 pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > >> >> >On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: > >> >> >> Hai, > > >> >> >> I want to know which is the right way of implementing and usage > of > >> >> >> fixed point number data types in hardware(industry standard)..I > >> have > >> >> >> referred various FIR > >> >> >> implementations where they are mostly handling filter > coefficients > >> as > >> >> >> integer(truncating from fixed or floating point using MATLAB) or > >> >> >> binary.Is it difficult to handle and implement real(fraction) > >> numbers > >> >> >> i.e.,filter > >> >> >> coefficients values directly in the hardware? > > >> >> >Google for fixed point VHDL to_ufixed and you'll get the code for > the > >> >> >standard (or soon to be a standard) VHDL fixed point package. > > >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS27... > >> >> >fixed+point+VHDL+to_ufixed > > >> >> >Kevin Jennings > > >> >> Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA > Target. > >> I > >> >> have found these packages you mentioned in response to this guy's > >> question, > >> >> very good. But I don't exactly understand how to use these > packages? > >> >> Any other comments welcome. > >> >> I am designing a butterworth lowpass filter (atm just 2nd order > >> filter). I > >> >> have implemented it in simulink and could generate VHDL code as > well > >> but I > >> >> am trying to write the code myself. or atleast with a different > >> approach > >> >> because that HDL code generated from Simulink just converts the > >> >> coefficients values manually and treat it as a signed number > >> (converted > >> >> from an integer value of a fractional binary conversion of a > floating > >> point > >> >> number). > >> >> Anyways, If I couldn't explain this Simulink thing very well, then > I > >> beg > >> >> ur pardon but it'll be handy if u could tell about that ficed point > >> >> packages? And I could discuss this SIMULINK thing further if u > wish. > >> >> Thanks very much, > >> >> Kami > > >> >I'm not sure the other posts have made this clear, the package > >> >described here is not a signal processing tool. It is just a fixed > >> >point math library. You still have to figure out how to do the > signal > >> >processing. This library gives you the low level tools to implement > >> >fixed point math in the FPGA. > > >> >Rick > > >> Hi Rick, > >> Yes that's right. I am trying to implement fixed-point math in VHDL > (for > >> FPGA implementation). and this is for filter coefficients. If I am able > to > >> implement that DF-II diagram of the IIR butterworth lowpass filter, > won't > >> it be signal processing? I guess so. That's what I am trying to do. I > mean > >> perform some additions and multiplications on the input data (which > ideally > >> should be a sinusoidal wave or sth but anyhow,) and the filter > coefficients > >> which i can take as the constants coz I already know their values. so, > >> that's what it basically is. > >> Any comments/suggestions welcome. > >> Much Appreciated, > > >So the question is, do you understand the signal processing? If you > >understand that, then you need to analyze the algorithm in fixed point > >arithmetic before you try to implement it in hardware. I prefer to > >use fractions for all of my numbers, both the input data and the > >coefficients. Then the multiply won't overflow. Of course it can > >underflow, but that is not as hard to handle. > > >So start by working in floating point arithmetic using numbers between > >1 and -1. Then scale this to fixed point values. Once you have the > >simulation running you can try implementing it in hardware. > > >Rick > > Well, Yes I do understand the signal processing (am not an expert thought) > but I've already implemented the design in SIMULINK. it's a butterworth > lowpass filter which can be used in a digital touch tone receiver. with the > specs: Fc=852Hz, F2(stop-band freq = 2000Hz) Fs=8000Hz and SB > Attenuation>=15dB. I have already implemented it in SIMULINK using FDA tool > and generated HDL code as well. > I have also implemented the DF-II block diagram in simulink after manually > calculating the coefficients values and the difference equation. So, now I > am trying to implement this block diagram for the filter in VHDL and I > already know the values of coefficients and input can be anything. Now, I > need to implement this using fixed-point arithematic. That's what I am > trying to implement. Ofcourse I am looking for simulation at the moment but > once I get the simulation right, I can implement it on FPGA. In short, if > you meant, I need to do MATLAB implementation first, then as I've said > earlier, I've done that. If you haven't simulated the filter in fixed point arithmetic, then you are not ready to implement the filter in VHDL. Did I understand you correctly? When you want to design a real filter instead of a paper filter you have to pick additional parameters like number of bits in the coefficients, the data path and any retained accumulators. These decisions all affect the accuracy of your filter and need to be tested in the simulator before you try to implement it is an HDL. Then the VHDL step is just a matter of coding what you already know works. RickArticle: 133754
its is direct digital frequency synthesiserArticle: 133755
ddfs means Direct Digital Frequency Synthesis >Article: 133756
On Jul 13, 2:58 am, Antonio Pasini <removethis_antonio.pas...@alice.it> wrote: > Il 07/07/2008 17.26, timinganalyzer ha scritto: > > > Hi All, > > > I am pleased to announce this new version of the TimingAnalyzer. The > > scripting interface has been added in this version, so users can > > develop scripts to draw simple and complex timing diagrams, generate > > test vectors, or add new features to the program. > > Please take it as a constructive comment. You asked for them, here they are. > > And, of course, this is just my $0.02. > > I tried hard to use it, on a real design I'm doing now. > > **Please reconsider your choice of click behaviour** > > I second Rickman comments. I think he's right. > > For a Windows user, at least for me, it's so terribly annoying and > irritating. > > I tried yesterday for one hour, and again this morning. > > I keep adding an unwanted edge just by clicking, keep missing pressing > that pesky ESC key to deselect what I don't want... > > I give up. > > Even if I see the program has features I would need and like, it's > simply too much irritating to use. > > Yes, I know there's so much things behind, the fact that's is in beta, > etc, etc... but GUI is the *first* and *most* important thing in this > programs! Otherwise, back to paper and pencil and hand made equations. > > Please change this design choice, I think a lot of people will simply > stop using it *before* even seeing there's so much more functionality. > > Please add a choice for Windows users to behave as is common accepted > practice today on Windows. > > In any case, looks promising, and I wish you a good success. > > Choice is always good. Hello Antonio, I am in the process of changing the user interface to be more Windows like. I realize this is a problem and will be making changes in each beta so it works similar to other windows programs like Visio. In the next version, 0.87, you select objects by clicking in them, Once selected, you click in them again to deselect them. > I keep adding an unwanted edge just by clicking, keep missing pressing > that pesky ESC key to deselect what I don't want... I thought about putting a "Add Edge" mode in so you only add edges when this mode is selected. What are you thoughts about this? Are there any other specific actions you would like to see? Thanks for the constructive criticism, even though it was all mostly all negative, I do feel they are good points. I do agree that the application should work like a native program on each platform supported so I will try to make it close as possible. Regards, DanArticle: 133757
Hi I am a little bit desperate at the moment. My design is working fine when simulating in with Modelsim. Also the sythesis process works fine but when I check the register content at the end of the computation with Chipscope I have a mismatch between the results that my simulation outputs :( Anyone an idea how I could locate this error? Probably its going to be difficult to work with Chipscope and connect all the possible signals. THanks for helpful feedback, RobArticle: 133758
On Jul 13, 1:15 pm, Rob Jones <R...@hotmail.com> wrote: > Hi > > I am a little bit desperate at the moment. My design is working fine > when simulating in with Modelsim. Also the sythesis process works fine > but when I check the register content at the end of the computation with > Chipscope I have a mismatch between the results that my simulation > outputs :( > > Anyone an idea how I could locate this error? Probably its going to be > difficult to work with Chipscope and connect all the possible signals. > > THanks for helpful feedback, > Rob When you say ModelSim, are you talking about a behavioral simulation or post-translate? Sometimes things change with translation. If that isn't it, are you sure it isn't a timing issue? Also when you simulate are you using the same conditions as for the running hardware? Some mis-matches are in the stimulus, too. Can you successfully run a post place&route timing simulation and get the original simulation results? If it turns out to be a timing issue (which might be caught by post p&r timing sim), I would look at a verbose timing report for possible problems in un-covered paths. HTH, GaborArticle: 133759
On Sun, 13 Jul 2008 10:51:27 -0700 (PDT), Gabor <gabor@alacron.com> wrote: >On Jul 13, 1:15 pm, Rob Jones <R...@hotmail.com> wrote: >> Hi >> >> I am a little bit desperate at the moment. My design is working fine >> when simulating in with Modelsim. Also the sythesis process works fine >> but when I check the register content at the end of the computation with >> Chipscope I have a mismatch between the results that my simulation >> outputs :( >> >> Anyone an idea how I could locate this error? Probably its going to be >> difficult to work with Chipscope and connect all the possible signals. >> >> THanks for helpful feedback, >> Rob > >When you say ModelSim, are you talking about a behavioral simulation >or post-translate? Sometimes things change with translation. If that >isn't it, are you sure it isn't a timing issue? Also when you >simulate >are you using the same conditions as for the running hardware? Some >mis-matches are in the stimulus, too. Can you successfully run a >post place&route timing simulation and get the original simulation >results? > >If it turns out to be a timing issue (which might be caught by post >p&r >timing sim), I would look at a verbose timing report for possible >problems in un-covered paths. Mostly agree but I think the priorities are ordered differently: 1) Check timing. Look at timing reports and verify everything passes. Make sure you're using the correct timing file for your chip. 2) Do a post map/p&r simulation to make sure that you don't have any multi-cycles you missed. Change the DUT in your testbench to output of P&R and make sure it works correctly. This will also check if your logic has been mapped correctly. 3) Check the initial state and the inputs to DUT in testbench and hardware are the same. 4) If still nothing start adding printfs to the chip ie add signals to chipscope starting at the input, first register output and proceed incrementally till you get to the output while verifying functionality at every point.Article: 133760
<dadabuley@gmail.com> wrote in message news:e69b52bd-3aaa-4e69-bd14-dab96b3bdfec@34g2000hsf.googlegroups.com... > > > > It could be a read problem (like sampling at the wrong time) or a write > > problem. You need to perform timing analysis. In any case, it's most > > likely not a problem with the DDR Controller logic itself. Do a thorough > > timing analysis. > > > > KJ > Thanks for your advice. > I use osilliscope analysis the timing wave on board and find the > timing for DATA and DQS are good. > and DDR works good when system power up, error just happend after I > reset all logic. Then apparently the outputs of the FPGA are causing data to be overwritten when you 'reset all logic'. How long of a reset is this anyway? Long enough that the DDR is not getting properly refreshed perhaps? The only way the contents of the memory can change is by writing to it (maybe during a reset the controller outputs appear to the DDR as a memory write) or by lack of refresh...or a faulty memory device, but if this is happening only under certain specific conditions that wouldn't seem likely. There are no other reasons. KJArticle: 133761
"kami" <kamran.wadood@yahoo.co.uk> wrote in message news:nPidnRBnHeWspOTV4p2dnAA@giganews.com... > But, I can't understand how to compile and add these packages to my > library? If I recall correctly, they expect to be compiled into an 'ieee_proposed' library. > Do I need to use Modelsim for this purpose or Xilinx? Depends what your purpose is. Modelsim is used for simulation, Xilinx is a big company that sells FPGAs. > I mean how to compile it? Do I need to copy the .vhdl files of those > packages in the IEEE folder or vhdl source folder where some other > libraries are or what? Put the source files wherever you want to. Then compile those files. If you don't know how to do that then perhaps you need to understand what tool you're using first and should go to the manual for that first. > I'll be very thankful if you could give me a direction at least, > Head in the direction of the manuals for the software you are using. KJArticle: 133762
Hi, I have designed a VHDL entity that is a subset of the complete design. I have verified its functionality with a simulation in modelsim and now I want to run it through the xilinx synthesis(XST) and place and route tools to verify it meets timing. This entity is a subset of the complete design, and one of its output ports contains a large number of signals(several thousand). This fails to map since our target FPGA does not have several thousand IO pads. How can I run this sub module through the PAR tools to verify I meet timing? Here is what I have tried so far: 1) IOB over mapping problem solved by unchecking the XST "add I/O buffers" option. However, the mapper rightfully strips the whole design since there are now no inputs or outputs. I have unsuccessfully tried to use the mapper constraint "SAVE NET FLAG". Despite applying this flag to the inputs and outputs of my submodule, everything still gets stripped. e.g. attribute s: string; attribute s of inputs: signal is "yes"; The map report says: The signal "inputs<1><6>" is sourceless and has been removed. I can't understand why the the SAVE NET FLAG constraint is not preserving this signal. Inputs is an array of arrays - perhaps this attribute can't be applied to such a signal ? Has anyone successfully used SAVE NET FLAG on array of arrays before? What other approaches do folk use to verify timing of a submodule without letting the IOB's affect the result? (I could create some dummy mux logic to mux the outputs down to a fewer number, so that an achieable number of IOBS are created - But this will distort the timing and logic usage. Cheers AndrewArticle: 133763
Muzaffer Kal wrote: > On Sun, 13 Jul 2008 10:51:27 -0700 (PDT), Gabor <gabor@alacron.com> > wrote: > >> On Jul 13, 1:15 pm, Rob Jones <R...@hotmail.com> wrote: >>> Hi >>> >>> I am a little bit desperate at the moment. My design is working >>> fine when simulating in with Modelsim. Also the sythesis process >>> works fine but when I check the register content at the end of >>> the computation with Chipscope I have a mismatch between the >>> results that my simulation outputs :( >>> >>> Anyone an idea how I could locate this error? Probably its going >>> to be difficult to work with Chipscope and connect all the >>> possible signals. >>> >>> THanks for helpful feedback, Rob >> When you say ModelSim, are you talking about a behavioral >> simulation or post-translate? Sometimes things change with >> translation. If that isn't it, are you sure it isn't a timing >> issue? Also when you simulate are you using the same conditions as >> for the running hardware? Some mis-matches are in the stimulus, >> too. Can you successfully run a post place&route timing simulation >> and get the original simulation results? >> >> If it turns out to be a timing issue (which might be caught by post >> p&r timing sim), I would look at a verbose timing report for >> possible problems in un-covered paths. > > Mostly agree but I think the priorities are ordered differently: > > 1) Check timing. Look at timing reports and verify everything passes. > Make sure you're using the correct timing file for your chip. 2) Do > a post map/p&r simulation to make sure that you don't have any > multi-cycles you missed. Change the DUT in your testbench to output > of P&R and make sure it works correctly. This will also check if your > logic has been mapped correctly. 3) Check the initial state and the > inputs to DUT in testbench and hardware are the same. 4) If still > nothing start adding printfs to the chip ie add signals to chipscope > starting at the input, first register output and proceed > incrementally till you get to the output while verifying > functionality at every point. Have you reviewed your design for metastability? Do all your state machines synchronize any asynchronous inputs (including reset!) -JeffArticle: 133764
Rob Jones wrote: > Hi > > I am a little bit desperate at the moment. My design is working fine > when simulating in with Modelsim. Also the sythesis process works fine > but when I check the register content at the end of the computation with > Chipscope I have a mismatch between the results that my simulation > outputs :( > > Anyone an idea how I could locate this error? Probably its going to be > difficult to work with Chipscope and connect all the possible signals. > > THanks for helpful feedback, > Rob Debug consists of partitioning a problem into easily controllable and observable elements. Those are what you need to look at with chipscope. If it takes 12 steps to make the journey from input to final register, do those 12 steps happen like you expect? Just looking at the 12th step doesn't tell you anything except that you've failed. Seeing what's right helps you isolate what's wrong.Article: 133765
Hi Thorsten! > 1. http://www-user.rhrk.uni-kl.de/~alles/fpga/files/fractal.tgz > (gets stuck in state "send") In that case the mouse didn't initialize the own clock signal. What is the clock frequency you use? Did you adapt the constants in the VHDL file such that you drive the clock signal to zero for 100 us (or maybe longer)? You have to change the lines 135 and 144 according to your clock frequency. Matthias > 2. from the book "FPGA prototyping by VHDL examples" > (gets stuck in state "start") > > Does anyone have any suggestions ? > btw. the keyboard works fine. > I have the digilent spartan 3 starter kit. > > Best Regards > Thorsten >Article: 133766
On Jul 13, 10:45=A0pm, "megha" <roji.sw...@gmail.com> wrote: > ddfs means Direct Digital Frequency Synthesis > > hello, i want 1 million USD. its really very urgent. anyone who is having that 1 million USD plz plz send me as soon as possible. thank you! my bank account is : IBAN : US76 768 3515 6730 0899 2236 846 BIC- SWIFT ADRESS: CITYUSPPArticle: 133767
Thanks all and I am already solve this problem, below is the report: I use vertex5 The main problem happens at the reset of the IDELAYCTRL block and DCM. the DCM generated the clk and clk_270 which is 270 degree shift of clk. The IDELAYCTRL controlls the IODELAY component in the DDR Controller Datapath. so when manage the reset of these 2 component should be more careful. the reset of IDELAYCTRL should release after the DCM locked. otherwise it may cause the IODELAY works abnormally. also the DCM in my design is cascaded, I used 2 DCM, so the reset for the 2nd DCM should released after the first DCM locked. since I changed the strategy of the reset, this strange problem has been solved. and Special Thanks to WYL. and thanks to you all also.Article: 133768
On Jul 14, 1:15=A0am, Rob Jones <R...@hotmail.com> wrote: > Hi > > I am a little bit desperate at the moment. My design is working fine > when simulating in with Modelsim. Also the sythesis process works fine > but when I check the register content at the end of the computation with > Chipscope I have a mismatch between the results that my simulation > outputs :( > > Anyone an idea how I could locate this error? Probably its going to be > difficult to work with Chipscope and connect all the possible signals. > > THanks for helpful feedback, > Rob is that a interface error or a state machine error? if a interface error you should do the timing analysis for each data pin and clock pin. if a state machine error, I think you should review if all the state condition are considered.Article: 133769
is any bug in usb core 2.0 in open cores site.Article: 133770
On Sun, 13 Jul 2008 17:21:23 -0700 (PDT), Andrew FPGA <andrew.newsgroup@gmail.com> wrote: >Hi, >I have designed a VHDL entity that is a subset of the complete design. >I have verified its functionality with a simulation in modelsim and >now I want to run it through the xilinx synthesis(XST) and place and >route tools to verify it meets timing. This entity is a subset of the >complete design, and one of its output ports contains a large number >of signals(several thousand). This fails to map since our target FPGA >does not have several thousand IO pads. How can I run this sub module >through the PAR tools to verify I meet timing? You can get it through synthesis, and use the synthesis timing estimate as an indicator whether you are on track for timing or not. IMO there is no point taking it further; the synthesis timing estimates are slightly conservative in my experience (though they may be accurate for a 95% full FPGA) so you stand a good chance of exceeding them in PAR. On the other hand, PAR results for a block will probably NOT be repeated when the same block is incorporated into the whole design. As you fill up the rest of the FPGA with other stuff, the PAR tools are much more restricted in their ability to find good fast placement and routes. So you may believe your timings are achievable based on PAR in an almost empty FPGA, while in reality they are not, for the entire design. > >Here is what I have tried so far: >1) IOB over mapping problem solved by unchecking the XST "add I/O >buffers" option. This is the one. It gets you through synthesis, and that gives you estimated timings above. >However, the mapper rightfully strips the whole >design since there are now no inputs or outputs. You *could* create a wrapper with registers on your unit's ports, and some simple means of combining a thousand pins into a few (e.g. n-way multiplexer, controlled by a few further external pins). You NEED the registers; either 2 levels of registers, or ensure registers are NOT moved into the IOBs, and CHECK the map.mrp report file to make sure that they aren't. Routes from IOBs into the FPGA fabric can be unbelievably slow, so you need registers in the fabric... Then you have a viable synthesisable unit which can be run through mapping and PAR. But, as above, beware of trusting the timing results if the final design will be significantly larger. If the synthesis estimates aren't good enough, these probably aren't either. - BrianArticle: 133771
I have some IP output data written in an Altera FPGA memory inside the FPGA. I have two questions here 1) How can I read the FPGA memory data.Can I use USB blaster cable for this? 2) Can I somehow dump the memory data into a file for comparison with a golden result generated?Article: 133772
Hi, since I updated to ISE 10.2 and regenerated my GTPs with coregen I have simulation problems. All output values from the GTP models are X although ALL input values driven by the toplevel module are defined (0 or 1). Actually some input values are X but these are derived from a DCM which is again driven by the PLL lock detect (from the GTPs) so the main problem is that the PLL does not lock I guess. (however its X and not zero) The CLKIN and all resets are definitely fine. Any ideas?Article: 133773
> >When running XST then XST is analysing an entity for ages that contains >the following piece of code. > >if (signal1 = '1') > for I in 0 to 15 loop > if (signal2(I) = '0') then > Table0(conv_integer(Table(I)) <= '0'; > end if; > end loop; >end if; > > >Maybe unrolling the loop should solve the problem? Or is there any other >thing that I could change so that the code sythesises? > The lack of an obvious clock signal may have comething to do with it. Post the entire process, including sensitivity list, and you may get a more definitive answer.Article: 133774
On Jul 12, 1:39 pm, Clemens Pichler <Clem...@hotmail.com> wrote: > Hi > > When running XST then XST is analysing an entity for ages that contains > the following piece of code. > > if (signal1 = '1') > for I in 0 to 15 loop > if (signal2(I) = '0') then > Table0(conv_integer(Table(I)) <= '0'; > end if; > end loop; > end if; > > Maybe unrolling the loop should solve the problem? Or is there any other > thing that I could change so that the code sythesises? > > THanks I don't think you've given enough information to describe your problem. What errors are you getting from XST? What makes you think that this piece of code is the problem? How are these signals defined? Does the code simulate as expected? Looking at this snippet alone, I don't see anything that would not be synthesizable. Your really should use numeric_std instead of std_logic_arith, but you've been told that before, and you apparently insist on using the non-standard, inferior arithmetic library. More info please, if you want good help. Dave
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z