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On Wed, 09 Jul 2008 23:06:52 -0700, Muzaffer Kal <kal@dspia.com>
wrote:
>Hi everyone,
>I'm supposed to implement a serializer where the parallel data and
>clock arrive from outside the chip and I have an 8x internal clock
>which is frequency locked to the incoming clock but the phase
>relationship between internal fast clock and external slow clock is
>unknown
Thanks for giving me the excuse to tidy up this thing, which I've
used in similar situations. Its latency is approximately half
a cycle of the source domain clock, which should be OK.
It absolutely assumes that the phase offset between source
clock and destination 8x-oversampling clock is fixed, but makes
no assumptions about the value of that phase offset. It should
tolerate phase jitter of about +/- a quarter-cycle of the source
clock.
You can think of it as a 2-deep FIFO whose read and write
pointers stay in lockstep, or a ping-pong buffer.
Either way, it works for me.
~~~~~~~~~~~~~~~~~~~~~~~~ begin code ~~~~~~~~~~~~~~~~~~~~~
module isochronous_x8 (
// resynchronizes between a source clock and
// a destination clock that is known to be running
// at exactly 8x the source frequency, with an
// unknown but fixed phase offset
// INITIALISATION
input asynch_init,
// SOURCE DOMAIN
input source_clock,
input [7:0] source_data,
// DESTINATION DOMAIN
input dest_x8_clock,
output reg [7:0] dest_data,
output reg dest_strobe,
output reg locked
);
reg wrA; // Chooses which buffer slot to write
reg [7:0] d0; // buffer slots
reg [7:0] d1;
// Source domain logic:
// write into the two buffer slots alternately
//
always @(posedge source_clock or posedge asynch_init)
if (asynch_init) begin
wrA <= 0;
d0 <= 0;
d1 <= 0;
end else begin
if (wrA)
d1 <= source_data;
else
d0 <= source_data;
wrA <= ~wrA;
end
// Destination domain logic:
// oversample the wrA signal to locate source phase.
// Once we've located the first rising edge of wrA,
// corresponding to the first data value after reset,
// raise the "locked" signal and synch-up the clock
// divider counter "div8". Thenceforward, assume
// the phase of the two clocks is fixed. Tolerate
// about 1/4 cycle jitter in source clock. If jitter
// goes outside that limit, drop the "locked" signal
// and re-synch.
//
always @(posedge dest_x8_clock or posedge asynch_init)
begin: dest_domain
reg [7:0] oversample;
reg [2:0] div8;
if (asynch_init) begin
locked <= 0;
div8 <= 0;
oversample <= 0;
dest_strobe <= 0;
dest_data <= 0;
end else begin
// shift into the oversample register
oversample <= {oversample[6:0], wrA};
div8 <= div8 + 1;
// by default, no output
dest_strobe <= 0;
if (locked && (div8 == 0)) begin
// This should be the right moment to sample.
// Check that the wrA signal transitioned at
// an appropriate time:
casez (oversample)
8'b00????11:
begin
dest_strobe <= 1;
dest_data <= d0;
end
8'b11????00:
begin
dest_strobe <= 1;
dest_data <= d1;
end
default:
// Sampling has slipped too far
locked <= 0;
endcase
end else if (!locked) begin
// Seek
if (
(oversample[7:5] == 3'b000)
&& (oversample[2:0] == 3'b111)
) begin
locked <= 1;
div8 <= 0;
end
end // if (locked ...)
end // if (asynch_init)...else...
end // dest_domain
endmodule
~~~~~~~~~~~~~~~~~~~~~~~~~ end code ~~~~~~~~~~~~~~~~~~~~~~
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 133701Hi all, I'm working on dynamic partial reconfiguration on a virtex 4 (sx35) fpga. I would to use hwicap to make internal reconfiguration. Do you know if a bus macro with enable signal is necessary? Does partial reconf wok well also using a normal bus macro? Thanks for your help. PaoloArticle: 133702
On Jul 10, 5:39 am, "Symon" <symon_bre...@hotmail.com> wrote: > "Frank Buss" <f...@frank-buss.de> wrote in message > > news:lwpnm8xptojr$.5dpw9umuf1k2$.dlg@40tude.net... > > > He asked for putting the output into the > > memory, only. Looks like he don't want to read it back :-) > > In which case he needs one of these:-http://academics.vmi.edu/ee_js/Research/IC_Datasheets/digital_cmos/Wr... Symon, Thank you so much for that link. I saw this datasheet back in the 1970's with much amusement. I especially liked the filament voltage supply and cooling requirements. This one's going up on my wall :-) Regards, GaborArticle: 133703
Yes, how many times I don't write here, maybe about 6 years, from my thesis on a qpsk modulator on a Virtex 1000, I don't know if they still write here but in the case my greetings to Ray Andraka and Brian Philosky that helps me during that job. In Italy there wasn't and there isn't so much opportunity to work on fpga so actually my job is different, but I'm trying to renew my experience on fpga so last week I buy a Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK from Silica for about 235euro. But I've not the cable to program it, so I ask to Silica that suggest me the http://www.xilinx.com/products/devkits/HW-USB-G.htm for 140 euros but my budget for personal training is ended, can you suggest me some cheaper solution to program that board ?? Many Thanks Antonio D'Ottavio www.etantonio,itArticle: 133704
"Symon" <symon_brewer@hotmail.com> wrote in message news:g54ld3$mm3$1@aioe.org... > > "Frank Buss" <fb@frank-buss.de> wrote in message > news:lwpnm8xptojr$.5dpw9umuf1k2$.dlg@40tude.net... >> >> He asked for putting the output into the >> memory, only. Looks like he don't want to read it back :-) >> > In which case he needs one of these:- > http://academics.vmi.edu/ee_js/Research/IC_Datasheets/digital_cmos/Write%20Only%20Memory.pdf Please can supply simulation model if haves?Article: 133705
Antonio, Not supported by Xilinx software (you must use the Digilent drivers): http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Cables&Cat=Cable See the programming cables at the middle of the page. You need to create the files, then leave ISE, enter the Digilent programming utility, and then download the file. Austin etantonio wrote: > Yes, > how many times I don't write here, > maybe about 6 years, from my thesis on a qpsk modulator on a Virtex > 1000, > I don't know if they still write here but in the case my greetings to > Ray Andraka and Brian Philosky that helps me > during that job. > In Italy there wasn't and there isn't so much opportunity to work on > fpga so actually my job is different, > but I'm trying to renew my experience on fpga so last week I buy a > Spartan 3AN DSP development board > AES-SPEEDWAY-S3ADSP-SK from Silica for about 235euro. > But I've not the cable to program it, so I ask to Silica that suggest > me the > http://www.xilinx.com/products/devkits/HW-USB-G.htm > for 140 euros but my budget for personal training is ended, can you > suggest me some cheaper solution to program that board ?? > Many Thanks > > Antonio D'Ottavio > www.etantonio,itArticle: 133706
Hi I have a bit a problem, I would like to capture the status of 16 registers in my architecture each of them 32 bits long. However, if I try to integrate an Logic Analyzer the maximum datapath that I could use is 256 bits. In my case, I would need 512 bits of data to be transfered between the FPGA and host computer via ILA. Has anyone an idea how I could overcome this limitation so that I could read out the whole information? Many thanksArticle: 133707
MikeWhy wrote: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:g54ld3$mm3$1@aioe.org... >> In which case he needs one of these:- >> http://academics.vmi.edu/ee_js/Research/IC_Datasheets/digital_cmos/Write%20Only%20Memory.pdf > > Please can supply simulation model if haves? Writing a physical correct simulation model for the faucet, which you can see in the block diagram, would be really difficult in VHDL, but I guess the code below is a fairly good approximation. You can specify the size of the memory by specifying the address_width parameter when instantiating the entity and with data_width you can specify the number of bits per element. Default is a memory of 4294967296 bytes. When synthesizing, it has an exceptional low LE count, works with very fast clocks and last but not least: This works for both, as simulation model and with real FPGAs! entity WriteOnlyMemory is generic ( address_width: integer := 32; data_width: integer := 8 ); type address_type is unsigned(address_width - 1 downto 0); type data_type is unsigned(data_width - 1 downto 0); port( address: in address_type; data: in data_type; clock: in std_logic; write_enable: in std_logic ); end entity WriteOnlyMemory; architecture rtl of WriteOnlyMemory is begin signal the_storage: data_type; write_process: process(clock) variable temp: data_type begin if rising_edge(clock) then if write_enable = '1' then temp := 0; for i in 0 to address loop temp := temp xor data; end loop; end if; the_storage <= temp; end if; end process; end architecture rtl; -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 133708
Clemens wrote: > Hi > > I have a bit a problem, I would like to capture the status of 16 > registers in my architecture each of them 32 bits long. However, > if I try to integrate an Logic Analyzer the maximum datapath that I > could use is 256 bits. In my case, I would need 512 bits of data to be > transfered between the FPGA and host computer via ILA. Has anyone an > idea how I could overcome this limitation so that I could read out the > whole information? > > Many thanks I believe you can insert multiple ILA cores, so maybe you can workaround the datapath limitation this way. -KevinArticle: 133709
Clemens wrote: > Hi > > I have a bit a problem, I would like to capture the status of 16 > registers in my architecture each of them 32 bits long. However, > if I try to integrate an Logic Analyzer the maximum datapath that I > could use is 256 bits. In my case, I would need 512 bits of data to be > transfered between the FPGA and host computer via ILA. Has anyone an > idea how I could overcome this limitation so that I could read out the > whole information? > > Many thanks Another possibility might be to use double data rate. So build a custom core of 256 DDR registers and connect your 512 samples with them. Connect Chipscope with your 256 register, let Chipscope run at twice the clock frequency (and single data rate) you use for your device under test and now you get 2 sets of 256 samples with chipscope. Regards, LorenzArticle: 133710
Hi everyone, I am a begginer with microblaze, and I am trying to do some practice code in a Spartan3 Development Boards. I want to program a counter with the opb_timer and print the counter every 0.5 seconds in the RS232 out interface. I dont have enough experience programming the timer driver in generate mode. I would like to know if I need to initialize the timer if I include #"xtmrctr_l.h" instead of #"xtmrctr.h". And what functions do I need to use to start and pause the timer. Thnx AlfredArticle: 133711
Thanks for your inputs guys, but the thing is that I get now from XST the following error NUmber of bounded IOBs 484 out of 248 195% (OVERMAPPED) So it seems that the FPGA just allows me to have a a certain number if input/output information and I cant really read out all the information in the registers...Article: 133712
On Jul 10, 12:10=A0am, colin <colin_toog...@yahoo.com> wrote: > You don't need to find out the IR length. What your trying to do is > called "blind interrogation" in the JTAG spec. As you clock into Test > logic Reset all devices enter manufacturers ID mode if it is > implemented and bypass if it isn't. A device will shift out a 1 on the > first edge of the clock if it is shifting out its ID and will shift > out a 0 if it is in bypass. It is then straightforward to work out > what devices are in your chain. > > High end JTAG test software that does interconnect testing (which is > what JTAG was originally for) does not trust the information given in > the bsdl files untill they check the manufacturers ID and then the IR > & DR lengths on pretty much every test they carry out. > > Colin Thanks for all the replies. I'll check into the BSDL files stuff. slideArticle: 133713
> On Wed, 09 Jul 2008 Muzaffer Kal <kal@dspia.com> wrote:
>> I'm supposed to implement a serializer where the parallel data and
>> clock arrive from outside the chip and I have an 8x internal clock
>> which is frequency locked to the incoming clock but the phase
>> relationship between internal fast clock and external slow clock is
>> unknown
Muzaffer, it looks like you asked exactly
the right question at the right time ;)
Jonathan Bromley wrote:
> Thanks for giving me the excuse to tidy up this thing, which I've
> used in similar situations. Its latency is approximately half
> a cycle of the source domain clock, which should be OK.
A very clever and complete verilog tutorial,
and the rtl viewer does a good job with it.
I often find it easier to write code than read it,
but this an uncommon exception.
It did 292 MHz on the 8x clk on a stratix2
without touching a thing.
Thanks for taking the time to post it.
-- Mike Treseler
Article: 133714Hi All, How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage xilinx fpga tool it self will recognize and through as warning or error. At what stage in the asic flow this multicycle path and False path are identified. How to fix this Multi cycle path and false path in the fpga flow How it is going to effect the Timing Closure and the Slack of the design. regards kilArticle: 133715
On Thu, 10 Jul 2008 11:21:20 +0100, Jonathan Bromley wrote:
[...]
>You can think of it as a 2-deep FIFO whose read and write
>pointers stay in lockstep, or a ping-pong buffer.
>Either way, it works for me.
AAAAAARGHHH.
Rule #1 of Usenet: Errors will be detected 30 seconds
after hitting send.
The code I provided was adapted from something else
and, although it works correctly, it has a lot of
redundant logic. There is no need for the two
ping-pong buffers; a single buffer is enough.
The double buffer trick was used in a system where
I didn't have the luxury of oversampling.
Here's a corrected version, and a testbench.
The logic's simpler, so it should please Mike by
going even faster :-)
Apologies.
~~~~~~~~~~~~~~~~~~~~ begin device code ~~~~~~~~~~~~~~~~~
module mesochronous_x8 (
// resynchronizes between a source clock and
// a destination clock that is known to be running
// at exactly 8x the source frequency, with an
// unknown but fixed phase offset
// INITIALISATION
input asynch_init,
// SOURCE DOMAIN
input source_clock,
input [7:0] source_data,
// DESTINATION DOMAIN
input dest_x8_clock,
output reg [7:0] dest_data,
output reg dest_strobe,
output reg locked
);
reg c2; // Divide clock by 2
reg [7:0] d; // buffer
// Source domain logic:
// write into the two buffer slots alternately
//
always @(posedge source_clock or posedge asynch_init)
if (asynch_init) begin
c2 <= 0;
d <= 0;
end else begin
c2 <= ~c2;
d <= source_data;
end
// Destination domain logic:
// oversample the c2 signal to locate source phase.
// Once we've located the first rising edge of c2,
// corresponding to the first data value after reset,
// raise the "locked" signal and synch-up the clock
// divider counter "div8". Thenceforward, assume
// the phase of the two clocks is fixed. Tolerate
// about 1/4 cycle jitter in source clock. If jitter
// goes outside that limit, drop the "locked" signal
// and re-synch.
//
always @(posedge dest_x8_clock or posedge asynch_init)
begin: dest_domain
reg [7:0] oversample;
reg [2:0] div8;
if (asynch_init) begin
locked <= 0;
div8 <= 0;
oversample <= 0;
dest_strobe <= 0;
dest_data <= 0;
end else begin
// shift into the oversample register
oversample <= {oversample[6:0], c2};
div8 <= div8 + 1;
// by default, no output
dest_strobe <= 0;
if (locked && (div8 == 0)) begin
// This should be the right moment to sample.
// Check that the c2 signal transitioned at
// an appropriate time:
casez (oversample)
8'b00????11,
8'b11????00:
begin
dest_strobe <= 1;
dest_data <= d;
end
default:
// Sampling has slipped too far
locked <= 0;
endcase
end else if (!locked) begin
// Seek
casez (oversample)
8'b000zz111,
8'b111zz000:
begin
locked <= 1;
div8 <= 0;
end
endcase
end // if (locked ...)
end // if (asynch_init)...else...
end // dest_domain
endmodule
~~~~~~~~~~~~~~~~~~~ begin testbench code ~~~~~~~~~~~~~~~~
module meso_tb;
// DUT connections
//
reg asynch_init;
reg source_clock;
reg [7:0] source_data;
reg dest_x8_clock;
wire [7:0] dest_data;
wire dest_strobe;
wire locked;
// DUT instance
//
mesochronous_x8 dut(
asynch_init,
source_clock,
source_data,
dest_x8_clock,
dest_data,
dest_strobe,
locked
);
// Testbench internal signals
//
reg run;
reg virtual_source_clock;
// Reset generator
//
initial begin
asynch_init = 1;
@(posedge source_clock)
@(negedge dest_x8_clock)
asynch_init = 0;
end
// Generate x8 destination clock, and an idealised
// version of source clock that runs at exactly
// one-eighth of the destination clock frequency
//
initial begin: dest
dest_x8_clock = 0;
virtual_source_clock = 0;
forever wait (run)
while (run) begin
repeat (8)
#5 dest_x8_clock = ~dest_x8_clock;
virtual_source_clock = ~virtual_source_clock;
end
end
// Generate the source clock by skewing the idealised
// clock by a variable amount
//
initial begin: source_clock_gen
time skew;
source_clock = 0;
forever @(virtual_source_clock)
source_clock <= #(skew) virtual_source_clock;
end
// Generate incrementing data on the source
//
initial begin : source_data_gen
source_data = 0;
forever @(negedge source_clock)
source_data = source_data + 1;
end
// Testbench control: vary the source clock skew
// over time, so that in the first part of the test
// the source clock runs slightly slow and in the
// second part of the test it runs slightly fast
//
initial begin : testcase
source_clock_gen.skew = 0;
run = 1;
repeat (300) @(posedge dest_x8_clock)
source_clock_gen.skew = source_clock_gen.skew+1;
repeat (300) @(posedge dest_x8_clock)
source_clock_gen.skew = source_clock_gen.skew-1;
run = 0;
end
endmodule
~~~~~~~~~~~~~~~~~~~~~~~~~ end code ~~~~~~~~~~~~~~~~~~~~~~
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 133716<ekavirsrikanth@gmail.com> wrote in message news:51facbfd-43fa-4247-810e-51c7d658ec5b@c65g2000hsa.googlegroups.com... > > Hi All, > > How to identify the Multi cycle path and the False path in the design. > do we need to identify after the Synthesis stage xilinx fpga tool it > self will recognize and through as warning or error. > If this is a medium/high budget project I would speak to the Fishtail (http://www.fishtail-da.com/) guys. Their Focus product will automatically find most(all?) MCP/FP in your design and output the result to a constraints file. I believe both Precision/Synplicity are supported. This is a great product but as I mentioned mostly for the big guys. If you have to do this manually then start by looking at the most negative slack path and simply plough through the code/schematics to see if that path is false/multicycle or not. It is not going to be easy or quick especially for false path. If you have access to a formal tool or PSL/SVA support for your simulator then you might be able to write a property to check that, for example, and enable pin on the output of a long combinatorial path FF is always stable for more than 1 clockcycle. Hans. www.ht-lab.com > At what stage in the asic flow this multicycle path and False path are > identified. How to fix this Multi cycle path and false path in the > fpga flow > > How it is going to effect the Timing Closure and the Slack of the > design. > > > regards > kilArticle: 133717
Clemens wrote: > Thanks for your inputs guys, but the thing is that I get now from XST > the following error > > NUmber of bounded IOBs 484 out of 248 195% (OVERMAPPED) > > So it seems that the FPGA just allows me to have a a certain number if > input/output information and I cant really read out all the information > in the registers... That error sounds to me to be about external IOs not about FPGA internal connections. So You do use 484 external Ports within Your toplevel file and do only have something like 248 Pins available? Maybe you should consider multiplexing Your IOs within some wrapper or fully connect Your design to Your module under test. That is not a chipscope limitation. That is a limitation caused by Your design. Regards, LorenzArticle: 133718
"vignesh_karthi" <pvprabhuraj@gmail.com> wrote in message news:ecf5b59d-ba57-4c5f-9b30-93f0ff38e2f6@59g2000hsb.googlegroups.com... > My name is vignesh. > > I am also new guy to Xilinx .. i want to know the following things... > please help me... > > 1. how can i create the *.ucf file using xilinx Tool ? (if you have > provide me ) > > 2. how can i avoid the multicycle path and false path ? (if you have > provide me ) > > 3. Do you have any basic user manual for xilinx tool ? (if you have > provide me ) > > > Advanced Thanks to you... Hi Vignesh, Since you are just getting started, the videos at http://www.burched.com/freevideos.ag.php may help you. Many basic questions are covered. My "Single Top FPGA Tips" might also be helpful http://www.burched.com/fpgatoptips11.pdf Best regards, Tony BurchArticle: 133719
Jonathan Bromley wrote:
> AAAAAARGHHH.
>
> Rule #1 of Usenet: Errors will be detected 30 seconds
> after hitting send.
But knowing Rule #1 does not affect the applicability of Rule #1.
There is no other path to enlightenment :)
> The code I provided was adapted from something else
> and, although it works correctly, it has a lot of
> redundant logic. There is no need for the two
> ping-pong buffers; a single buffer is enough.
> The double buffer trick was used in a system where
> I didn't have the luxury of oversampling.
Thanks, I'll hang on to both.
> Here's a corrected version, and a testbench.
Which completes the verilog tutorial. Thanks.
> The logic's simpler, so it should please Mike by
> going even faster :-)
Very nice. 490.44 MHz 9 luts, 30 regs.
-- Mike Treseler
Article: 133720>On Jun 18, 8:09=A0am, faza <fazulu.v...@gmail.com> wrote: >> Hai, >> >> I want to know which is the right way of implementing and usage of >> fixed point number data types in hardware(industry standard)..I have >> referred various FIR >> implementations where they are mostly handling filter coefficients as >> integer(truncating from fixed or floating point using MATLAB) or >> binary.Is it difficult to handle and implement real(fraction) numbers >> i.e.,filter >> coefficients values directly in the hardware? >> > >Google for fixed point VHDL to_ufixed and you'll get the code for the >standard (or soon to be a standard) VHDL fixed point package. > >http://www.google.com/search?source=3Dig&hl=3Den&rlz=3D1G1GGLQ_ENUS278&q=3D= >fixed+point+VHDL+to_ufixed > >Kevin Jennings > Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I have found these packages you mentioned in response to this guy's question, very good. But I don't exactly understand how to use these packages? Any other comments welcome. I am designing a butterworth lowpass filter (atm just 2nd order filter). I have implemented it in simulink and could generate VHDL code as well but I am trying to write the code myself. or atleast with a different approach because that HDL code generated from Simulink just converts the coefficients values manually and treat it as a signed number (converted from an integer value of a fractional binary conversion of a floating point number). Anyways, If I couldn't explain this Simulink thing very well, then I beg ur pardon but it'll be handy if u could tell about that ficed point packages? And I could discuss this SIMULINK thing further if u wish. Thanks very much, KamiArticle: 133721
hello, i want a simple VHDL code for DDFS. its really very urgent. anyone who is having that VHDL code plz plz send me as soon as possible. thank you! my email address is roji.sweet@gmail.comArticle: 133722
On Jul 9, 8:41 pm, LittleAlex <alex.lo...@email.com> wrote: > On Jul 9, 10:49 am, Matt <metal...@gmail.com> wrote: > > > > > On Jul 9, 1:03 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > On Jul 9, 9:44 am, Matt <metal...@gmail.com> wrote: > > > > > Ive seen posts on this error in VHDL a few times around here, but I am > > > > still unsure how to get rid of this error so my nets don't get > > > > removed. Here is the code that is causing the error: > > > > > library ieee; > > > > use ieee.std_logic_1164.all; > > > > use ieee.std_logic_arith.all; > > > > use ieee.std_logic_unsigned.all; > > > > > entity BLINK is > > > > > PORT( SA: IN STD_LOGIC_VECTOR (19 downto 0); --Offending > > > > input vector > > > > pin2: OUT STD_LOGIC := '0'; > > > > clk: IN STD_LOGIC); > > > > > end BLINK; > > > > > architecture FLASH of BLINK is > > > > > CONSTANT count: INTEGER:=8330000; > > > > SIGNAL t: INTEGER:= 0; > > > > SIGNAL sig: STD_LOGIC:='0'; > > > > SIGNAL state: STD_LOGIC; > > > > CONSTANT address: STD_LOGIC_VECTOR (19 downto 0) := X"002E8"; > > > > SIGNAL BASEADDRESS: STD_LOGIC_VECTOR (19 downto 0); > > > > SIGNAL ADD: STD_LOGIC_VECTOR (2 downto 0); > > > > > begin > > > > > PROCESS (clk, SA) --SA is placed in > > > > sensitivity list > > > > begin > > > > > BASEADDRESS<=SA AND "11111111111111111000"; --SA is > > > > used to derive a value for a signal > > > > ADD<=SA (2 downto > > > > 0); --SA > > > > is used to derive a value for a signal > > > > > IF(BASEADDRESS=address) THEN > > > > > . > > > > . > > > > . > > > > > I get the error that SA_0 through SA_19 has no load. As you can see, I > > > > use the SA vector. I have even tried placing it in the sensitivity > > > > list, but I still get the 'has no load' error and the net continues to > > > > get removed after synthesis. How do I go about either giving this > > > > vector a dummy load or ignoring the warnings and keeping the net in my > > > > design? > > > > > Thanks in advance. > > > > The signals BASEADDRESS and ADD are not used, so any assignment to > > > them is being optimized away. Then you are left with input signals > > > that do nothing, and that's where the warning message is coming from. > > > Connect those signals to something, and the logic won't be optimized > > > away. > > > > As is is, you have one output, and it is forced to '0', so I would be > > > surprized if there was _any_ logic left. > > > Isn't BASEADDRESS being used in the IF statement? > > > IF(BASEADDRESS=address) THEN > > > also, ADD is used in a similar switch case later in the code, I > > removed it just to keep it short. > > > Thanks, > > Matt > > BASEADDRESS is used in the IF statement, but it doesn't actually "do" > anything. If it's equal to something, ADD gets set, but ADD isn't > used for anything, so that assignment is a "don't care", so the > comparison doesn't matter, so ... Thanks for the replies. By adding: ADD<=SA (2 downto 0); the errors went away. Is there away to keep the SA net with out actually loading it with something? Thanks again, MattArticle: 133723
megha a écrit : > hello, i want a simple VHDL code for DDFS. its really very urgent. anyone > who is having that VHDL code plz plz send me as soon as possible. > thank you! > my email address is roji.sweet@gmail.com Please define DDFS as accurately as possible Nicolas From me@home.org Fri Jul 11 12:25:30 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!goblin2!goblin.stu.neva.ru!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <4877c1ba$0$25950$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <me@home.org> Subject: ps2 mouse initialization fails Newsgroups: comp.arch.fpga Date: Fri, 11 Jul 2008 21:25:30 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 16 Organization: CNNTP NNTP-Posting-Host: 15dbb480.read.cnntp.org X-Trace: DXC==DBA1AWQch3W411>X6hFR;WoT\PAgXa?1A?mbOAB4R05CWCf629N194hldKiGb`JF=7I5\[g:cU[?\8?:iBZH4[> X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:146353 X-Received-Date: Fri, 11 Jul 2008 16:25:33 EDT (flpi142.ffdc.sbc.com) Hi, I tried out 2 mouse modules. Both get stuck in the mouse initialization process. The mouse does not respond. The modules i tried out are : 1. http://www-user.rhrk.uni-kl.de/~alles/fpga/files/fractal.tgz (gets stuck in state "send") 2. from the book "FPGA prototyping by VHDL examples" (gets stuck in state "start") Does anyone have any suggestions ? btw. the keyboard works fine. I have the digilent spartan 3 starter kit. Best Regards ThorstenArticle: 133724
On Jul 11, 2:40=A0pm, "kami" <kamran.wad...@yahoo.co.uk> wrote: > > Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. I > have found these packages you mentioned in response to this guy's questio= n, > very good. But I don't exactly understand how to use these packages? > Any other comments welcome. The packages come with a testbench and documentation that explains how to use them. Read those first, then post more specific questions here if you have any. KJ
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