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Hi, I have a Lyrtech SFFSDR board, where a virtex4 SX35 is connected to the emif of a davinci dm6446. I woul like to create a very basic register accessible for reading and writing from the davinci. I tried to read xapp753, but unfortunately I wasn't able to thoroughly understand it . do you have a commented example?Article: 133526
On Jul 1, 9:29 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Register internal to the CPU or hardware register. What device are you using? > > ---Matthew Hicks > > > Hi everybody, > > > I am using PPC to configure number of LUTs using HWICAP, my question > > is , Is it possible to generate an interrupt internally according to a > > change in register value , as i want to do new configuration > > depending on this value? > > > thanks > > Fatma my device is xc2vp30Article: 133527
there is a sx95t, and a lx85, which is it? Austin PatC wrote: > Hi, > > I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit > DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device. > > The 500MHz input clock is driven to a BUFIO that connects to the CLK > input of the OSERDES blocks. > > This same input clock is driven to a BUFR that divides its frequency by > 2 and connects to the CLKDIV input of the OSERDES blocks and the read > side of an asynchronous FIFO that holds the data samples. > > Each OSERDES output is connected to an IODELAY element and then to a > OBUFDS. > > I added period constraints for all the clocks in the design into the UCF > file and built the code. It passed PAR with 0 timing errors. > > > > In Timing Analyzer tool, I noticed that the 500MHz input clock and its > associated BUFIO clock paths were not analyzed, whereas all the FPGA > fabric logic that runs @ 250MHz met the timing constraints. > > How can I make sure that my design does not have any timing issues at > the 500MHz input and BUFIO clocks? > > > Thanks in advance, > -Pat > > > PS: Originally posted on X's user forums by ShantM.Article: 133528
On Jul 2, 8:10 am, austin <aus...@xilinx.com> wrote: > there is a sx95t, and a lx85, which is it? It's mispelled. It should read sx95t Thanks, -PatC > Austin > > PatC wrote: > > Hi, > > > I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit > > DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device. > > > The 500MHz input clock is driven to a BUFIO that connects to the CLK > > input of the OSERDES blocks. > > > This same input clock is driven to a BUFR that divides its frequency by > > 2 and connects to the CLKDIV input of the OSERDES blocks and the read > > side of an asynchronous FIFO that holds the data samples. > > > Each OSERDES output is connected to an IODELAY element and then to a > > OBUFDS. > > > I added period constraints for all the clocks in the design into the UCF > > file and built the code. It passed PAR with 0 timing errors. > > > In Timing Analyzer tool, I noticed that the 500MHz input clock and its > > associated BUFIO clock paths were not analyzed, whereas all the FPGA > > fabric logic that runs @ 250MHz met the timing constraints. > > > How can I make sure that my design does not have any timing issues at > > the 500MHz input and BUFIO clocks? > > > Thanks in advance, > > -Pat > > > PS: Originally posted on X's user forums by ShantM.Article: 133529
First of all thanks for all the great advice I've got thusfar, quite outstanding! Jim, I had already tried the emulation route and as Mark has already pointed out the emulators really are not of a standard that makes it worthwhile. As for not being an FPGA project I only have this page... http://home.comcast.net/~olimar/DS/jumbotron/ as ANY sort of guide to doing something similar. The thought process really is that if Neal is almost able to do what I'm trying to do then maybe some similar equipment is not a bad idea! That siad I'd love to hear how an earth I'd even think of approaching this say with a PIC chip or similar???? Remember, electronics noob alert! Austin, I read your post in complete fear lol I see I have a LOT to learn here but I'm commited and if it takes some serious book reading and playing then I will do so, thank you very much for taking the time to give me some information! In fact I almost relish it in a strange way as its like jumping back in time and going back to writing 68k assembly code for the Atari St and Amiga. All right I know its different but its certainly good to get hands 'dirty' so to speak as I've become lazy as a .NET developer. I still remember my old VSYNC code for the Atari ST and the little tricks you could pull to get rid of that annoying border at the bottom and top of the screen, ahhh bliss! Urbrite, thank you for your excellent advice and information. Again, I see there is a lot to learn here but you have answered a lot of the odd questions. One thing I'm really quite worried about is blowing up the board or Nintendo DS cause I've done something stupid with how I connect them both. I envisage something like this.... Nintendo DS (Soldered wires on PCB) Spartan 3 Board Red [0-5] ----> <---- I/O Pins Male Header Spartan 3 Board Green [0-5] ----> <---- I/O Pins Male Header Spartan 3 Board Blue [0-5] ----> <---- I/O Pins Male Header Spartan 3 Board DCLK - Data Sampling clock ----> <---- I/O Pins Male Header Spartan 3 Board GSP1 - Vertical Sync ----> <---- I/O Pins Male Header Spartan 3 Board VGND - Assuming this is ground! ----> <---- I/O Pins Male Header Spartan 3 Board I have a multimeter here, should I do any voltage checks first etc or am I barking up the wrong tree as obviously digital signals will be rapid 'highs' and 'lows'? Also, how do I identify to the Spartan 3 Board that one of the pins is ground, is that just done as part of the pin assignment in ISE?? Sorry about the stupid questions, its difficult for a super noob to find his feet lol If anybody would like to work together on this I'm more then willing to make it worth their while :) Email me at pedwards at funkygamer .co.uk or just reply on here with how I can contact you! Thanks again guys.Article: 133530
Pat, How do you know "it wasn't analyzed" when you also say there is no warning, nor error, and all paths were properly constrained? One easy way to see if the paths are constrained properly is to tighten the constraint(s) until the tools report those paths do not meet timing. This is much the same as testing on the bench at higher and higher clock rates until the design fails, but instead you are doing this with the timing tools (rather than testing on the bench). Always best to use the tools to ensure timing is met, as testing a single device may not provide you with any confidence (that part might be really fast). AustinArticle: 133531
A book that is not too tough to get through, and is a golden reference on the subject: "High Speed Digital Design: A Handbook of Black Magic" by Howard Johnson I highly recommend it to anyone, hobbiest or professional, who ever has to connect more than two wires together (and expect them to work). Once you get the wires connected, programming the FPGA to capture the data is the next hurdle, but one that is more "software" than "hardware." Screw up the "software" and you just change the verilog, or VHDL code, and make a new bitstream. Screw up the hardware, and you are chasing gremlins potentially forever. For a reasonable reference (there are hundreds) on writing VHDL or verilog for FPGAs, "FPGA Prototyping by VHDL Examples" or "FPGA Prototyping by Verilog Examples" by Chiu (he has a series of books that solve problems in VHDL, and then identically in another book, in verilog) He also uses the Digilent Spartan 3 boards to do all the examples. I would buy the books, and read them FIRST, and then get the appropriate Spartan 3 board. You could also write the VHDL, or verilog, simulate it, and test the code before you even have the Spartan 3 board using the Xilinx (free) Webpack software. AustinArticle: 133532
On Jul 1, 11:03 am, Zhane <m...@hotmail.com> wrote: > On Jul 1, 5:38 pm, Sean Durkin <news_ju...@durkin.de> wrote: > > > > > Zhane wrote: > > > On Jul 1, 1:20 pm, PatC <p...@REMOVETHISpatocarr.com> wrote: > > >> Zhane wrote: > > >>> when i try to translate it, it tells me this > > >>> ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) > > >>> 'DCM_SP_INST' > > >>> in the design. To suppress this error specify the correct instance > > >>> name or > > >>> remove the constraint. > > >>> <snip> > > >>> my top.vhd, make use of a component from clockmanager.vhd ...inside > > >>> clockmanager.vhd has > > >>> what's wrong huh? > > > Since the instance is inside another module, you have to specify the > > complete path to the instance you want to constrain, e.g. > > > INST clockmanager_inst/DCM_SP_INST CLK_FEEDBACK = 1X; > > > ... and so on. clockmanager_inst is the instance name for the > > clockmanager-module you use in your top level. > > > > even after including in my top.vhd also cannot. Im still getting the > > > same error > > > But when i remove... > > > > INST DCM_SP_INST CLK_FEEDBACK = 1X; > > > INST DCM_SP_INST CLKDV_DIVIDE = 2.0; > > > INST DCM_SP_INST CLKFX_DIVIDE = 1; > > > INST DCM_SP_INST CLKFX_MULTIPLY = 2; > > > INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; > > > INST DCM_SP_INST CLKIN_PERIOD = 20.000; > > > INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; > > > INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; > > > INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; > > > INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; > > > INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; > > > INST DCM_SP_INST FACTORY_JF = C080; > > > INST DCM_SP_INST PHASE_SHIFT = 0; > > > INST DCM_SP_INST STARTUP_WAIT = FALSE; > > > > from my constraints file...i can do it w/o any error. > > > > should I remove them? > > > You can use attributes in your VHDL-code instead of specifying > > constraints in the UCF, or you can specify GENERICs when instantiating. > > Seehttp://tinyurl.com/4cwlf8 > > > HTH, > > Sean > > > -- > > My email address is only valid until the end of the month. > > Try figuring out what the address is going to be after that... > > thanks.. it solved the problem. > > I've been trying out the following code with TEMPUART.VHD as my top > module on my UART. I connected the Uart of my spartan to my PC using a > null modem connection. > > It's weird cause I never seem to be able to get the data I output , FF > and 0A, on my PC. I get 7F instead of FF... > > http://www.mediafire.com/?mjbgzgwxtwb << my source is located here Dropping the high order bit is most likely to be a problem with the PC settings. Make sure you have the word size set to 8 bits with no parity. Cheers, GaborArticle: 133533
"austin" <austin@xilinx.com> wrote in message news:g4gos5$4l02@cnn.xsj.xilinx.com... > I would buy the books, and read them FIRST, and then get the appropriate > Spartan 3 board. You could also write the VHDL, or verilog, simulate > it, and test the code before you even have the Spartan 3 board using the > Xilinx (free) Webpack software. There's something close to a rite of passage in writing a Hello World on each new system. Lighting an LED and making it spin with an encoder wheel sounds about right for embedded stuff. ;) I can heartily second the recommendation for Chiu's book. The pace is right for someone with some software and a little digital background. Even so, there's a tendency to not notice the full importance of some concepts in the understandable rush to expand your language "vocabulary." Respecting the need for a clock would have saved me a few headaches early on.Article: 133534
Then you are using a version of the PPC405 that doesn't support a coprocessor so there is no way to know the instantaneous value of internal registers. ---Matthew Hicks > On Jul 1, 9:29 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > >> Register internal to the CPU or hardware register. What device are >> you using? >> >> ---Matthew Hicks >> >>> Hi everybody, >>> >>> I am using PPC to configure number of LUTs using HWICAP, my >>> question is , Is it possible to generate an interrupt internally >>> according to a change in register value , as i want to do new >>> configuration depending on this value? >>> >>> thanks >>> Fatma > my device is xc2vp30 >Article: 133535
On Wed, 2 Jul 2008 03:32:07 -0700 (PDT), manuel-lozano@mixmail.com wrote: >Hi, > >I'm looking for a minipci card with an FPGA in order to work for some >project. The PCI interface should be programmed inside the FPGA apart >from other application specific functions. > >Unfortunately I have only found standard PCIs > >Do anybody know any breadboard mini pci (with or without FPGA) that I >can use as starting point. like this perhaps? http://enterpoint.co.uk/moelbryn/minican.html - BrianArticle: 133536
MikeWhy wrote: > There's something close to a rite of passage in writing a Hello World > on each new system. Lighting an LED and making it spin with an encoder > wheel sounds about right for embedded stuff. ;) I'd venture to make a further suggestion along these lines. What you want to achieve isn't exactly noob stuff - there's a reasonably steep learning curve ahead. As such I'd suggest... * Buy your FPGA starter board but don't connect it to anything! * Lighting a LED is a pretty good start * You need to familiarise yourself with video generation before you start sampling and regenerating other sources. I'd suggest you play around with generating some VGA video on the board itself - emulation of a simple bit-mapped arcade game (Space Invaders) would be a good start and there's plenty of examples to get you started. * Once you've "mastered" video generation, then you can start looking at connecting to the DS and sampling video. For extra credit: * Write your own ARM cores and emulate the DS in the FPGA itself, doing away with the need to sample video! ;) That should keep you busy for the best part of a week! :P Just my AUD$0.02 worth... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 133537
On Jul 2, 1:27 pm, austin <aus...@xilinx.com> wrote: > Pat, > > How do you know "it wasn't analyzed" when you also say there is no > warning, nor error, and all paths were properly constrained? > > One easy way to see if the paths are constrained properly is to tighten > the constraint(s) until the tools report those paths do not meet timing. > > This is much the same as testing on the bench at higher and higher clock > rates until the design fails, but instead you are doing this with the > timing tools (rather than testing on the bench). > > Always best to use the tools to ensure timing is met, as testing a > single device may not provide you with any confidence (that part might > be really fast). > > Austin Hi, Here are the UCF constraints I used to do the build NET "dac_clk_in_p" TNM_NET = dacclk_in_p; NET "dac_clk_in_n" TNM_NET = dacclk_in_n; NET "dac_clk_div" TNM_NET = BUFR_CLK; NET "sys_clk" TNM_NET = sysclk; TIMESPEC TS_dac_clk_in_p = PERIOD dacclk_in_p 2 ns PRIORITY 1; #500MHz TIMESPEC TS_dac_clk_in_n = PERIOD dacclk_in_n 2 ns PRIORITY 1; #500MHz TIMESPEC TS_BUFR_CLK = PERIOD "BUFR_CLK" 4 ns PRIORITY 1; #250MHz TIMESPEC TS_sys_clk = PERIOD sysclk 4 ns PRIORITY 1; #250MHz The timing analyzer report below lead me to the conclusion that these paths were not analyzed ================================================================================ Timing constraint: TS_dac_clk_in_p = PERIOD TIMEGRP "dacclk_in_p" 2 ns HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_in_n = PERIOD TIMEGRP "dacclk_in_n" 2 ns HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_BUFR_CLK = PERIOD TIMEGRP "BUFR_CLK" 4 ns HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div = PERIOD TIMEGRP "dac_clk_div" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div_0 = PERIOD TIMEGRP "dac_clk_div_0" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div_1 = PERIOD TIMEGRP "dac_clk_div_1" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div_2 = PERIOD TIMEGRP "dac_clk_div_2" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div_3 = PERIOD TIMEGRP "dac_clk_div_3" TS_dac_clk_in_p * 2 HIGH 50% PRIORITY 1; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_dac_clk_div_4 = PERIOD TIMEGRP "dac_clk_div_4" TS_dac_clk_in_n * 2 HIGH 50% PRIORITY 1; 933 paths analyzed, 367 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 3.613ns. -------------------------------------------------------------------------------- Thanks, ShantArticle: 133538
On Jul 3, 5:34=A0am, Gabor <ga...@alacron.com> wrote: > On Jul 1, 11:03 am, Zhane <m...@hotmail.com> wrote: > > > > > On Jul 1, 5:38 pm, Sean Durkin <news_ju...@durkin.de> wrote: > > > > Zhane wrote: > > > > On Jul 1, 1:20 pm, PatC <p...@REMOVETHISpatocarr.com> wrote: > > > >> Zhane wrote: > > > >>> when i try to translate it, it tells me this > > > >>> ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) > > > >>> 'DCM_SP_INST' > > > >>> =A0 =A0in the design. =A0To suppress this error specify the corre= ct instance > > > >>> name or > > > >>> =A0 =A0remove the constraint. > > > >>> <snip> > > > >>> my top.vhd, make use of a component from clockmanager.vhd ...insi= de > > > >>> clockmanager.vhd has > > > >>> what's wrong huh? > > > > Since the instance is inside another module, you have to specify the > > > complete path to the instance you want to constrain, e.g. > > > > INST clockmanager_inst/DCM_SP_INST CLK_FEEDBACK =3D 1X; > > > > ... and so on. clockmanager_inst is the instance name for the > > > clockmanager-module you use in your top level. > > > > > even after including in my top.vhd also cannot. Im still getting th= e > > > > same error > > > > But when i remove... > > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLK_FEEDBACK =3D 1X; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKDV_DIVIDE =3D 2.0; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKFX_DIVIDE =3D 1; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKFX_MULTIPLY =3D 2; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKIN_DIVIDE_BY_2 =3D FALSE= ; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKIN_PERIOD =3D 20.000; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKOUT_PHASE_SHIFT =3D NONE= ; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DESKEW_ADJUST =3D SYSTEM_SY= NCHRONOUS; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DFS_FREQUENCY_MODE =3D LOW; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DLL_FREQUENCY_MODE =3D LOW; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DUTY_CYCLE_CORRECTION =3D T= RUE; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST FACTORY_JF =3D C080; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST PHASE_SHIFT =3D 0; > > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST STARTUP_WAIT =3D FALSE; > > > > > from my constraints file...i can do it w/o any error. > > > > > should I remove them? > > > > You can use attributes in your VHDL-code instead of specifying > > > constraints in the UCF, or you can specify GENERICs when instantiatin= g. > > > Seehttp://tinyurl.com/4cwlf8 > > > > HTH, > > > Sean > > > > -- > > > My email address is only valid until the end of the month. > > > Try figuring out what the address is going to be after that... > > > thanks.. it solved the problem. > > > I've been trying out the following code with TEMPUART.VHD as my top > > module on my UART. I connected the Uart of my spartan to my PC using a > > null modem connection. > > > It's weird cause I never seem to be able to get the data I output , FF > > and 0A, on my PC. I get 7F instead of FF... > > >http://www.mediafire.com/?mjbgzgwxtwb<< my source is located here > > Dropping the high order bit is most likely to be a problem with > the PC settings. =A0Make sure you have the word size set to 8 bits > with no parity. > > Cheers, > Gabor i've set on the PC side to 8bits with no parity. but i can only get 7F instead of FFArticle: 133539
hai, I understood that the design synthesized in one device of xilinx can be implemented in the other device.. but whether the design synthesized from other tools like celoxica compiler for one xilinx device can be implemented in other device.? regards, rajArticle: 133540
Hi All, I have a big system which uses more than 1000 Spartan3 FPGAs. The chips are configured either remotely via a dedicated communication interface, or downloaded automatically from FLASH by simple state machine based on another programmable device. The problem is, that in some cases (probability of c.a. 2%) the INIT_B doesn't go down after PROG_B is set to LOW. When I retry to reconfigure the chip in which the problem occured (without power cycling), the problem usually disappears. However sometimes, INIT_B doesn't go LOW during a few consecutive retries. What can be the cause of the above problem? It seems, that JTAG pins are correctly pulled up (I've heard, that they may disturb the configuration problem). -- TIA & Regards, Wojtek ZabolotnyArticle: 133541
Hi thanks for your response. Unfortunately this is a PCI card not a MiniPCI. Best regards, Manuel On 3 jul, 02:39, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 2 Jul 2008 03:32:07 -0700 (PDT), manuel-loz...@mixmail.com > wrote: > > >Hi, > > >I'm looking for a minipci card with an FPGA in order to work for some > >project. The PCI interface should be programmed inside the FPGA apart > >from other application specific functions. > > >Unfortunately I have only found standard PCIs > > >Do anybody know any breadboard mini pci (with or without FPGA) that I > >can use as starting point. > > like this perhaps? > > http://enterpoint.co.uk/moelbryn/minican.html > > - BrianArticle: 133542
Im trying to make use of the fifo in my Spartan3E starter kit i've added the component declaration and instantiation template as instructed in the vho file. but im getting the following error when i try to implement the design ERROR:NgdBuild:604 - logical block 'FIFO' with type 'fifo_generator_v3_3' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fifo_generator_v3_3' is not supported in target 'spartan3e'. Ive also added "Library XilinxCoreLib;" at my top module, which refers to the fifo component. am I missing something?Article: 133543
"Zhane" <me75@hotmail.com> wrote in message news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com... > Im trying to make use of the fifo in my Spartan3E starter kit > > > i've added the component declaration and instantiation template as > instructed in the vho file. but im getting the following error when i > try to implement the design > > ERROR:NgdBuild:604 - logical block 'FIFO' with type > 'fifo_generator_v3_3' could > not be resolved. A pin name misspelling can cause this, a missing > edif or ngc > file, or the misspelling of a type name. Symbol > 'fifo_generator_v3_3' is not > supported in target 'spartan3e'. > > Ive also added "Library XilinxCoreLib;" at my top module, which refers > to the fifo component. > > am I missing something? Hi, this error indicates that the design hierarchy is not complete most likely there is also an ngc file generated which is the actual content of the core for ISE is this file in the same folder as your ise project? if not you could set the macro search path to include the folder in searching for all required files Regards, StephanArticle: 133544
hi all, I am using PPC to make runtime configuration to certain luts in EDK , my problem is i created my own C function , and i want to use my c function in many designs so, i created header file where this function is defined on it, and in my c function in the top i include the .h file, and finally in my normal c code i included the .h file , and of cource in the code i called my c function, i got an error undefined reference to `configureLutsfunction' collect2: ld returned 1 exit status i don't know what is the problem thanks FatmaArticle: 133545
On Jul 2, 8:43 am, PatC <p...@REMOVETHISpatocarr.com> wrote: > Hi, > > I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit > DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device. > > The 500MHz input clock is driven to a BUFIO that connects to the CLK > input of the OSERDES blocks. > > This same input clock is driven to a BUFR that divides its frequency by > 2 and connects to the CLKDIV input of the OSERDES blocks and the read > side of an asynchronous FIFO that holds the data samples. > > Each OSERDES output is connected to an IODELAY element and then to a OBUFDS. > > I added period constraints for all the clocks in the design into the UCF > file and built the code. It passed PAR with 0 timing errors. > > In Timing Analyzer tool, I noticed that the 500MHz input clock and its > associated BUFIO clock paths were not analyzed, whereas all the FPGA > fabric logic that runs @ 250MHz met the timing constraints. > > How can I make sure that my design does not have any timing issues at > the 500MHz input and BUFIO clocks? > > Thanks in advance, > -Pat > > PS: Originally posted on X's user forums by ShantM. Hi Pat, I think that the 500MHz clock does not come under timing analysis because there is no fabric logic in this clock domain. Since the only things in this clock domain are hard IP blocks (OSERDES), the synthesis and PAR tools cannot do anything to to affect the timing (bar issue a warning if it detects the clock is too fast or slow). You need to refer to the V5's DC and switching datasheet to ensure correct circuit operation. Cheers RobArticle: 133546
On Jul 3, 4:54=A0pm, "Stephan van Beek" <stephan.vanb...@mathworks.nl> wrote: > "Zhane" <m...@hotmail.com> wrote in message > > news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com... > > > > > Im trying to make use of the fifo in my Spartan3E starter kit > > > i've added the component declaration and instantiation template as > > instructed in the vho file. but im getting the following error when i > > try to implement the design > > > ERROR:NgdBuild:604 - logical block 'FIFO' with type > > 'fifo_generator_v3_3' could > > =A0 not be resolved. A pin name misspelling can cause this, a missing > > edif or ngc > > =A0 file, or the misspelling of a type name. Symbol > > 'fifo_generator_v3_3' is not > > =A0 supported in target 'spartan3e'. > > > Ive also added "Library XilinxCoreLib;" at my top module, which refers > > to the fifo component. > > > am I missing something? > > Hi, > > this error indicates that the design hierarchy is not complete > most likely there is also an ngc file generated which is the actual conten= t > of the core for ISE > is this file in the same folder as your ise project? > if not you could set the macro search path to include the folder in > searching for all required files > > Regards, > Stephan how to set a macro search path?Article: 133547
Hi all, I wanted to know about the different debug interfaces used(or standards present like JTAG etc...) in a wireless SOC having a RISC processor. ARM uses some thing called trace debugging, I didn't get the concept clearly. Can anyone enlighten me on the same. I know about JTAG. Thanks, VittalArticle: 133548
Thanks again for all your responses. I'm always amazed at the help available and the time people put in to help others it really is appriciated. Yes, books it is, some orders for them already made on Amazon. Just installing the ISE suite to start 'playing' there and yes, I think your all totally right, LED's and Hello Worlds are the order of the day for now! lol @ Mark, when I write the ARM9 cores and the relevant emulation code I'll be sure to upload it and tell the world !!!! :) :) :) Thanks again chaps I'll keep you all updated so you can have a good chuckle at watching a noob stratch his head and do lots of stupid things :)!!!!!Article: 133549
Hello, I ask for people who has detected some problem in programs running in External Memory (Micron DDR SDRAM). These problems are about "printf" and "malloc" functions, and the results are unexpected. Best Regards for your answers.
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