Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Fri, 19 Sep 2008 15:34:19 -0500, Jon Elson <jmelson@wustl.edu> wrote: >Hello, all, > >I just set up a new system with CentOS 5 (based on Red Hat Enterprise >Linux) and tried to install WebPack 10.1 on it. It says : > >Product is not supported on "Linux x86_64" platform. >Any ideas? Is WebPack totally restricted to just a couple OS versions? It's officially supported on just a couple of versions. However when I installed SUSE-Linux 11 (64-bit) on an AMD-64 machine, the install process gave me the option of installing 32-bit compatibility libraries. (I don't know if that's unique to SUSE, or unique to version 11, or commonplace. I just said yes!). Naturally Webpack wouldn't install ... until I edited the Linux-64 version check out of the setup script and tried it anyway, on the theory that hopefully he 32-bit compat libraries would help. It seems to run just fine. (NOTE: Haven't tried device programming with USB or parallel cables, so there may be problems lurking there) Just one datapoint, not a definitive answer. - BrianArticle: 135201
> On Fri, 19 Sep 2008 15:34:19 -0500, Jon Elson <jmelson@wustl.edu> > wrote: > >> Hello, all, >> >> I just set up a new system with CentOS 5 (based on Red Hat Enterprise >> Linux) and tried to install WebPack 10.1 on it. It says : >> >> Product is not supported on "Linux x86_64" platform. >> >> Any ideas? Is WebPack totally restricted to just a couple OS >> versions? >> > It's officially supported on just a couple of versions. > > However when I installed SUSE-Linux 11 (64-bit) on an AMD-64 machine, > the install process gave me the option of installing 32-bit > compatibility libraries. (I don't know if that's unique to SUSE, or > unique to version 11, or commonplace. I just said yes!). > > Naturally Webpack wouldn't install ... until I edited the Linux-64 > version check out of the setup script and tried it anyway, on the > theory that hopefully he 32-bit compat libraries would help. > > It seems to run just fine. > > (NOTE: Haven't tried device programming with USB or parallel cables, > so there may be problems lurking there) > > Just one datapoint, not a definitive answer. > > - Brian > I just installed ISE 10 on a 64-bit version of Fedora 9. Both 32-bit and 64-bit versions of the binaraies work fine. I had to spend some extra time getting both USB and Parallel III programming working (namely installing fxload, compiling my own libusb drivers, and exporting some variables), but it all works great now. ---Matthew HicksArticle: 135202
Jon Elson wrote: > That looks pretty much like a 32-bit CPU to me. The CPUs read out as : [...] > model name : Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz The Core 2 Duo is a 64-bit CPU. You can install either 32-bit or 64-bit Linux on it. Do a 'uname -p' to find out whether you are running an i386 or x86_64 kernel. If you're running x86_64, you can install WebPACK but you'll have to force it to install the 32-bit version instead of the 64-bit version (since the latter isn't actually provided in WebPACK). This used to require either editing one of the Xilinx scripts involved early in the setup process, or skipping that script and invoking the 32-bit installer directly. Perhaps in newer versions of WebPACK they may have come up with a cleaner way to do it.Article: 135203
General Schvantzkopf wrote: > If you are running 64 CentOS you can always > put a 32 bit VM on it to install the tools. You don't need to go to that extreme. Just look at the scripts that start the installation. They do some checks to decide whether the host is 32-bit or 64-bit. Just patch it to always think it's 32-bit, and the install works fine. It would be nice if Xilinx made the script smart enough that on a 64-bit host, it would revert to doing a 32-bit install if the 64-bit binaries weren't available (as is the case with WebPACK).Article: 135204
Hello, I want to make a Virtex-II Pro on the Xilinx XUPV2P (http:// www.xilinx.com/univ/xupv2p.html, http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P) talk to an Stratix GX on the Altera High-Speed Development Kit, Stratix GX Edition (http://www.altera.com/literature/ug/ ug_stx_gx_hs_dev_kit.pdf?GSA_pos=1&WT.oss_r=1&WT.oss=High-Speed %20Development%20Kit,%20Stratix%20GX%20Edition). I want the communication be fast, using the gigabit transcievers on those FPGAs. I am aware that Xilinx has Aurora and Altera has SerialLite-II. However, are those protocols compatible with each other? Will simply a point to point connectio with SMA (connector and cable) work for my purpose? Will that communication be bidirectional though the same cable, or will it need separate point to point connection in each direction? I am a completely newbie to gigabit transceivers, and also rather new to Altera brand, wlthough have used Xilinx for many years. I will appreciate your advice. Kind regards for your fast reply. -- JaaCArticle: 135205
On Sep 19, 9:54 am, Peter Alfke <pe...@xilinx.com> wrote: > After 13 years and >2000 postings I will retire from comp.arch.fpga. > I think I have helped some, informed many, and irritated only a few. > It has been a significant part of my life, and I will miss it. (But I > will keep lurking from home). > Xilinx asked me to organize the user documentation for the next > generations of Virtex and Spartan devices. > That keeps me real busy, and I hope you will appreciate the results in > due course. > Cheers, Good-Bye und Auf Wiedersehen ! > Peter Alfke Peter - Say it's not so! Is this a cruel, early April Fools prank? You'll be missed, your insight has been wonderful! John ProvidenzaArticle: 135206
On Sep 19, 4:38=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Fri, 19 Sep 2008 09:54:27 -0700 (PDT), Peter Alfke <pe...@xilinx.com> > wrote: > > >After 13 years and >2000 postings I will retire from comp.arch.fpga. > >I think I have helped some, informed many, and irritated only a few. > >It has been a significant part of my life, and I will miss it. (But I > >will keep lurking from home). > > You'll be missed. Thanks for the help and advice you have given over the > years. > > - Brian Hi Peter, I have never met you, but you are considered as my best friend and teacher in the FPGA group in my mind; I have never heared your voice, but I read each of your postings silently; I have never known your age, but I remember the day I read the best article coauthored by you about asynchronous FIFO in my life; I have never been in Xilinx, but I feel its excellence through your service with this group in authoritive and informative voice. Now comp.conf.fpga group and I will miss you a lot. Your services in this group are greatly appreciated. WengArticle: 135207
On Sep 19, 3:48=A0pm, Marlboro <cco...@netscape.net> wrote: > Remember back in the old days, the Xlnx sw can detect your ucf syntax > error almost immediately and point out which error whih c line.. blah > blah.. > > But in the 10.1 (dont know what happened to the others), it take like > 10 minnutes or so to do some blah blah translate then it ends up to > tell that your ucf got a problem. =A0Then you have fix the ucf file then > re-run everything.. then take another 10 minutes to find out your ucf > has another syntax error, what's the progress here? I typically don't update a software tool unless there is a pressing need to do so. This is especially true of a synthesis tool. I'm still running ISE 8.1 - it's currently meeting my area and timing requirements. Darol KlawetterArticle: 135208
Darol Klawetter <darol.klawetter@l-3com.com> wrote: >On Sep 19, 3:48=A0pm, Marlboro <cco...@netscape.net> wrote: >> Remember back in the old days, the Xlnx sw can detect your ucf syntax >> error almost immediately and point out which error whih c line.. blah >> blah.. >> >> But in the 10.1 (dont know what happened to the others), it take like >> 10 minnutes or so to do some blah blah translate then it ends up to >> tell that your ucf got a problem. =A0Then you have fix the ucf file then >> re-run everything.. then take another 10 minutes to find out your ucf >> has another syntax error, what's the progress here? > >I typically don't update a software tool unless there is a pressing >need to do so. This is especially true of a synthesis tool. I'm still >running ISE 8.1 - it's currently meeting my area and timing >requirements. I have been using ISE8.2 for a project but it is terribly slow. IIRC the older versions are more faster. But then again; writing an IDE is not Xilinx's core business. They really should wake-up and write an Eclipse plugin instead of keep on doing something they obviously know nothing about. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135209
On 2008-09-19 18:54:27 +0200, Peter Alfke <peter@xilinx.com> said: > After 13 years and >2000 postings I will retire from comp.arch.fpga. > I think I have helped some, informed many, and irritated only a few. > It has been a significant part of my life, and I will miss it. (But I > will keep lurking from home). > Xilinx asked me to organize the user documentation for the next > generations of Virtex and Spartan devices. > That keeps me real busy, and I hope you will appreciate the results in > due course. > Cheers, Good-Bye und Auf Wiedersehen ! > Peter Alfke I'm quite sad to hear that you are leaving. Your postings have always been some of the most informational in this group. Best wishes for your new task at Xilinx PS : We are still waiting for "Six not so easy Pieces" :) GreetingsArticle: 135210
Hello everyone, I'm tired of using the Xilinx ISE to look at RTL schematics, mainly because it's so slow and cumbersome to use. What I'd like to do is output a netlist and use another script to process that netlist into input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). I have figured out how to get the Xilinx tools to output a netlist, but it appears they output a 'technology' version and not an 'RTL' version of the netlist. Is there any way to get the tools to output a netlist that is in the more useful (to me) 'RTL' format? My desire is to be able to write VHDL code, build it with my build process and check the RTL without ever having to enter Xilinx's IDE. I'd also like to be able to easily extract schematics for inclusion into the chronicle of my personal project at http://www.harp-project.com/, but the Xilnix tools make this incredibly difficult. Thanks for any info, thuttArticle: 135211
I've been told that Altera has patented I/O technology that makes DDR3 interfacing "better" (in quotes because that could mean anything). I received this answer when I asked about DDR3 support since we are considering migrating from Xilinx to Altera. The answer was that Altera, due to this technology, is able to support DDR3 at 533MHz clock rate while Xilinx seems to be tentative about 400MHz support. What's the real story? -MartinArticle: 135212
m wrote: > I've been told that Altera has patented I/O technology that makes DDR3 > interfacing "better" (in quotes because that could mean anything). I > received this answer when I asked about DDR3 support since we are > considering migrating from Xilinx to Altera. The answer was that > Altera, due to this technology, is able to support DDR3 at 533MHz > clock rate while Xilinx seems to be tentative about 400MHz support. > > What's the real story? I don't know, but I can guess something. No idea, if this is even close, haven't looked at Altera parts for awhile... In DDR2 (and I suppose it's the same for DDR3) the memory chips have On-Die-Termination (ODT), that can be turned on and off through a dedicated IO. The idea is that you only turn it on when you send data towards the memory chip, so there's a termination at the end of the transmission line. The rest of the time the termination is turned off to conserve power and avoid detrimental effects if you want to transmit the OTHER way (i.e. from the memory chip to the controller, e.g. the FPGA). Now, ideally this should be possible on BOTH sides, that is the termination should be switchable on the side of the controller as well. I know that in Xilinx devices this is not possible. DCIs are either turned on or off permanently, it's "hardwired" in the bitstream. That usually means that you burn tons of power and signal integrity is not the optimum it could be. Maybe recent Altera devices have the ability to turn off IO terminations during operation? That would explain it and could be helpful. That's my guess, for what it's worth. :) cu, SeanArticle: 135213
"Peter Alfke" <peter@xilinx.com> wrote in message news:83321799-204c-47e6-8c7b-0ac53ceab040@b2g2000prf.googlegroups.com... > After 13 years and >2000 postings I will retire from comp.arch.fpga. > I think I have helped some, informed many, and irritated only a few. > It has been a significant part of my life, and I will miss it. (But I > will keep lurking from home). > Xilinx asked me to organize the user documentation for the next > generations of Virtex and Spartan devices. > That keeps me real busy, and I hope you will appreciate the results in > due course. > Cheers, Good-Bye und Auf Wiedersehen ! > Peter Alfke Thank you Peter for all your care and effort with this group over the years. You will be sorely missed and affeectionately remembered. It was highlight for me when I met you in person once and shook your hand at a Xilinx seminar in Sydney Australia. Best wishes for your new roles and kindest regards, Tony BurchArticle: 135214
I recently purchased a Xilinx Spartan II development kit from www.easyfpga.com. My intention is to use the board to generate a BPSK modulated intermediate frequency. I want to connect an output pin directly to a lowpass filter (e.g. this one: http://www.mini-circuits.com/pdfs/BLP-10.7+.pdf ) that has a 50 ohm input. Let's say I generate a sequence of 1's and 0's at a sample rate of 20 MHz. If I consider this an analog signal it is a 10 MHz square wave. This square wave has frequency components at 10, 30, 50, 70 etc. MHz. If the output voltage is +3.3 VDC for a 1, and 0 for VDC for a 0 then there is also a DC bias. If I lowpass filter this signal I should end up with a 10 MHz sine wave plus the DC bias. If I then block the DC with a capacitor I should have a 10 MHz sine wave centered at 0 volts...right? The Xilinx documentation says I can choose from a variety digital outputs, for example LVTTL. My question is can I just connect the center pin of my coax to the output pin of the FPGA board, and ground the shield conductor? Do I need some sort of impedence matching? How do I do that? Thank you, BrianArticle: 135215
If you have slow slew rate selected, I would just connect the pin right to
the coax- it will work fine. If you have fast slew rate selected, series
terminate with a 33 - 50 own resistor.
You can put the DC blocking capacitor right at the FPGA pin as well.
In article <b494fffb-34a2-4872-8b3b-d2618b6af742@k37g2000hsf.googlegroups.com>,
<heilig@iname.com> wrote:
>I recently purchased a Xilinx Spartan II development kit from www.easyfpga.com.
>My intention is to use the board to generate a BPSK modulated
>intermediate frequency. I want to connect an output pin directly to a
>lowpass filter (e.g. this one: http://www.mini-circuits.com/pdfs/BLP-10.7+.pdf
>) that has a 50 ohm input.
>
>Let's say I generate a sequence of 1's and 0's at a sample rate of 20
>MHz. If I consider this an analog signal it is a 10 MHz square wave.
>This square wave has frequency components at 10, 30, 50, 70 etc. MHz.
>If the output voltage is +3.3 VDC for a 1, and 0 for VDC for a 0 then
>there is also a DC bias. If I lowpass filter this signal I should end
>up with a 10 MHz sine wave plus the DC bias. If I then block the DC
>with a capacitor I should have a 10 MHz sine wave centered at 0
>volts...right?
>
>The Xilinx documentation says I can choose from a variety digital
>outputs, for example LVTTL. My question is can I just connect the
>center pin of my coax to the output pin of the FPGA board, and ground
>the shield conductor? Do I need some sort of impedence matching? How
>do I do that?
>
>Thank you,
>Brian
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 135216I'm interested if anyone is using or is even familiar with the HDL Companion product from HDL Works. Just looking for comments on the tool from actual users. Looks interesting to me mainly for the hierarchy and signal path browsing capabilities. Thanks, RobArticle: 135217
Hi Peter! As others have already pointed out, your and Austin's presense here was important not only for us, your customers, but also for Xilinx. It's too bad you both have now left... But let's look at the bright side: "Peter Alfke" <peter@xilinx.com> wrote > (But I will keep lurking from home). This is our hope for the X future :) All the best, /MikhailArticle: 135218
Hi all, I'm having problems with ISE seemingly ignoring timing constraints set in the UCF file. One of the constraints ignored comes from Xilinx's MIG tool and looks like this: INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL"; TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS "TS_SYS_CLK" * 4; I'm not getting any errors, such as unable to locate nets, rather the constraint seems ignored and looking in the timing report it is these very paths that are failing (by a long way). I thought that if the target nets don't exist then you get a translate error. I am using partitions in the design. I've tried to do a build after a "clean up project files" and the constraint is still ignored. Any ideas? RobArticle: 135219
On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote: > I've been told that Altera has patented I/O technology that makes DDR3 > interfacing "better" (in quotes because that could mean anything). =A0I > received this answer when I asked about DDR3 support since we are > considering migrating from Xilinx to Altera. =A0The answer was that > Altera, due to this technology, is able to support DDR3 at 533MHz > clock rate while Xilinx seems to be tentative about 400MHz support. > > What's the real story? > > -Martin AFIK the big difference is that Altera have technology that allows continual monitoring and adjustment of the IO delays. This means that the uncertainties are reduced and they can run at higher frequencies. Also, Altera have IP solutions for DIMMs, but I believe that Xilinx will only support components at the moment. Interfacing to DIMMs is much harder than a single component because the address and control signals are routed in a "fly-by" topology meaning that reads and writes need to be levelled. HTH RobArticle: 135220
On Sep 19, 8:48=A0pm, Marlboro <cco...@netscape.net> wrote: > Remember back in the old days, the Xlnx sw can detect your ucf syntax > error almost immediately and point out which error whih c line.. blah > blah.. > > But in the 10.1 (dont know what happened to the others), it take like > 10 minnutes or so to do some blah blah translate then it ends up to > tell that your ucf got a problem. =A0Then you have fix the ucf file then > re-run everything.. then take another 10 minutes to find out your ucf > has another syntax error, what's the progress here? The translate stage finds the error, but changing the UCF should not require you to re-synthesize. After changing the UCF you should immediately be able to re-run translate. Are you selecting "Rerun all"?Article: 135221
Jaime Andrés Aranguren Cardona wrote: > Hello, > > I want to make a Virtex-II Pro on the Xilinx XUPV2P (http:// > www.xilinx.com/univ/xupv2p.html, > http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P) > talk to an Stratix GX on the Altera High-Speed Development Kit, > Stratix GX Edition (http://www.altera.com/literature/ug/ > ug_stx_gx_hs_dev_kit.pdf?GSA_pos=1&WT.oss_r=1&WT.oss=High-Speed > %20Development%20Kit,%20Stratix%20GX%20Edition). I want the > communication be fast, using the gigabit transcievers on those FPGAs. > > I am aware that Xilinx has Aurora and Altera has SerialLite-II. > However, are those protocols compatible with each other? Will simply a > point to point connectio with SMA (connector and cable) work for my > purpose? Will that communication be bidirectional though the same > cable, or will it need separate point to point connection in each > direction? > > I am a completely newbie to gigabit transceivers, and also rather new > to Altera brand, wlthough have used Xilinx for many years. I will > appreciate your advice. > > Kind regards for your fast reply. > > -- > > JaaC Aurora and SerialLite-II are not the same protocol so they are not compatible. You will need to decided what protocol you want to use and implement it in each device. On the connection side you need will 4 coax cables to connect the TXP/TXN pairs to the RXP/RXN pairs. You should also check to see that AC coupling is used in each direction to ensure correct signaling levels for each device. Ed McGettigan -- Xilinx IncArticle: 135222
thutt wrote: > Hello everyone, > > I'm tired of using the Xilinx ISE to look at RTL schematics, mainly > because it's so slow and cumbersome to use. What I'd like to do is > output a netlist and use another script to process that netlist into > input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). > > I have figured out how to get the Xilinx tools to output a netlist, > but it appears they output a 'technology' version and not an 'RTL' > version of the netlist. > > Is there any way to get the tools to output a netlist that is in the > more useful (to me) 'RTL' format? > > My desire is to be able to write VHDL code, build it with my build > process and check the RTL without ever having to enter Xilinx's IDE. > I'd also like to be able to easily extract schematics for inclusion > into the chronicle of my personal project at > http://www.harp-project.com/, but the Xilnix tools make this > incredibly difficult. > > Thanks for any info, > thutt > I think the RTL schematic is in a proprietary format. I don't know if it's possible to view it in another tool. If you want a better viewer for the technology schematic, you can import the NGC into PlanAhead, which now comes with ISE. If you want a better RTL viewer, you probably have to resynthesize with a different synthesizer and view the schematic in that tool. -KevinArticle: 135223
On Sep 17, 10:19=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > "knight" <krshe...@gmail.com> wrote in message > > news:9435ad0e-1a3b-4397-96e3-02d522d01268@e39g2000hsf.googlegroups.com...= > Hi > > > how can i represent any number in 32 bit signed1QNformat.. > > Let the number be 1.5 > > From web search...http://www.actel.com/ipdocs/CoreCORDIC_DS.pdf > Table 3 > HTH., Syms. Hey thanx a lotArticle: 135224
On Sep 18, 1:08=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Sep 17, 3:23=A0pm, osquillar <ogm101...@hotmail.com> wrote: > > > > > On 17 sep, 23:20, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Sep 17, 7:37=A0am, osquillar <ogm101...@hotmail.com> wrote: > > > > > Hello all, I'm working with an microblaze system and I'm trying to > > > > work with a Micron MT48LC16M16 memory and something strange happens= , > > > > It seem than I can read positions all position but if I try to writ= e > > > > in positions 00 and 01 nothing changes and if I write something in > > > > positions 02 and 03 they seems to be written in position 00 and 01.= It > > > > happens the same with the rest of the memory. > > > > > Any idea?. > > > > > Regards > > > > Are you using a development board or have you rolled your own? > > > If you produced your own board, check the power pins for proper > > > hookup. =A0It's too wasy to have power not hooked up properly through > > > your part and "accidentally" power the device through address or data > > > lines biasing the protection diodes. > > > I rolled my own board. I checked the power and ground supply pins and > > all is correct. I use the gdb debugger for my application and opening > > the memory window I see that effect, writing in address 00 has no > > effect but writing in address 02 the datas seems to be written in > > address 00 and writing in address 06 the datas are written in address > > 04, and the value of the address 02 and 06 remains 0xffff. > > I'm using the mch_opb_sdram controller for this pourpose.- Hide quoted = text - > > > - Show quoted text - > > Perhaps timing is an issue? =A0Do you have the Tco for the address, the > Tsu and Th of the memory, and the Tskew of the clock between the two > devices? > > Are any of the address pins shorted to something else on the board? > Are you sure? > > Have you written to all addresses or just the 5 (or so) you've > mentioned so far? Hello John.... for example... ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F INITIAL DATA 12 FF FA DE 32 25 25 17 14 25 DA 11 BC 67 FE A2 If I try to write in address 00 , 01, 02, etc ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 If I read the result after writting. ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 If you do this all along the memory the effect is the same. All the timing parameters are correct and I've checked with an oscilloscope the signals and seems to be correct also. Any idea?. Thanks
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z