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Hello everyone, Good Day. I want to download the following VHDL code to FPGA Xilinx Virtex-4. process(clk) begin if (clk'event and clk = '1') then if (cycle = '0') then x <= a; cycle <= '1'; else x <= b; cycle <= '0'; end if; end if; end process; I have downloaded this to the FPGA. I have given input by DIP switch (An active low signal is generated when a given switch is ON) and output is in LED (turned ON by driving the LEDx signal to logic 0). the result is as follows: 1. when a=11 and b=11 (by DIP switch), ALL output LED is OFF 2. when a=01 and b=01 , x(1) is MORE BRIGHT, x(0) is OFF 3. when a=11 and b=01 , x(1) is LESS BRIGHT, x(0) is OFF Can I explain the result like this, because of the RAPID clocking, x changes rapidly. When it has the same value as previous, it is BRIGHT. and when it has different values, it is less bright. I am using CLK_100 (System Clock This clock input is connected to a 100MHz LVTTL oscillator) as clk. How can I control the clock speed? regards and thanks in advance panthoArticle: 136126
On 3 Nov., 05:42, "500milesaway" <500milesa...@gmail.com> wrote: [..] > 1. when a=3D11 and b=3D11 (by DIP switch), ALL output LED is OFF > 2. when a=3D01 and b=3D01 , x(1) is MORE BRIGHT, x(0) is OFF > 3. when a=3D11 and b=3D01 , x(1) is LESS BRIGHT, x(0) is OFF [..] > I am using CLK_100 (System Clock =96 This clock input is connected to a > 100MHz LVTTL oscillator) as clk. How can I control the clock speed? Just introduce a counter with more than 22-bit width, and change the output only once per counter run (e.g. if counter =3D 0). I know no board that allows to reduce clock externaly in that bandwith and I don't think the dll of virtex 4 allows a clock reduction to 2E06. bye ThomasArticle: 136127
Hi Is there a way to increase performance of Altera functional simulation models? Specifically, I am using FFT core in our project and this is the bottleneck of simulation speed, which I am not surprised to see, given that VHO model is hundred of thousand lines of technology mapped code consisting of Altera library primitives. Using Verilog *.VO does not give much improvement. Moreover, FFT core simulation performance behaves in weird fashion - until core is feed in with first block of samples sim speed is quite good, then when FFT processing starts it slows down (as expected). But then simulation speed does not improve in idle times between processing of consecutive FFT symbols => when FFT core is idle. Regards MichalArticle: 136128
On Sun, 2 Nov 2008 19:37:41 -0800 (PST), subbu instru <gsreddyeee@gmail.com> wrote: > >hello brian, >thank u for given ur valid solution, but still iam getting same error. >plese help me with another good solution. You did remember to delete both std_logic_unsigned and std_logic_arith, didn't you? - BrianArticle: 136129
Brian Drummond wrote: >> hello brian, >> thank u for given ur valid solution, but still iam getting same error. >> plese help me with another good solution. > You did remember to delete both std_logic_unsigned and std_logic_arith, > didn't you? Maybe it's because the code he posted doesn't have a line 84. The code he posted doesn't have a "/=" operator in there either, and that's what the HDL parser is complaining about. So I'm guessing the code he posted has nothing do to with the error message he posted. Maybe he's editing the wrong file or something? Besides, even though std_logic_arith and std_logic_unsigned suck and should be avoided, they should work fine in this case, since he wrote it exactly as Xilinx does in their appnotes. :) cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 136130
> If I understand correctly we can't use ODT for the address/control > signals on the DDR2 side > because DDR2 only supports ODT on data-related signals. Yes, this is the case. ODT is for DQ/DQS/DM signals only. As I've said, I would recommend a 50R terminator to Vtt for address and control signals at the memory end. I wouldn't recommend you leave these nets un-terminated no matter how slow you are running because this will cause the amplitude of the signal to increase massively and be outside the spec for the memory. Also, even when you are running at slow clock rates you have to bear in mind that the edges are quite fast and without termination you can get overshoot outside the absolute maximum pin voltage for the device. > For your interface, did you use the Xilinx Memory Interface generator, > or do your own interface > by hand? We went for a custom solution because the MIG controller was too restrictive at the time. That was about 2 years ago now so the MIG controller has probably moved on a fair bit since then. One big problem we had with MIG was getting the read data capture to work properly because we had quite a wide bus (32 bits) and Xilinx's solution of delaying the DQS with LUTs was tricky with a wide fanout (and the data width of 32 bits wasn't supported in MIG at the time). I would say that if it is possible to get MIG working with your design constraints then I would strongly recommend you go down that route. This is because the MIG design has had a hell of a lot of testing both by Xilinx and the user community, and it is the quickest path the a stable, reliable solution. > Also, may I ask how far away your DDR2 ICs were from your FPGA, and if > there was only > a single IC per interface or multiple ICs? We had two 16bit wide components. they were placed within about an inch of the FPGA. The longest trace length was about 3 inches.Article: 136131
On Nov 2, 3:52=A0pm, "Alessandro" <apo...@email.it> wrote: > Hi! > > I'm using blockram which is initialized from a .coe file. > > I need to often change the initialization data, and every time I have to = go > through the IP core manager and rebuild the component. > > On my computer at home, furthermore, I'm unable to run the IP manager due= to > a lack of ram (512MB) which makes the stupid java machine unable to start= . > > Is there a way to update the blockram content directly? Browsing the sour= ce > file, I found this line: > c_init_file_name =3D> "mem_text.mif", > and opening the .mif file resulted in a clearly readable ascii file with > binary rapresentation of data, for example "00011100". > > Unfortunately, modifying this file does not change blockram content on ne= xt > recompile, even after a cleanup of the project files. > > Any hint? > > Ciao and thanks in advance > Alessandro I think the .mif file is only used for simulation. You could very painfully use the INIT parameter of the instantiated memory with lots of lines of 256-bit hex constants placed right in your source code. Depending on the organization of your memory, this can require shuffling the bits around to match the initialization parameter. I've seen this done with a Perl script to generate INIT values for PicoBlaze. It might not be too bad if your RAM uses only one block RAM primitive in its natural width. Regards, GaborArticle: 136132
On 31 Okt., 13:58, axr0284 <axr0...@yahoo.com> wrote: > 1) If my module detects an address parity error but bit 8 in the > command register used to turn on system error signaling is set to 0, > does my system > a) ignore the command > b) Responds normally ignoring parity checking > c) Takes possession of the request by asserting DEVSEL and then sends > back a target abort. > The PCI spec is not too clear about this particular case. Actually it is very clear. Section 3.8.2.2 in Revision 2.1 of the spec states: "A selected agent that detects an address parity error should do one of the following: claim the cycle and terminate as though the address was correct, claim the cycle and terminate with Target-Abort, or not claim the cycle and let it terminate the Master-Abort." So you have the choice of a), b) and c). I do not have a newer version of the spec, maybe it became more restrictive. I still believe that b) is stupid, because you do not even know whether you should perform a read or a write access. Kolja SulimmaArticle: 136133
On Nov 2, 4:04=A0am, n...@puntnl.niks (Nico Coesel) wrote: [snip] > >Have you looked into running slower than 125 mhz (with the dll disabled)= ? =A0I > >want to do this, at probably around 33mhz, but I'm having trouble gettin= g > >any information about it: =A0namely can I do it and will it work? =A0Jus= t > >wondering if you knew anything about that. > > The datasheet specifies a minimum operating frequency. But whats the > use of DDR2 when using it at lower speeds? Perhaps DDR or SDRAM is a > better choice in such situations. > > -- > Programmeren in Almere? > E-mail naar nico@nctdevpuntnl (punt=3D.) The best reason for DDR2 is small chip size, low price (sweet spot in price per bit) and high bit density. Single data rate chips are bulky and expensive if you want 1 Gbit or more (i.e. multiple chips vs 1 DDR2). DDR 1 uses more power, can be even harder to use, and still has a minimum operating frequency requirement. That being said, if you don't need that much memory, a single-rate mobile SDRAM or even DDR mobile SDRAM will reduce your interface parts count.Article: 136134
In article <d7f10746-01b5-42bc-b472-7950aaa744b2@b31g2000prf.googlegroups.com>,
mikel <mikel262@gmail.com> wrote:
>Hi
>Is there a way to increase performance of Altera functional simulation
>models? Specifically, I am using FFT core in our project and this is
>the bottleneck of simulation speed, which I am not surprised to see,
>given that VHO model is hundred of thousand lines of technology mapped
>code consisting of Altera library primitives. Using Verilog *.VO does
>not give much improvement.
>
>Moreover, FFT core simulation performance behaves in weird fashion -
>until core is feed in with first block of samples sim speed is quite
>good, then when FFT processing starts it slows down (as expected). But
>then simulation speed does not improve in idle times between
>processing of consecutive FFT symbols => when FFT core is idle.
>
>Regards
>Michal
Write a simple model to use in place of their model. Use their model only
for final cycle-accurate checkout. I'm doing this for their altmemphy-based
memory controllers.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 136135if you want to change the bram content in your bitfile you can use "data2mem". this can be done without a recompile and changes the bitfile only. if you want to change the bram content for simulation, try a script for the INIT generics. take a look at the opencores plasma cpu project, there is a makefile included, which generates a "filled" bram vhdl instance. ciao heiko Alessandro schrieb: > Hi! > > I'm using blockram which is initialized from a .coe file. > > I need to often change the initialization data, and every time I have to go > through the IP core manager and rebuild the component. > > On my computer at home, furthermore, I'm unable to run the IP manager due to > a lack of ram (512MB) which makes the stupid java machine unable to start. > > Is there a way to update the blockram content directly? Browsing the source > file, I found this line: > c_init_file_name => "mem_text.mif", > and opening the .mif file resulted in a clearly readable ascii file with > binary rapresentation of data, for example "00011100". > > Unfortunately, modifying this file does not change blockram content on next > recompile, even after a cleanup of the project files. > > Any hint? > > Ciao and thanks in advance > Alessandro > > From rgaddi@technologyhighland.com Mon Nov 03 09:05:25 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!newshub.sdsu.edu!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 03 Nov 2008 11:05:22 -0600 Date: Mon, 3 Nov 2008 09:05:25 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: requesting solution for error:HDLParsers:810 Message-Id: <20081103090525.90141e36.rgaddi@technologyhighland.com> References: <616e3cfa-65aa-4429-b60a-9e92b0b41465@p10g2000prf.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 29 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-AOmSQiza7x/Rcd/8Cpz8ndr1snApybQZj2cnnvlBC3l9u8G6N1pCT53Eukp/FnvbmhKwxLGtNsSMZ4g!7ZArQjN3ORM2nCnJZKLflRLsYEh1174ilgORIfHqVXy/KcDQtabjM882LSwSxrZnGRE5F18CCbAr!TYmVTI+iE48x7SWsoXk= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:149010 X-Received-Date: Mon, 03 Nov 2008 12:05:23 EST (flpi142.ffdc.sbc.com) On Sun, 2 Nov 2008 08:00:30 -0800 (PST) subbu instru <gsreddyeee@gmail.com> wrote: > [snip] > ERROR:HDLParsers:810 - "G:/subbu/model/addition/additest.vhw" Line > 84. /= has two possible definitions in this scope. > Parsing "additest_beh.prj": 0.28 > > [snip] > > entity adder1 is > Port ( clock : in STD_LOGIC; > reset : in STD_LOGIC; > A : in STD_LOGIC_VECTOR (8 downto 0); > B : in STD_LOGIC_VECTOR (8 downto 0); > SUM : out STD_LOGIC_VECTOR (8 downto 0)); > end adder1; > > [snip] Oversnipping along that branch keeps me from replying directly to the message, but I think Sean's got the right idea. I'm going to go out on a limb here and guess that code you posted is actually in a file called "adder1.vhd" and that "additest.vhw" is an entirely different file, with entirely different problems, probably on or near line 84. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 136136
On Nov 3, 8:35=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 31 Okt., 13:58, axr0284 <axr0...@yahoo.com> wrote: > > > 1) If my module detects an address parity error but bit 8 in the > > command register used to turn on system error signaling is set to 0, > > does my system > > a) ignore the command > > b) Responds normally ignoring parity checking > > c) Takes possession of the request by asserting DEVSEL and then sends > > back a target abort. > > The PCI spec is not too clear about this particular case. > > Actually it is very clear. Section 3.8.2.2 in Revision 2.1 of the spec > states: > "A selected agent that detects an address parity error should do one > of the following: claim the cycle and terminate as though the address > was correct, claim the cycle and terminate with Target-Abort, or not > claim the cycle and let it terminate the Master-Abort." > > So you have the choice of a), b) and c). > I do not have a newer version of the spec, maybe it became more > restrictive. > I still believe that b) is stupid, because you do not even know > whether you should perform a read or a write access. > > Kolja Sulimma Thanks for the answer. I've decided to go with Target Abort on that one since on my implementation there is only 1 master and 1 slave on the bus. AmishArticle: 136137
Gabor wrote: > I think the .mif file is only used for simulation. You could very > painfully use the INIT parameter of the instantiated memory with lots of > lines of > 256-bit hex constants Thanks to both of you for your replies. It is 16KBytes of rom image for a processor... sounds very painful :-) You mean that the file and/or format in which the ip manager certainly stores this information into one of the component's files is unknown? Ciao! AlessandroArticle: 136138
I hope to get your feedback of what you think of integrating IAR EWARM (probably the same for EWAVR) with the hardware development scene. All our hardware design tools have Tcl scripting support for batching. I think it would be great to have the IAR simulator communicate with our FPGA simulator ( in our case ModelSim ) . This way we can make nightly builds possible and make tests with the ARM and the FPGA, resulting in better quality and early detection of faults. The easiest way to integrate with multiple other environments is to make a macro available in the debugger to execute an TclScript. To make it more useful i would like to set an memory range (address of the FPGA) like for example 0x40000000-0x60000000 and all memory access in this range should be handled with the Tcl script. This tcl script returns an value on read. or just voids on a write. Please let me know what you think, to work on the idea so we can make a sollid feature request @ IAR. Best regards, AllardArticle: 136139
Hi, I want to learn Nios with its examples: hello. Although the environment is correct, see below: SOPC_KIT_NIOS2=C:\altera\72\quartus\nios2eds I have check it both on control panel and cmd window. The following error message apperes. I can see both app_rules.mk and gnu_rules.mk exist at the build directory. What is wrong with that? Thanks in advance. --------------------------------------------------------------------------------------------- **** Build of configuration Debug for project hello_world_2 **** make -s all includes make: /bin/sh.exe: Command not found make: /bin/sh.exe: Command not found make: /bin/sh.exe: Command not found make: /bin/sh.exe: Command not found make: /bin/sh.exe: Command not found C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: 153: /components/altera_hal/build/gnu_rules.mk: No such file or directory C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: 157: /components/altera_hal/build/gtf_rules.mk: No such file or directory make: *** No rule to make target `/components/altera_hal/build/ gtf_rules.mk'. Stop. Build completed in 2.637 secondsArticle: 136140
You dont have make installed. But i see Windows and Linux lines in your question. This riddles me... On 2008-11-03 22:00:03 +0100, fl <rxjwg98@gmail.com> said: > Hi, > I want to learn Nios with its examples: hello. Although the > environment is correct, see below: > > SOPC_KIT_NIOS2=C:\altera\72\quartus\nios2eds > > I have check it both on control panel and cmd window. > > The following error message apperes. I can see both app_rules.mk and > gnu_rules.mk exist at the build directory. What is wrong with that? > Thanks in advance. > > > > --------------------------------------------------------------------------------------------- **** > > Build of configuration Debug for project hello_world_2 **** > > make -s all includes > make: /bin/sh.exe: Command not found > make: /bin/sh.exe: Command not found > make: /bin/sh.exe: Command not found > make: /bin/sh.exe: Command not found > make: /bin/sh.exe: Command not found > C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: > 153: /components/altera_hal/build/gnu_rules.mk: No such file or > directory > C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: > 157: /components/altera_hal/build/gtf_rules.mk: No such file or > directory > make: *** No rule to make target `/components/altera_hal/build/ > gtf_rules.mk'. Stop. > Build completed in 2.637 secondsArticle: 136141
On Nov 3, 4:29=A0pm, Allard <All...@unknownposter.com> wrote: > You dont have make installed. > > But i see Windows and Linux lines in your question. This riddles me... > > On 2008-11-03 22:00:03 +0100, fl <rxjw...@gmail.com> said: > > > > > > > Hi, > > I want to learn Nios with its examples: hello. Although the > > environment is correct, see below: > > > SOPC_KIT_NIOS2=3DC:\altera\72\quartus\nios2eds > > > I have check it both on control panel and cmd window. > > > The following error message apperes. I can see both app_rules.mk and > > gnu_rules.mk exist at the build directory. What is wrong with that? > > Thanks in advance. > > > -----------------------------------------------------------------------= ----=AD------------------ > **** > > > Build of configuration Debug for project hello_world_2 **** > > > make -s all includes > > make: /bin/sh.exe: Command not found > > make: /bin/sh.exe: Command not found > > make: /bin/sh.exe: Command not found > > make: /bin/sh.exe: Command not found > > make: /bin/sh.exe: Command not found > > C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: > > 153: /components/altera_hal/build/gnu_rules.mk: No such file or > > directory > > C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: > > 157: /components/altera_hal/build/gtf_rules.mk: No such file or > > directory > > make: *** No rule to make target `/components/altera_hal/build/ > > gtf_rules.mk'. =A0Stop. > > Build completed in 2.637 seconds- Hide quoted text - > > - Show quoted text - At the command line, the system (Vista) do not recognize "make" input. Where does "make" come from? Vista? Or, it comes with Quartus? ThanksArticle: 136142
Brian Drummond wrote: > I suspect something obscure in the logic you didn't post is causing it > to be simplified; therefore the other block appears redundant. The code in question is a video controller, and the offending variable/signal is simply a pipeline delay for one of the signals. In fact, the controller has a number of pipeline delays and it would appear that a *pair* of them were being (incorrectly) optimised out. Anyway, I'm not going to defiantly claim there is definitely nothing wrong with my code, so I'll endeavour to put together a small sample project and see if I can't reproduce the problem. And in answer to other threads, the code simulates correctly, and works exactly as expected on Altera silicon. There's really nothing complicated in this scenario, believe me - a couple of counters and some pipeline shift registers. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136143
fl wrote: > At the command line, the system (Vista) do not recognize "make" input. > Where does "make" come from? Vista? Or, it comes with Quartus? Thanks You're better off using the NIOS IDE when starting out, as the environment is "shrink-wrapped" and you won't have to worry about makefiles etc. But to answer your question, "make" should be part of the NIOS tools distribution. You *do* have the NIOS tools installed, right? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136144
Hello Guys, I am trying to move a current project files that contain PCI Xilinx IP Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the project. The ISE 7.x does not have "export source" function. Also, I have tried to move the following files: (.v , .xco and .ucf) and have created a new project with the same target and same name in ISE 10.1 and started adding the source files (.v , .xco and .ucf). That allowed me to synthesize the project successully but did not allow me to implement the design. It fails from the first step "translate" ! and lists the following log: Resolving constraint associations... Checking Constraint Associations... ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>" LOC = "T8" |> [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 |> [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ..... and alot of similar error messages (ERROR:ConstraintSystem:59 ) I have tried also to do "clean up project" but that did not solve the p[roblem. So what could be the thing that I am missing?Article: 136145
On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote: > Hello Guys, > > I am trying to move a current project files that contain PCI Xilinx IP > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the > project. The ISE 7.x does not have "export source" function. Also, I > have tried to move the following files: (.v , .xco and .ucf) and have > created a new project with the same target and same name in ISE 10.1 > and started adding the source files (.v , .xco and .ucf). That allowed > me to synthesize the project successully but did not allow me to > implement the design. It fails from the first step "translate" ! and > lists the following log: > Why are you making it so hard? Just make a copy of the -entire- ISE-7.1 project (sub-directories and all) and open the project with ISE-10.1 ISE will convert is for you. AlexArticle: 136146
On Nov 3, 6:43=A0pm, Mark McDougall <ma...@vl.com.au> wrote: > fl wrote: > > At the command line, the system (Vista) do not recognize "make" input. > > Where does "make" come from? Vista? Or, it comes with Quartus? Thanks > > You're better off using the NIOS IDE when starting out, as the environmen= t > is "shrink-wrapped" and you won't have to worry about makefiles etc. > > But to answer your question, "make" should be part of the NIOS tools > distribution. You *do* have the NIOS tools installed, right? > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Hi, I do use Nios IDE. The above message is from the IDE. I want to know what is wrong with the IDE. Thanks.Article: 136147
On Tue, 04 Nov 2008 10:38:36 +1100, Mark McDougall <markm@vl.com.au> wrote: >Brian Drummond wrote: > >> I suspect something obscure in the logic you didn't post is causing it >> to be simplified; therefore the other block appears redundant. > >The code in question is a video controller, and the offending >variable/signal is simply a pipeline delay for one of the signals. In >fact, the controller has a number of pipeline delays and it would appear >that a *pair* of them were being (incorrectly) optimised out. aaah... >Anyway, I'm not going to defiantly claim there is definitely nothing wrong >with my code, so I'll endeavour to put together a small sample project and >see if I can't reproduce the problem. ... and I have seen *some* evidence that there *may* be a problem with pipeline delays implemented as variables (actually a variable array, to easily control the length); or the transition between signals and such delays. About a year ago, on XST 7.1. It manifested as a cycle difference between the length of the pipeline in simulation, and the same pipeline in practice. I didn't have time to dig down properly and locate the problem; it's still on the ToDo list. Hence the cautious language; I regard it as most probably something dumb on my part unless I can clearly point to XST (as with signals in procedures obeying variable assignment scheduling). So despite the Doubting Thomases (e.g. me), there's no need to question your own sanity. You might be on to something worth reporting. - BrianArticle: 136148
On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote: > > > Hello Guys, > > > I am trying to move a current project files that contain PCI Xilinx IP > > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the > > project. The ISE 7.x does not have "export source" function. Also, I > > have tried to move the following files: (.v , .xco and .ucf) and have > > created a new project with the same target and same name in ISE 10.1 > > and started adding the source files (.v , .xco and .ucf). That allowed > > me to synthesize the project successully but did not allow me to > > implement the design. It fails from the first step "translate" ! and > > lists the following log: > > Why are you making it so hard? =A0Just make a copy of the -entire- > ISE-7.1 project (sub-directories and all) and open the project with > ISE-10.1 > > ISE will convert is for you. > > Alex Hello Alex, Thanks for your reply... I have tried that also and ISE asked me to convert it and make automatically a backupfile of the old one but ..... unfortunately I end up with the same errors... I have to emphasis that there is an IP core used in the project. so maybe I have to set up the ISE 10.1 to recognize the IPcores available in the other station were ISE7.1 resides. So probably there is a procedure I need to follow or so? Any clues :(Article: 136149
Brian Drummond wrote: > > ... and I have seen *some* evidence that there *may* be a problem with > pipeline delays implemented as variables (actually a variable array, to > easily control the length); or the transition between signals and such > delays. About a year ago, on XST 7.1. > > It manifested as a cycle difference between the length of the pipeline > in simulation, and the same pipeline in practice. > I saw a similar bug in XST 9.1 (fixed in 9.2), that would drop (add?) a pipeline stage on inferred memories under certain conditions. I never boiled this down to a testcase, as the problem went away in XST 9.2, and I ended up using Synplify on that job anyhow due to other problems with XST. XST attempts to push extra register stages into the BRAM by enabling the output pipeline register; under certain conditions, XST would lose track of what it was doing, and wire up the BRAM incorrectly. I saw this on a pipelined inferred ROM, where the synthesized circuit was off by one cycle from the simulation. I forget the exact details, but XST would either push the BRAM address register input back one stage without enabling the BRAM data pipeline register; or, enable the register but connect one BRAM address port to the original address, the other to the earlier address stage, and then wire the data up to the wrong output port. ( Whichever one it was showed up clearly as a weird connection to the BRAM in the schematic viewer. ) Brian
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