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On Feb 3, 2:38=A0pm, Simon <goo...@gornall.net> wrote: > well, this is all very nice, but more importantly, when are they going - to actually start delivering these things, and how much will they - cost ? - - I can't really believe they haven't *got* that information, so why the - staged release of info ? Maybe they don't yet have yield info?. No price point, and 2H 2009 timelines, all suggest they have first silicon only. Even MHz specs are hard to find... Other companies have stock at Digikey when they do Product announcements/press releases... -jgArticle: 137951
Hi, I implemented an Aurora link layer using EDK.Now I am concerned about reliability and want to implement a 64-Bit or 32-Bit Hamming Code to enable error detection and correction. Now I am wondering if that makes sense anyway, because if there are bit errors the 8B/10B coding featured in Aurora would dismiss erroneous data words anyway and the Hamming Code would not work. Please correct me if i'm wrong. So what means do I actually have to implement a fail-safe connection via Aurora? Thanks in advance, SaulArticle: 137952
http://www.eetimes.com/showArticle.jhtml;jsessionid=N5KULYMEMNGWUQSNDLOSKH0CJUNN2JVN?articleID=213000271 "One Spartan-6 FPGA, an LX16 device, is already sampling..." "The Spartan-6 family is priced at between about $3 and $54 in high volume of 10,000 units..." All I could find. Luiz CarlosArticle: 137953
Nathan Bialke wrote: > Hello, > > In case anyone hasn't already seen, Xilinx has some preliminary > information about Virtex-6 and Spartan-6 online here - > http://www.xilinx.com/products/v6s6.htm . > > I do have a question about Virtex-6 and it's one LUT6/two flip-flop > architecture. I'm struggling to think of why a user would have any use > for that second flip-flop. It seems to me that the second flip-flop > only has use when the LUT6 is split into two LUT5's. However, the > family overview indicates that a dual-LUT5 has the same restriction as > in Virtex-5 - the inputs to the dual-LUT5s have to be the same. I know > in my designs I don't tend to get many LUT5s synthesized, so I'm not > sure how often that actually happens. The only other case I can even > think of is to use the second flip-flop as solely a storage element, > but without the ability to drive the clock enable input of the flop by > some sort of combinational signal (ie, an address decode) without > "spending" the associated LUT6, it's use seems very limited. > > I am very cognizant of the fact that the people here and at Xilinx are > smarter than me. So, I figured that I'd give them a chance to explain > the design choice. I'm always interested in ways to use FPGA resources > more effectively. > > Thanks! > Perhaps it is something to do with Altera having used a larger LUT connected to two FF's for some time now (since the Stratix II, but not on the Cyclones). Altera's is a bit more advanced (8-input LUT that can be split in many ways, but still with a maximum full LUT of 6 inputs), but it sounds a little "me too" from Xilinx. Of course, if it really does give faster or more compact designs, then "me too" is the right move!Article: 137954
HT-Lab wrote: > > I would suggest you also check out the excellent Leon core (Sparc V8 in > VHDL). I just re-synthesised an old leon2.3.7 version and it fits easily in > a 3S500E which you can find on most low-cost development boards. > > http://en.wikipedia.org/wiki/LEON > > Hans > www.ht-lab.com > Thank you Hans! I will take a look at this. Best Regards GMArticle: 137955
> >But the answer of your question is I don't know if there is a way to >disable these warnings :) > >--enes > In the ISE 10.1 you can filter these messages (and any others) if it causes you pain .. Go to menu 'Edit/Message Filters' in the ISE after a build and add the message(s) that you wish to suppress. Cheers Peter.Article: 137956
On Feb 2, 3:49=A0pm, "kristian" <kri...@gmx.de> wrote: > >kristian <kri...@gmx.de> wrote: > > >> I'm implementing a autocorrelation function using a fft and ifft hard > core > >> (v6.0) on a Virtex5. When starting the fft, I see at the output that > the > >> result is reversed in the frequency domain. > > >If you are feeding the result of fft into ifft, possibly with some > >frequency domain filtering, it is much more efficient that way. > > >If not, there should be cores that generate in the more usual order. > > >-- glen > > hi glen, > > the ifft expects the values in normal order. the only way is to save the > values from the fft in ram. is this normal that the fft core from xilinx > has reversed output data? > > Regards, > kris Kris, No idea about the details of the Xilinx core, but if you have real valued input data and complex output data, you can expect that the output (if you reverse the output samples, with the DC value at the middle) is the negative complex conjugate (see Wikipedia or a standard textbook). That means you could just swap the real and imaginary output, assuming it's a real bug that you want to hack up a fix for. Alternatively, the behaviour you describe for a simple sinusoid could be correct, since you didn't specify the start phase. A sinusoid that's off by 180 degrees (pi radians) will have its value (dirac fft coeffs) multiplied by exp(i*pi) =3D -1. - KennArticle: 137957
Guy_FPGA pisze: > Hi Adam... > > I am not using flash for the nios program- all the SW is located at an > internal ram.... > > :) > > Guy So you have to only update mif files thru compilation :) AdamArticle: 137958
Hi, I'm currently playing with a Terasic DE1 (aka Altera Cyclone II Starter Board), and looking to attach a little external hardware. Specifically, a PIC microcontroller, 40MHz clock oscillator and a couple of TTL buffers. In all likelihood, an external 5V supply will be running the TTL; the PIC and oscillator will (ideally) be powered by the DE1. Both expansion ports provide +5V and +3.3V from the DE1. Does anyone know what the power ratings on these outputs are? I've checked the Reference Manual, which contains a ton of pin-assignment tables, but nothing on how much power can be safely leached from the board via the expansion ports. Thanks, -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/Article: 137959
"Nathan Bialke": > In case anyone hasn't already seen, Xilinx has some preliminary > information about Virtex-6 and Spartan-6 online here - > http://www.xilinx.com/products/v6s6.htm . Ok, and what's the real difference between virtex6 and spartan6? The availability of TBUFs, again? What I don't get with spartan3 is why they didn't put some MUX logic into the switch matrices. I hate spending much logic (and specially logic-levels!) on really nothing but a bus. Gruss Jan BrunsArticle: 137960
On 3 Feb, 13:29, Philip Pemberton <usene...@philpem.me.uk> wrote: > Hi, > I'm currently playing with a Terasic DE1 (aka Altera Cyclone II Starter > Board), and looking to attach a little external hardware. Specifically, a > PIC microcontroller, 40MHz clock oscillator and a couple of TTL buffers. > In all likelihood, an external 5V supply will be running the TTL; the PIC > and oscillator will (ideally) be powered by the DE1. > > Both expansion ports provide +5V and +3.3V from the DE1. Does anyone know > what the power ratings on these outputs are? > > I've checked the Reference Manual, which contains a ton of pin-assignment > tables, but nothing on how much power can be safely leached from the > board via the expansion ports. > > Thanks, > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ It's impossible to specify that for the 3.3V supply, as it will depend on how much current is used by the FPGA. You will have to see how much current your application takes and then look at the regulator spec. to see how much more is available. LeonArticle: 137961
On 3 f=E9v, 08:36, "Jan Bruns" <testzugang_janbr...@arcor.de> wrote: > "Nathan Bialke": > > > In case anyone hasn't already seen, Xilinx has some preliminary > > information about Virtex-6 and Spartan-6 online here - > >http://www.xilinx.com/products/v6s6.htm. > > Ok, and what's the real difference between virtex6 and spartan6? > The availability of TBUFs, again? > > What I don't get with spartan3 is why they didn't put > some MUX logic into the switch matrices. I hate spending > much logic (and specially logic-levels!) on really nothing > but a bus. > > Gruss > > Jan Bruns - Virtex 6 has a different DSP Block (DSP48E), with a 25x18 multiplier instead of a 18x18 multiplier as in the Spartan-6 (DSP48A) - Faster transceivers in Virtex-6 - 36kbit blockram (V6) instead of 18 kbit block ram (S6) - System monitor in Virtex-6 And I suppose that the Virtex-6 will eventually come with PowerPcs embedded in them and also they're probably much faster than Spartan-6.Article: 137962
On Feb 3, 1:04=A0pm, oen_br <oen_no_s...@yahoo.com.br> wrote: > http://www.eetimes.com/showArticle.jhtml;jsessionid=3DN5KULYMEMNGWUQSND..= . > > "One Spartan-6 FPGA, an LX16 device, is already sampling..." > "The Spartan-6 family is priced at between about $3 and $54 in high > volume of 10,000 units..." > > All I could find. > > Luiz Carlos Hm. if that pricing is correct (but seems to come directly from Xilinx!) then it pretty nice (low) from 1.5$ down to 0.5$ per 1K LUT (from smallest to largest device) but.. it seems that even Spartan-3A family isnt fully shipping, there is NO STOCK of any of the newer packages offerings at all, 0 zero stock all distributors. Of course the cheaper package is the one that is not available. AnttiArticle: 137963
On Feb 3, 7:37=A0am, kennheinr...@sympatico.ca wrote: > On Feb 2, 3:49=A0pm, "kristian" <kri...@gmx.de> wrote: > > > > > >kristian <kri...@gmx.de> wrote: > > > >> I'm implementing a autocorrelation function using a fft and ifft har= d > > core > > >> (v6.0) on a Virtex5. When starting the fft, I see at the output that > > the > > >> result is reversed in the frequency domain. > > > >If you are feeding the result of fft into ifft, possibly with some > > >frequency domain filtering, it is much more efficient that way. > > > >If not, there should be cores that generate in the more usual order. > > > >-- glen > > > hi glen, > > > the ifft expects the values in normal order. the only way is to save th= e > > values from the fft in ram. is this normal that the fft core from xilin= x > > has reversed output data? > > > Regards, > > kris > > Kris, > > No idea about the details of the Xilinx core, but if you have real > valued input data and complex output data, you can expect that the > output (if you reverse the output samples, with the DC value at the > middle) is the negative complex conjugate (see Wikipedia or a standard > textbook). That means you could just swap the real and imaginary > output, assuming it's a real bug that you want to hack up a fix for. Mental misfire... negative complex conjugate is just inverting the real part; no swap required. > > Alternatively, the behaviour you describe for a simple sinusoid could > be correct, since you didn't specify the start phase. A sinusoid > that's off by 180 degrees (pi radians) will have its value (dirac fft > coeffs) multiplied by exp(i*pi) =3D -1. > > =A0- KennArticle: 137964
I'm surprised that the Spartan-6 integrated memory controller does not support
DIMMs. Also surprised that there are no integrated memory controllers in
Virtex-6.
Note the Virtex-6 Select-IO voltage range: only up to 2.5V! 2.5V is the
new 5V...
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 137965
On 3 f=E9v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
> I'm surprised that the Spartan-6 integrated memory controller does not su=
pport
> DIMMs. =A0Also surprised that there are no integrated memory controllers =
in
> Virtex-6.
>
> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! =A02.5V is th=
e
> new 5V...
3.3V is the new 5V you might say
>
> --
> /* =A0jhal...@world.std.com AB1GO */ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0/* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=3D80;q+p-80;p-=3D2*a[p])for(z=3D9;z--;)q=
=3D3&(r=3Dtime(0)
> +r*57)/7,q=3Dq?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?=
!a[p+q*2
> ]?a[p+=3Da[p+=3Dq]=3Dq]=3Dq:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," =
#"[!a[q-1]]);}
Article: 137966
In article <410e08bf-0eb4-4096-9755-53cfbedb13f1@k9g2000vbl.googlegroups.com>,
oen_br <oen_no_spam@yahoo.com.br> writes:
|> http://www.eetimes.com/showArticle.jhtml;jsessionid=N5KULYMEMNGWUQSNDLOSKH0CJUNN2JVN?articleID=213000271
|>
|> "One Spartan-6 FPGA, an LX16 device, is already sampling..."
|> "The Spartan-6 family is priced at between about $3 and $54 in high
|> volume of 10,000 units..."
According to my experience with Digikey et al., it will then be between $20 and
$300 for a single chip. The Digikey/Avnet/NuHorizon prices are ridiculously
high...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 137967>From previous thread: +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ My first cleanup was to at least reduce the strings to something that I could actually read. The side effect being that the first character of the string got clobbered and that answer will reside in the spagetti code that you pointed out. Meantime its not immediately obvious to me from the testbench: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... I see the "T" getting in, to the datastream, but I haven't found where it got clobbered. I do know the code is a complete mess. The source code is here if anyone is interested: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/source/LOKI_Top.vhd http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/source/ ++++++++++++++++++++++++++++++++++++++++++++++++++++ Ok, so I've been working with the testbench and the actual development board on why my dumb terminal program doesn't get the first character of the message: "Testing 1,2,3..." Here is a good screen capture of the dumb terminal as well as a separate screen showing the testbench run: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap11_missingfirstletter.png After a lot of mucking about, I zeroed in on the actual pin/wire that the message is going out on, and sure enough, there is the first letter "supposedly" going out in Testbench, "T" followed by "e" followed by "s". all exactly as it should be: start bit, 8 bits of data, and a stop bit, timed exactly at 115200 baud. Meantime, the real world is missing the first letter. What am I missing here? Why is the sim and the real world out of sync?Article: 137968
On Tue, 3 Feb 2009 07:31:46 -0800 (PST), jleslie48 wrote: >After a lot of mucking about, I zeroed in on the actual pin/wire that >the message is going out on, >and sure enough, there is the first letter "supposedly" going out in >Testbench, "T" followed by "e" followed >by "s". all exactly as it should be: start bit, 8 bits of data, and a >stop bit, timed exactly at 115200 baud. > >Meantime, the real world is missing the first letter. > >What am I missing here? Why is the sim and the real world out of >sync? I don't have time to look in detail right now, but my first port of call would be to check that you aren't overrunning the transmitter. I can easily imagine a situation in which you write the first character, note that the Tx claims to be ready for a second, so write the second character too soon - and it then overwrites the first character in one of the Tx's internal buffers. A good sanity check for this would be to add a dead-reckoning delay between characters and see if that works. Or just try sending a 1-character message. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137969
In article <d41631f3-74f4-4d1a-b7e3-c601a24cc6da@v39g2000pro.googlegroups.com>,
Benjamin Couillard <benjamin.couillard@gmail.com> wrote:
>On 3 fév, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
>> I'm surprised that the Spartan-6 integrated memory controller does not support
>> DIMMs. Also surprised that there are no integrated memory controllers in
>> Virtex-6.
>>
>> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! 2.5V is the
>> new 5V...
>
>3.3V is the new 5V you might say
No, 3.3V was the old new 5V. The new new 5V is 2.5V. Altera Straitx-IV
also does not support 3.3V I/O.
For recent designs I try to use 1.8V for I/O... there are a number of logic,
clock and peripheral chips which will work at this level, which matches DDR2
RAM power supply.
Not much available for 1.5V yet (for DDR3).
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 137970On Feb 3, 10:37 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Tue, 3 Feb 2009 07:31:46 -0800 (PST), jleslie48 wrote: > >After a lot of mucking about, I zeroed in on the actual pin/wire that > >the message is going out on, > >and sure enough, there is the first letter "supposedly" going out in > >Testbench, "T" followed by "e" followed > >by "s". all exactly as it should be: start bit, 8 bits of data, and a > >stop bit, timed exactly at 115200 baud. > > >Meantime, the real world is missing the first letter. > > >What am I missing here? Why is the sim and the real world out of > >sync? > > I don't have time to look in detail right now, but my first > port of call would be to check that you aren't overrunning > the transmitter. I can easily imagine a situation in which > you write the first character, note that the Tx claims to > be ready for a second, so write the second character too > soon - and it then overwrites the first character in one > of the Tx's internal buffers. > > A good sanity check for this would be to add a dead-reckoning > delay between characters and see if that works. Or just try > sending a 1-character message. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Jonathan, Thanks again for your insight. I like that 1 character test I will do that in two minutes. Meantime, my associate doesn't like the fact that the tx_write_buffer_stb occurs on the same boundary as the update to tx_data_in: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap12_missingfirstletter.png does this sound right? > A good sanity check for this would be to add a dead-reckoning > delay between characters and see if that works. I love this idea but don't know how to implement it. Earlier in this project we agreed to black-box the nasties of the workings of the RS232. This sounds like I have to open that [pandora's] box again.Article: 137971
jleslie48 wrote: > http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... > > I see the "T" getting in, to the datastream, but I haven't found where > it got clobbered. Is the reset pulse lined up ok?Article: 137972
On Tue, 3 Feb 2009 07:50:10 -0800 (PST), jleslie48 wrote: >> >After a lot of mucking about, I zeroed in on the actual pin/wire that >> >the message is going out on, >> >and sure enough, there is the first letter "supposedly" going out in >> >Testbench, "T" followed by "e" followed >> >by "s". all exactly as it should be: start bit, 8 bits of data, and a >> >stop bit, timed exactly at 115200 baud. >> >> >Meantime, the real world is missing the first letter. Sorry, I didn't read that carefully enough the first time. Do I understand correctly that you have examined the serial line output from the UART, and you are seeing the 'T' character - with its start, stop etc - actually going out on the line? If so, then my suggestion about buffer overrun is irrelevant and instead you need to ask why you are not seeing that character. Here are some possibilities: 1) It's going out so soon after you powered-up the FPGA that the real, physical receiver (which, I assume, is a COM port on your PC) has not had time to establish an idle-line level. 2) Ditto, but you have some issue with the modem handshake signals (DSR, RTS etc) so that the COM receiver doesn't think the line is active at that time. 3) Look carefully at the serial line output again: is it REALLY following the protocol? At least 11 bit times of "mark" followed by the transition to "space" at the beginning of the start bit? I don't know if you are using parity, but if so... perhaps there's some initialisation issue and the parity is wrong on the first character? A storage 'scope on the serial line, triggered by the FPGA's configuration DONE signal going true, might yield some insights. Many an experiment has foundered on the reefs of power-up initialisation trouble. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137973
On Tue, 3 Feb 2009 07:50:10 -0800 (PST), jleslie48 wrote: >Meantime, my associate doesn't like the fact that the >tx_write_buffer_stb >occurs on the same boundary as the update to tx_data_in: If there is, in the UART code or anywhere else, a process that is clocked by rising_edge(tx_write_buffer_stb) (or the equivalent with 'event) then you are screwed. If, however, this is a synchronous enable signal and all the UART's activity is clocked by the clk_16_6_MHz signal as it should be, then all is well and you have nothing to worry about on that score. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137974
On Feb 3, 12:35=A0am, "S. Bernstein" <jiffyl...@freenet.de> wrote: > Please correct me if i'm wrong. So what means do I actually have to > implement a fail-safe connection via Aurora? > > Thanks in advance, > Saul It seems to me you should be asking why you want to make a fail-safe connection with Aurora. Aurora is only specified to a BER of 1E-12. Even if you manage to protect the data payload portion of the frames, your frame error rate will be limited by the control (K) characters used by Aurora, which won't be protected. Moreover, the specification tends to assert a hard error (and hence, reinitialize the link) when there is an error in these characters, which is somewhat inconvenient. Further, I'd suggest that Hamming codes are going to be difficult to use with 8b/10b encoding. Remember that a bit error in an 10b character can result in more than one bit error in the corresponding 8b character. As a result, your Hamming code will probably be a lot less effective than you think it'd be. Of course, you can remove 8b/ 10b encoding, but then you're going to have a whole lot of trouble getting Aurora to work. As a practical matter, the question has to be asked - why do you want to do this? If this is an wired connection, there should be no bit errors. If there are bit errors in your system, the system is misconfigured or improperly designed. If this is an optical connection or something fancier, you should know the properties of your channel - most likely, Hamming codes are not nearly the most effective error correction mechanism available to you for even more reasons than I've specified. They may, however, be the cheapest, which definitely counts for something. The route I've considered, but not implemented, for something approximating this is to use an Aurora-like protocol (with all K characters being triplicated) with Reed Solomon encoding being done on the data at the 8b/10b level (using 10 bit symbols). If you'd like more detail, feel free to contact me. - Nathan
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