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I have some questions about how to transmit data between NiosII system and the outside user logic.For example, if I want to use a TSE mac in my niosII system,the nios II can control the TSE mac,but Nios II don't need to get the data from TSE MAC,I only want to get the data from TSE MAC and store them in fifo for later use outside the NiosII system,the NiosII is only for control,but I don't know how to do it in sopcbuilder,can someone give me some advice.Article: 138626
On Mar 2, 5:31=A0am, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > Hal Murray wrote: > > Without that code, you can't tell what sort of device it is so > > you can't hand it off to the right driver to load the right > > FPGA code. =A0(You don't even know there is an FPGA to be loaded.) > > > It might have some default device/manufacturer codes. =A0If so, > > that will work as long as you only have one of them in the system. > > The vendor would just have to allocate unique device-id for each chip > type and use their own vendor-id. If there are many FPGAs my > understanding is that with PCIe and P-to-P connections the topology is > unique and the chips can be identified from the PCI topology. Same > problem applies when there are multiple identical PCIe cards on > the system. It has been a long time since I worked with PCI and have not worked with PCIe at all. Are you saying that when a device is enumerated, the host knows exactly what port of what chip the device is on? I guess if this ID truly is unique and does not change then there is no reason that it couldn't work. Can you work out exactly how much logic would be required in the FPGA? It sounds like you have worked with PCIe quite a bit before. If you can put together a download that can be booted up via a serial flash chip, then this could work to serve the OP's purpose, no? With compression, I expect this chip could be pretty small even for large FPGAs. I know Xilinx has bit stream compression, do the others use it as well? RickArticle: 138627
On Mar 2, 4:41=A0am, knight <krshe...@gmail.com> wrote: > Hi thanks a lot for the reply... > But how can i instantiate an IBUF to get back an ODDR output...??? > won't it require a hardware loopback...???- Hide quoted text - All Xilinx I/O pins are bidirectional input/outputs. If you use an IOBUF (bidirectional output buffer), you can take the output of the ODDR to put it on the output portion of the buffer and use the input portion of the buffer to read it back into the FPGA fabric. I'm not sure any synthesis tools will take a seperately instantiated IBUF and turn it into an IOBUF, but I have no inclination to try. That said, again, Symon is right. You most likely don't want to or need to do this.Article: 138628
On Feb 28, 9:29 am, doug <x...@xx.com> wrote: > google "cordic" > > 'use_real_email' wrote: > > Does anyone have an idea or where i can find information on how can to > > implement a cordic algorithm on an altera cyclone II or cyclone III > > fpga? http://en.wikipedia.org/wiki/CORDIC Study the matlab/octave code towards the end. It works too..... Check the results with the 'angle()' or 'atan2()' commands. Look at figure 5, since this is a common way of using the cordic for FM demod: http://www.linuxjournal.com/article/7505 Study hard!! This is not going to be easy...Article: 138629
On Sun, 01 Mar 2009 10:52:08 -0800 doug <xx@xx.com> wrote: > [snip] > The schematic editor has it good points and its bad points. First of > all, your problem is easy to take care of. On the right hand side of > the screen, under the file list part, there is a choice under a > section labelled: "when you move an object" of either "keep the > connections to other objects" or "break the connections to other > objects." That will fix this issue. However, moving things in > the editor is not easy to do quickly and it is hard to keep neat > schematics as a project grows. It is particularly annoying when > you move something to another sheet. If you use paste, special, > then you can keep the pin names but they will be invisible so > you have to rename them to make them visible. > > Most people here do not use schematics. Using VHDL or verilog > gives them the opportunity to come here and ask how to trick > the system into doing what they want. Getting brams is always > fun. With schematics you miss most of that since, if you want > a bram, you just put one in. Other bad points include the fact that it won't actually let you place bus taps anymore, and that at least in 10.1, if you've got the window floated so that you can use 100% of your screen for your schematic instead of 30%, the Find command (or Ctrl+F if you accidentally hit it) crashes the program, losing all your work. I agree wholeheartedly with one of the earlier posters. I'm not saying there's anything wrong with schematic design entry as a concept, and there very well may be excellent tools for it out there, but ISE Schematic Editor was not meant to be used. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 138630
On Mon, 02 Mar 2009 01:57:58 -0800
Alex Freed <alex_news@mirrow.com> wrote:
> dracosilv wrote:
> >
> > I think I'm going to go with Verilog or VHDL (not 100% sure which
> > yet, but probably VHDL), since the logic seems pretty simple.
>
> I wonder what drives you towards VHDL - not to start a religious war
> here. The same functionality can look like
>
> module BUFF4(input e, input [3:0] I, output [3:0] O);
>
> assign O = (e == 1) ? I : 4'bz;
> endmodule
>
> -Alex.
And in VHDL as:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BUFE4 is
port(
O : out std_logic_vector(3 downto 0);
E : in std_logic;
I : in std_logic_vector(3 downto 0);
);
end BUFE4;
architecture BUFE4_V of BUFE4 is
begin
O <= I when (E = '1') else "ZZZZ";
end BUFE4_V;
What made the original code a little cumbersome was not using vectors,
not language choice.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 138631On Mar 1, 4:27=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > the time goes faster and faster each month :( > so there is less time to write magazine content > still the february issue is released with less > delay then last few issuehttp://groups.google.com/group/antti-brain/files= ?hl=3Den > > Antti I was reading your Brain issue from Jan and I noticed that you used an Actel part on the stamp instead of the XP from Lattice. You said, "The reasons are non technical, the STAMP60 (A3P060 based Stamp) is very low cost FPGA module." Do you find the ProASIC3 is cheaper than the XP from Lattice? I am building a board with a 5k LUT XP part and am getting them for under $10. I guess I didn't look hard at the ProASIC3. I don't recall if it was a package issue or what. I'm curious why you didn't use an XP or XP2 part. The XP2 is available in an 8x8 132 pin BGA if that can work for you. RickArticle: 138632
On Mar 2, 8:32=A0pm, rickman <gnu...@gmail.com> wrote: > On Mar 1, 4:27=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > Hi > > > the time goes faster and faster each month :( > > so there is less time to write magazine content > > still the february issue is released with less > > delay then last few issuehttp://groups.google.com/group/antti-brain/fil= es?hl=3Den > > > Antti > > I was reading your Brain issue from Jan and I noticed that you used an > Actel part on the stamp instead of the XP from Lattice. =A0You said, > "The reasons are non technical, the STAMP60 (A3P060 based Stamp) is > very low cost FPGA module." =A0Do you find the ProASIC3 is cheaper than > the XP from Lattice? =A0I am building a board with a 5k LUT XP part and > am getting them for under $10. =A0I guess I didn't look hard at the > ProASIC3. =A0I don't recall if it was a package issue or what. =A0I'm > curious why you didn't use an XP or XP2 part. =A0The XP2 is available in > an 8x8 132 pin BGA if that can work for you. > > Rick Hi Rick, the the reason for choosing A3P060 first was purely non-technical as simple as overleft stock ;) and yes, i do belive it to be the cheapest Flash FPGA, well it may not be the be best in price/perfomance ratio, but in pure price it is. the A3P060 based stamp module OEM/disti pricing is below 10$ very likely we could not offer Lattice XP2 based modules at sale price below 10$, hm maybe I should talk about it to Lattice tomorrow ;) but... I do have XP2 CS132 samples on my desk, and those will also find their product soon :) AnttiArticle: 138633
On Feb 28, 9:09=A0am, monu...@gmail.com wrote: > Why is xilinx-microblaze interrupt controller foolishly complicated? Because it's part of the Xilinx EDK. -aArticle: 138634
On Mar 2, 5:29 am, chenyong20...@gmail.com wrote: > Hi, > I'm changing from Xilinx to Altera and sometimes confused by Altera > products. Now I'm trying to instantiate PCIE with SOPC Builder. The > spec states there will be an Avalon-MM interface, but I can only find > a TX interface in SOPC. Can anybody help me to understand this TX > interface with Avalon-MM? thanks > > CY Dated March, 2009, so it's probably the most recent: <http:// www.altera.com/literature/ug/ug_pci_express.pdf>Article: 138635
On Mar 2, 7:43 am, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > I have some questions about how to transmit data between NiosII system > and the outside user logic.For example, if I want to use a TSE mac in > my niosII system,the nios II can control the TSE mac,but Nios II don't > need to get the data from TSE MAC,I only want to get the data from TSE > MAC and store them in fifo for later use outside the NiosII system,the > NiosII is only for control,but I don't know how to do it in > sopcbuilder,can someone give me some advice. The best advice I can give you is to learn how to search the web. Google isn't too bad at finding stuff. This is the 3rd hit (out of almost 8000): <www.altera.com/support/examples/nios2/exm-ethernet-acceleration.html> And I have found this web site to be quite useful for NIOS issues: <www.altera.com>Article: 138636
On Feb 28, 9:09 am, monu...@gmail.com wrote: > Why is xilinx-microblaze interrupt controller foolishly complicated? This is USENET, not Yahoo Answers. You don't get points for asking questions.Article: 138637
For those of that don't get our newsletter there two new board products released today. Craignell2 takes the concepts the Craignell1 series but squeezes much more into the DIL40 initial release. FPGAs now up to a XC3S1400A, 128 Flash, and up to 512Mbit SDRAM. It's a very impressive module and one of our best products that we have shown as yet. The second product released is the first release of a new family. Mulldonoch2 takes an industry standard EBX size but with the twist of dual FPGAs instead of a conventional processor. It has plenty of Flash and SDRAM for processor applications. It also has low power and suspend modes so it can wake up due a stimulus like onboard RTC or Ethernet and so on. It's also got a PC104+(PCI) for expansion. Lot's of I/Os on our DIl format headers now enhanced with full power strips and even a settable regulators for voltages that are not there as standard. Details of both of these are in the newsletter www.enterpoint.co.uk. Links to the products from the main website shortly. There are live pages already for these products. URLs are in the newsletter. John Adair Enterpoint Ltd.Article: 138638
On Mar 2, 1:55 pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Mar 2, 8:32 pm, rickman <gnu...@gmail.com> wrote: > > > > > On Mar 1, 4:27 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Hi > > > > the time goes faster and faster each month :( > > > so there is less time to write magazine content > > > still the february issue is released with less > > > delay then last few issuehttp://groups.google.com/group/antti-brain/files?hl=en > > > > Antti > > > I was reading your Brain issue from Jan and I noticed that you used an > > Actel part on the stamp instead of the XP from Lattice. You said, > > "The reasons are non technical, the STAMP60 (A3P060 based Stamp) is > > very low cost FPGA module." Do you find the ProASIC3 is cheaper than > > the XP from Lattice? I am building a board with a 5k LUT XP part and > > am getting them for under $10. I guess I didn't look hard at the > > ProASIC3. I don't recall if it was a package issue or what. I'm > > curious why you didn't use an XP or XP2 part. The XP2 is available in > > an 8x8 132 pin BGA if that can work for you. > > > Rick > > Hi Rick, > > the the reason for choosing A3P060 first was purely non-technical > as simple as overleft stock ;) > > and yes, i do belive it to be the cheapest Flash FPGA, well it may > not be the be best in price/perfomance ratio, but in pure price it is. > > the A3P060 based stamp module OEM/disti pricing is below 10$ > very likely we could not offer Lattice XP2 based modules at sale > price below 10$, hm maybe I should talk about it to Lattice > tomorrow ;) > > but... I do have XP2 CS132 samples on my desk, and those will > also find their product soon :) My current product is rather price sensitive as I had to lock in a price before the hardware was designed, so every dollar saved in manufacturing costs goes into my pockets (after going through the pockets of Uncle Sam)... I could not find a cheaper solution than the XP in the 100 pin TQFP. A lot of the price of the low end FPGAs comes from the testing time which in turn relates to the number of pins. I think when I checked the price on the XP2 smallest part in the cs132 pin package, it was about $4 - $5 more than the XP part. Also, the XP2 requires a 1.2 volt Vcore which is another $0.50 to $1.00 for even a linear or $2.00 or more for a switcher not to mention the board space. But then not all projects can use a package as large as the 100 pin TQFP (I never thought I would call that package "large"). Although, I will say that the board you show with the SiBlue part, the serial flash and the LDO is bigger than a 100 TQFP. Some things left out of your CPU chart that might be useful are; the license terms (pBlaze can not be used in non-X parts) and design size. The LUT count can vary depending on the target family (I think the pBlaze is instantiated X primatives, no?), but it would be nice to have an idea if they are close in size or rather different. BTW, I like your term FCU. I have been trying to find a reasonable name to distinguish FPGA CPUs from others. FCU is unique as long as no one confuses it with a floating point unit. I'm not sure I understand what some of your projects are about, but I have to give you credit for some amazing soldering! It has been a long time since I was able to do that sort of work. RickArticle: 138639
On Mar 2, 4:50=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > For those of that don't get our newsletter there two new board > products released today. ...snip... > Details of both of these are in the newsletterwww.enterpoint.co.uk. > Links to the products from the main website shortly. There are live > pages already for these products. URLs are in the newsletter. > > John Adair > Enterpoint Ltd. When I follow your link as viewed in Google Groups, I get a report of an attack. Reported Attack Site! This web site at us-euro.biz has been reported as an attack site and has been blocked based on your security preferences. Attack sites try to install programs that steal private information, use your computer to attack others, or damage your system. Some attack sites intentionally distribute harmful software, but many are compromised without the knowledge or permission of their owners. Any idea how/why this is happening? RickArticle: 138640
On Feb 27, 2:59=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Feb 24, 4:48=A0pm, Gabor <ga...@alacron.com> wrote: > > > A lot of empty columns in the timing specifications, but > > already errata listed for two devices of the family. > > > Worth a look: > > >http://www.latticesemi.com/corporate/newscenter/newsletters/newsfebru... > > > Regards, > > Gabor > > it seems they even have working silicon :) > well PCIe was already offered in ECP2 > > so Xilinx will be the 3rd company shipping low cost > FPGA with serdes (I assume Arria's are also shipping at the moment) > > Antti This announcement doesn't change the order of low-cost serdes offerings. The ECP2M family has been around for a while now...Article: 138641
Rick I got something similar and something different in a different browser. Typing the address in manually appears ok. It seems the link has somehow been hacked or corrupted. I will try and remove the original post. As far as I can tell our website hasn't been compromised and the machine these are posted from reasonably secure. Apologies to everyone that got the rubbish off the link. John Adair Enterpoint Ltd. On 2 Mar, 21:50, John Adair <g...@enterpoint.co.uk> wrote: > For those of that don't get our newsletter there two new board > products released today. > > Craignell2 takes the concepts the Craignell1 series but squeezes much > more into the DIL40 initial release. FPGAs now up to a XC3S1400A, 128 > Flash, and up to 512Mbit SDRAM. It's a very impressive module and one > of our best products that we have shown as yet. > > The second product released is the first release of a new family. > Mulldonoch2 takes an industry standard EBX size but with the twist of > dual FPGAs instead of a conventional processor. It has plenty of Flash > and SDRAM for processor applications. It also has low power and > suspend modes so it can wake up due a stimulus like onboard RTC or > Ethernet and so on. It's also got a PC104+(PCI) for expansion. Lot's > of I/Os on our DIl format headers now enhanced with full power strips > and even a settable regulators for voltages that are not there as > standard. > > Details of both of these are in the newsletterwww.enterpoint.co.uk. > Links to the products from the main website shortly. There are live > pages already for these products. URLs are in the newsletter. > > John Adair > Enterpoint Ltd.Article: 138642
Rick I got something similar and something different in a different browser. Typing the address in manually appears ok. It seems the link has somehow been hacked or corrupted. I will try and remove the original post. As far as I can tell our website hasn't been compromised and the machine these are posted from reasonably secure. Apologies to everyone that got the rubbish off the link. John Adair Enterpoint Ltd.Article: 138643
Here's the original again without link: Website linked removed is enterpoint dot co dot uk For those of that don't get our newsletter there two new board products released today. Craignell2 takes the concepts the Craignell1 series but squeezes much more into the DIL40 initial release. FPGAs now up to a XC3S1400A, 128 Flash, and up to 512Mbit SDRAM. It's a very impressive module and one of our best products that we have shown as yet. The second product released is the first release of a new family. Mulldonoch2 takes an industry standard EBX size but with the twist of dual FPGAs instead of a conventional processor. It has plenty of Flash and SDRAM for processor applications. It also has low power and suspend modes so it can wake up due a stimulus like onboard RTC or Ethernet and so on. It's also got a PC104+(PCI) for expansion. Lot's of I/Os on our DIl format headers now enhanced with full power strips and even a settable regulators for voltages that are not there as standard. Details of both of these are in the newsletter (Link Removed). Links to the products from the main website shortly. There are live pages already for these products. URLs are in the newsletter. John Adair Enterpoint Ltd.Article: 138644
Vesh wrote: > I am a final year student in electronics engineering and am doing my > final year project in FPGA spartan 3E starter kit. I need to have a > character generator ROM along with VGA controller core. A final year project that consists of a couple of counters and a ROM??? Maybe next year for your Masters thesis you could add a serial port? The really sad thing is that there's dozens if not a hundred freely available examples on the net that do exactly that, and yet you can't even be bothered to search for them yourself... -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 138645
Antti.Lukats@googlemail.com wrote: > On Mar 2, 4:56 am, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote: >> Vesh wrote: >>> I am a final year student in electronics engineering and am doing my >>> final year project in FPGA spartan 3E starter kit. I need to have a >>> character generator ROM along with VGA controller core. Could anyone >>> help me with this. I need to read characters from the character ROM >>> and display them on the VGA monitor. Please help >> You mean you need the ROM image, or the whole character >> generator logic. ROM images are available, but then with some >> graph paper you can make your own. >> >> http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-r-199.pdf >> >> has a design for a display terminal including a character >> generator. It generates NTSC timing, but it shouldn't be >> hard to modify for VGA timing. >> >> -- glen > > Glen > > 5 ***** award to you for the best reply to "please do my homework > begger" question. > > a scanned document from 1976 :) > > great reading... > > Antti > It seems especially appropriate that the file name begins "slac-r"...Article: 138646
On Mar 3, 5:18=A0am, Mark McDougall <ma...@vl.com.au> wrote: > Vesh wrote: > > I am a final year student in electronics engineering and am doing my > > final year project in FPGA spartan 3E starter kit. I need to have a > > character generator ROM along with VGA controller core. > > A final year project that consists of a couple of counters and a ROM??? > Maybe next year for your Masters thesis you could add a serial port? > > The really sad thing is that there's dozens if not a hundred freely > available examples on the net that do exactly that, and yet you can't eve= n > be bothered to search for them yourself... > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Thanks for ur link. No Mark..its just a part of our project named "Wireless Device Manager Using FPGA". Its not that i wasnt bothered to search them myself. I have, but most of them are incomplete especially without the .vhd file for character rom. I have already used VGA graphics controller..n i m just starting this text display. I was looking for faster approach.Article: 138647
Vesh wrote: > Thanks for ur link. No Mark..its just a part of our project named > "Wireless Device Manager Using FPGA". Its not that i wasnt bothered to > search them myself. I have, but most of them are incomplete especially > without the .vhd file for character rom. I have already used VGA > graphics controller..n i m just starting this text display. I was > looking for faster approach. I believe the SOL documentation has images of the generated characters from its generator. Otherwise, graph paper in a pen will do it. -- glenArticle: 138648
On Mar 2, 5:57=A0pm, gabor <ga...@alacron.com> wrote: > On Feb 27, 2:59=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Feb 24, 4:48=A0pm, Gabor <ga...@alacron.com> wrote: > > > > A lot of empty columns in the timing specifications, but > > > already errata listed for two devices of the family. > > > > Worth a look: > > > >http://www.latticesemi.com/corporate/newscenter/newsletters/newsfebru.= .. > > > > Regards, > > > Gabor > > > it seems they even have working silicon :) > > well PCIe was already offered in ECP2 > > > so Xilinx will be the 3rd company shipping low cost > > FPGA with serdes (I assume Arria's are also shipping at the moment) > > > Antti > > This announcement doesn't change the order of low-cost serdes > offerings. =A0The ECP2M family has been around for a while now... Antti knows that. He's just using an opportunity to take a jab at Xilinx. Heck, who doesn't want to do that once in awhile? RickArticle: 138649
rickman wrote: > On Mar 2, 5:31 am, Kim Enkovaara <kim.enkova...@iki.fi> wrote: >> Hal Murray wrote: > It has been a long time since I worked with PCI and have not worked > with PCIe at all. Are you saying that when a device is enumerated, > the host knows exactly what port of what chip the device is on? I I would say this depends on the OS and how it can represent the topology information. Going trough linux PCIe code is on my TODO list, but I haven't got into that yet. But in embedded system with full control of the OS, the enumeration is possible (the OS has to know physical level information about the board). Each PCIe port is behind a virtual PCI bridge (inside the PCIe switch) to emulate traditional PCI architecture. Each of those bridges show one extra level of PCIe hierarchy with one EP or a switch with more virtual bridges. I'm more a hardware guy, but this is my understanding of the PCI/PCIe software interface. Maybe someone here has more experience in writing PCIe enumeration logic to an OS ;) > reason that it couldn't work. Can you work out exactly how much logic > would be required in the FPGA? It sounds like you have worked with > PCIe quite a bit before. If you can put together a download that can I would say that it is so little that it does not matter in 40nm ;) The amount would differ quite much depending on how the interface is done. If it is simple register in conf. space the logic should be very simple because the hardcores usually show traditional CPU bus style interface for configuration cycles that are not decoded by the core itself. Memory mapped interface would require more logic, there most of the logic would be the transaction processing engine, but a simple one is not huge. > be booted up via a serial flash chip, then this could work to serve > the OP's purpose, no? With compression, I expect this chip could be > pretty small even for large FPGAs. I know Xilinx has bit stream > compression, do the others use it as well? One the other hand one huge flash with all the software, FPGA images etc. can be more economic and enables more flexibility. But each application has its own needs, otherwise this thread would have been quite short ;) --Kim
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