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Messages from 136700

Article: 136700
Subject: Re: simulation results is correct but synthesis result is not correct
From: Per <perk@isy.liu.se>
Date: Tue, 2 Dec 2008 10:28:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2008-12-02, J.Ram <jrgodara@gmail.com> wrote:
> On Dec 1, 12:15 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
> wrote:
>> On 1 Dez., 05:45, "J.Ram" <jrgod...@gmail.com> wrote:
>>
>> > Hello,
>> > I have a problem in peice of code.
>>

  Something I always tell my students are to know what they are
  designing. To draw an RTL-level schematic on paper before starting to
  design anything. Then you need to know how to implement the various
  components in the RTL-language. This in the end depends on your
  particular synthesiser, but most synthesiser interpret the RTL-code
  in the same way.

  \Per

Article: 136701
Subject: Re: simulation results is correct but synthesis result is not correct
From: "J.Ram" <jrgodara@gmail.com>
Date: Tue, 2 Dec 2008 02:52:24 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 1, 12:15 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 1 Dez., 05:45, "J.Ram" <jrgod...@gmail.com> wrote:
>
> > Hello,
> > I have a problem in peice of code.
>
> I see that you have a problem, but is more than just a piece.
> Simulation accepts software, synthesis expects hardware description.
> in vhdl you use for registered data transfer always a template in the
> form
>
> process (clk)
>   if rising_edge(Clk) then
>       <synchron change regs>
>   end if
>
> or for asynchronous reset:
>
> process(clk,reset)
>   if reset = active then
>     <reset regs asynchronous>
>   elsif rising_edge(Clk) then
>     <synchron update regs>
>   end if
>
> Your first process does something you propably wouldn't expect, when
> having a rising edge on clk, while reset=0 and ref_clk=1 This behavior
> is not synthesisable for most tools and need to be rewritten if
> needed.
>
> Three questions:
> 1. Why do you name a process, if you don't like to name it properly?
>    (eg. change u1 to registered_counter)
> 2. Why do you write redundant code?
>        a) if reset = 1 or..then...end if; if reset = 1 then...
>        b) if sig_count >= 4 or sig_count >5 then
> 3. Is there a reason to use the variables? Variables are good practice
> for most code but I see no reason in this particular code.
>
> bye Thomas

hello,
thanks for reply , i made some changes in previous code and reflected
below.
simulation is correct in this model, synthesizable but clk is
unconnected in RTL view.
can u suggest different code for same functionality.
i am waiting your reply.
 entity pn_clk is
port(
clk: in std_logic;
ref_clk : in std_logic;
reset : in std_logic;
out_clk : out std_logic)
end entity pn_clk;

architecture behav of pn_clk is
signal sig_count : natural range 0 to 8 := 0;
 begin
u1: process(clk, reset, ref_clk)
variable count : natural range 0 to 8 := 0;
begin
if reset = '1' or ref_clk = '1' then
count := 0;
end if;
if rising_edge(clk) then
if count = 8 then
count := 0;
else
count := count + 1;
end if;
end if;
sig_count <= count;
end process u1;
u2: process(sig_count)
variable clk_var : std_logic := '0';
begin
if sig_count >= 4  then
clk_var := 0;
else
clk_var := 1:
end if;
out_clk <= clk_var;
end process u2;
end behav;

Article: 136702
Subject: Re: reading registers
From: Sean Durkin <news_MONTH@tuxroot.de>
Date: Tue, 02 Dec 2008 14:05:08 +0100
Links: << >>  << T >>  << A >>
uraniumore238@gmail.com wrote:
> Hi guys,
> 
> I have a spartan 3 starter board from digilent. I using a 2 counter
> and then subtracting the two registers and then displaying these
> values on the led screen from lsb to msb (right to left). What kind of
> representation (signed magnitude, two's complement, ones complement)
> is my system displaying the binary value ? I am really confused on
> which technique to use in order to convert it into an integer
> value ...

I'm not sure I understand exactly what you're doing. Only one idea that
might help: usually on this kind of board LEDs are connected so they
light when the IO is set to low. So a lit LED means '0', and '1' turns
it off. Maybe that's all there is to your problem...

HTH,
Sean

-- 
Replace "MONTH" with the three-letter abbreviation of the current month
(simple, eh?).

Article: 136703
Subject: Re: simulation results is correct but synthesis result is not correct
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 2 Dec 2008 05:19:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 2, 5:52=A0am, "J.Ram" <jrgod...@gmail.com> wrote:
> thanks for reply , i made some changes in previous code and reflected
> below.

I see...there were only three syntax errors this time for your posted
code.  Is it so hard to post the code that you actually run through
the tools, or is it that you really don't run the tools thus not
catching the syntax errors?

> simulation is correct in this model, synthesizable but clk is
> unconnected in RTL view.
> can u suggest different code for same functionality.

Synplify didn't recognize your code as being that of a flip flop.  One
clue that you ignored is the following warnings that it produced...

Found combinational loop at count[3] (as well as for bits 2 thru 0).

Refer to the Synplify help under the VHDL Language Support/Sets and
Resets/Asynchronous Sets and Resets for the template that you must
follow.  Then, in addition to fixing the syntax errors, make the
following changes to your code

if reset =3D '1' or ref_clk =3D '1' then
count :=3D 0;
-- end if;
elsif rising_edge(clk) then

> i am waiting your reply.

Kevin Jennings

Article: 136704
Subject: how to read images from a microSD card ?
From: "papppanas" <raluca.florescu@gmail.com>
Date: Tue, 02 Dec 2008 08:07:54 -0600
Links: << >>  << T >>  << A >>
Hello

My problem right now is that I have to program a Spartan3 starter's kit
FPGA to read images from a microSD card (i.e. program the memory adaptor)
and I don't actually know where to start...
Can someone please give me a hint, so that I can start my work?

Thanks in advance,
Raluca 



Article: 136705
Subject: Re: reading registers
From: Gabor <gabor@alacron.com>
Date: Tue, 2 Dec 2008 06:13:35 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 2, 8:05=A0am, Sean Durkin <news_MO...@tuxroot.de> wrote:
> uraniumore...@gmail.com wrote:
> > Hi guys,
>
> > I have a spartan 3 starter board from digilent. I using a 2 counter
> > and then subtracting the two registers and then displaying these
> > values on the led screen from lsb to msb (right to left). What kind of
> > representation (signed magnitude, two's complement, ones complement)
> > is my system displaying the binary value ? I am really confused on
> > which technique to use in order to convert it into an integer
> > value ...
>
> I'm not sure I understand exactly what you're doing. Only one idea that
> might help: usually on this kind of board LEDs are connected so they
> light when the IO is set to low. So a lit LED means '0', and '1' turns
> it off. Maybe that's all there is to your problem...
>
> HTH,
> Sean
>
> --
> Replace "MONTH" with the three-letter abbreviation of the current month
> (simple, eh?).

As for the number format, normally it should be two's complement,
assuming you actually have signed values.  For a simple subtract
operation, the unsigned result and the two's complement signed
result would be the same unless your output has more bits than
the inputs.

Article: 136706
Subject: problem about V5 PCI Express endpoint
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Tue, 2 Dec 2008 06:36:04 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,Everybody,recently I made a pcb with v5 for pci express,and I have
5 test boards,and 3 of them can be detected by PC,and 2 of them can
not be detected by PC,and then I use the chipscope serial toolkit to
test the BRET rate,also I compare the good and the failed board.the
good board test pass by the near end PCS and near end PMA loopback
mode,but the failed board can only be tested pass by near end PCS
mode,for near PMA mode,the PLL is locked,all clocks is nomal,but the
MGT can not be linked,can anybody give me some advice for next step to
have a test.Also the MGTAVCC and other voltage are nomal.

Article: 136707
Subject: Re: how to read images from a microSD card ?
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Tue, 02 Dec 2008 08:52:12 -0800
Links: << >>  << T >>  << A >>
papppanas wrote:
> Hello
> 
> My problem right now is that I have to program a Spartan3 starter's kit
> FPGA to read images from a microSD card (i.e. program the memory adaptor)
> and I don't actually know where to start...
> Can someone please give me a hint, so that I can start my work?
> 

This is a pretty good set of articles:

http://elm-chan.org/docs/mmc/mmc_e.html

	-hpa

Article: 136708
Subject: Re: how to read images from a microSD card ?
From: "papppanas" <raluca.florescu@gmail.com>
Date: Tue, 02 Dec 2008 12:08:26 -0600
Links: << >>  << T >>  << A >>

thanks a lot! I hope this will help me get started.


Article: 136709
Subject: Re: how to read images from a microSD card ?
From: "papppanas" <raluca.florescu@gmail.com>
Date: Tue, 02 Dec 2008 12:33:25 -0600
Links: << >>  << T >>  << A >>
>papppanas wrote:
>> Hello
>> 
>> My problem right now is that I have to program a Spartan3 starter's
kit
>> FPGA to read images from a microSD card (i.e. program the memory
adaptor)
>> and I don't actually know where to start...
>> Can someone please give me a hint, so that I can start my work?
>> 
>
>This is a pretty good set of articles:
>
>http://elm-chan.org/docs/mmc/mmc_e.html
>
>	-hpa
>

One more question: I read the article and I'm thinking that it is refered
to how to program SDC/MMCs with a uC. The problem is that I need to used
VHDL to do that.
So my question is: can I use the commands presented (e.g. CMD1
READ_SINGLE_BLOCK) in a VHDL code?

Thanks in advance, 
Raluca

Article: 136710
Subject: Re: problem about V5 PCI Express endpoint
From: Mike Treseler <mtreseler@gmail.com>
Date: Tue, 02 Dec 2008 10:46:02 -0800
Links: << >>  << T >>  << A >>
bjzhangwn@gmail.com wrote:
> Hi,Everybody,recently I made a pcb with v5 for pci express,and I have
> 5 test boards,and 3 of them can be detected by PC,and 2 of them can
> not be detected by PC,and then I use the chipscope serial toolkit to
> test the BRET rate,also I compare the good and the failed board.the
> good board test pass by the near end PCS and near end PMA loopback
> mode,but the failed board can only be tested pass by near end PCS
> mode,for near PMA mode,the PLL is locked,all clocks is nomal,but the
> MGT can not be linked,can anybody give me some advice for next step to
> have a test.Also the MGTAVCC and other voltage are nomal.

Sounds like a logic race or impedance mismatch somewhere.
Check your layout lengths and balanced lines.
Check your fpga timing constraints.

        -- Mike Treseler

Article: 136711
Subject: Re: how to read images from a microSD card ?
From: Mike Treseler <mtreseler@gmail.com>
Date: Tue, 02 Dec 2008 10:49:45 -0800
Links: << >>  << T >>  << A >>
papppanas wrote:

> One more question: I read the article and I'm thinking that it is refered
> to how to program SDC/MMCs with a uC. The problem is that I need to used
> VHDL to do that.

The waveforms are the same.
Do you have a simulator?

> So my question is: can I use the commands presented (e.g. CMD1
> READ_SINGLE_BLOCK) in a VHDL code?

Yes.
It's just bouncing bits.

             -- Mike Treseler

Article: 136712
Subject: Re: how to read images from a microSD card ?
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 2 Dec 2008 13:34:06 -0800 (PST)
Links: << >>  << T >>  << A >>
papppanas wrote:
> Hello
>
> My problem right now is that I have to program a Spartan3 starter's kit
> FPGA to read images from a microSD card (i.e. program the memory adaptor)
> and I don't actually know where to start...
> Can someone please give me a hint, so that I can start my work?
>
> Thanks in advance,
> Raluca

Are you expecting to read images written by a computer or camera
phone?  Chances are those use a FAT system that didn't appear to be
covered by the article pointed out.

Perhaps a chip like the one found here
http://www.sparkfun.com/commerce/product_info.php?products_id=8226
could provide what you want if that is an end-goal.  If you just want
raw access, the article pointed out earlier should get you moving.

Article: 136713
Subject: Re: reading registers
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 2 Dec 2008 13:38:13 -0800 (PST)
Links: << >>  << T >>  << A >>
uraniumore...@gmail.com wrote:
> Hi guys,
>
> I have a spartan 3 starter board from digilent. I using a 2 counter
> and then subtracting the two registers and then displaying these
> values on the led screen from lsb to msb (right to left). What kind of
> representation (signed magnitude, two's complement, ones complement)
> is my system displaying the binary value ? I am really confused on
> which technique to use in order to convert it into an integer
> value ...
>
> Thanks,

Do you mean the "lcd screen?"  Are you using the picoblaze to write to
the screen?  Are you writing characters that the screen can use to
display your data or are you trying to write hte binary values
directly?

I have some code stashed away somewhere which converts a binary value
to decimal in that picoblaze code.

Article: 136714
Subject: Re: reading registers
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Tue, 02 Dec 2008 17:00:15 -0600
Links: << >>  << T >>  << A >>

>  Hi!  To me it seams like you are confused about how all these
>  representations corresponds to numbers. A two complement number is
>  just two complement because you decide it to be. From the hardware
>  perspective there is no difference when adding or
>  subtracting. Although subtracting usually requires you to interpret
>  the numbers as two's complement numbers.

The hardware does need to know about subtracting, or rather negating.
You use different hardware to subtract 1s complement vs 2s complement
numbers.

Maybe what you were thinking is that (with 2s complement) you
can interpreted a number with the top bit set as either a
negative number or a large positive number.  The same
hardware works for both.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136715
Subject: Re: how to read images from a microSD card ?
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Tue, 02 Dec 2008 16:10:28 -0800
Links: << >>  << T >>  << A >>
John_H wrote:
> papppanas wrote:
>> Hello
>>
>> My problem right now is that I have to program a Spartan3 starter's kit
>> FPGA to read images from a microSD card (i.e. program the memory adaptor)
>> and I don't actually know where to start...
>> Can someone please give me a hint, so that I can start my work?
>>
>> Thanks in advance,
>> Raluca
> 
> Are you expecting to read images written by a computer or camera
> phone?  Chances are those use a FAT system that didn't appear to be
> covered by the article pointed out.
> 

There is a link at the bottom of an article linking to another article
on the same site which contains the source for a microcontroller FAT
implementation.

At the point you need a filesystem, you probably want to instantiate a
microcontroller to handle the filesystems.  There are a number of good,
small, free cores readily available.

	-hpa

Article: 136716
Subject: CameraLink Deserilization and Module Constraint Files
From: reganireland@gmail.com
Date: Tue, 2 Dec 2008 16:41:11 -0800 (PST)
Links: << >>  << T >>  << A >>
Hey Guys,

I have used Xilinx XAPP485 to generate a cameralink deserializing
module as the first part in an image processing chain. The problem I
am facing is that I need to create a new top module in order to link
the outputs of the Xilinx module to the start of my image processing
design, and this is causing issues with the Xilinx UCF file.

It designated which pins to map the primary nets, but also forced the
location of two of the edge alignment modules with the RLOC_ORIGIN
constraint. Ont op of this it also generated some clock periods to be
used.

Now I cant use this constraint set because the module it pertains to
is no longer the top, but I also cannot use it on my new top module
(which just wires the two main components up) because the instantiated
modules it refers to do not exist.

Any ideas? Can you specify any constraints for non top modules?

Gints

Article: 136717
Subject: Re: problem about V5 PCI Express endpoint
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Tue, 2 Dec 2008 18:47:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On 12=D4=C23=C8=D5, =C9=CF=CE=E72=CA=B146=B7=D6, Mike Treseler <mtrese...@g=
mail.com> wrote:
> bjzhan...@gmail.com wrote:
> > Hi,Everybody,recently I made a pcb with v5 for pci express,and I have
> > 5 test boards,and 3 of them can be detected by PC,and 2 of them can
> > not be detected by PC,and then I use the chipscope serial toolkit to
> > test the BRET rate,also I compare the good and the failed board.the
> > good board test pass by the near end PCS and near end PMA loopback
> > mode,but the failed board can only be tested pass by near end PCS
> > mode,for near PMA mode,the PLL is locked,all clocks is nomal,but the
> > MGT can not be linked,can anybody give me some advice for next step to
> > have a test.Also the MGTAVCC and other voltage are nomal.
>
> Sounds like a logic race or impedance mismatch somewhere.
> Check your layout lengths and balanced lines.
> Check your fpga timing constraints.
>
>         -- Mike Treseler

Thanks,but why the loopback test fail?near end PMA mode test don"t
communicate with the output singals.

Article: 136718
Subject: Hold Time Requirement
From: carl.horton08@gmail.com
Date: Tue, 2 Dec 2008 22:10:16 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello, There

I read from the following from Wikipedia.

When connecting flip-flops in a chain, it is important to ensure that
the tCO of the first flip-flop is longer than the hold time (tH) of
the second flip-flop, otherwise the second flip-flop will not receive
the data reliably.

http://en.wikipedia.org/wiki/D_flip_flop#D_flip-flop

Could someone help to explain why tCO > tH will ensure the second flip-
flop receive
data reliably?

Thanks,

Carl Horton


Article: 136719
Subject: Re: Hold Time Requirement
From: backhus <nix@nirgends.xyz>
Date: Wed, 03 Dec 2008 08:05:09 +0100
Links: << >>  << T >>  << A >>
carl.horton08@gmail.com schrieb:
> Hello, There
> 
> I read from the following from Wikipedia.
> 
> When connecting flip-flops in a chain, it is important to ensure that
> the tCO of the first flip-flop is longer than the hold time (tH) of
> the second flip-flop, otherwise the second flip-flop will not receive
> the data reliably.
> 
> http://en.wikipedia.org/wiki/D_flip_flop#D_flip-flop
> 
> Could someone help to explain why tCO > tH will ensure the second flip-
> flop receive
> data reliably?
> 
> Thanks,
> 
> Carl Horton
> 
Hi Carl,
the statement you mentioned assumes that both FFs use the same clock.
Also it's assumed that there is almost no delay between from 1st FF
output to 2nd FF input.
If you are developing asics or PCB circuits you may use different kinds 
of FFs with different timing parameters. In that case it might happen, 
that the first FF changes its output line before the hold time required 
for the second FF is over(tCO < tH). Changing a FFs input between start 
of setup time and end of hold time causes unpredictable results or even 
metastability.

May be a rare case, but formally correct.
Inside FPGAs, where all the FFs are the same, this should not be an 
issue at all.

Have a nice synthesis
   Eilert


Article: 136720
Subject: Re: Hold Time Requirement
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 02 Dec 2008 23:10:42 -0800
Links: << >>  << T >>  << A >>
On Tue, 2 Dec 2008 22:10:16 -0800 (PST), carl.horton08@gmail.com
wrote:

>Hello, There
>
>I read from the following from Wikipedia.
>
>When connecting flip-flops in a chain, it is important to ensure that
>the tCO of the first flip-flop is longer than the hold time (tH) of
>the second flip-flop, otherwise the second flip-flop will not receive
>the data reliably.
>
>http://en.wikipedia.org/wiki/D_flip_flop#D_flip-flop
>
>Could someone help to explain why tCO > tH will ensure the second flip-
>flop receive data reliably?

Before I answer your question I'd like to clarify the quote. The said
condition is only true when the clock pins of the two flops have
absolutely zero skew. The more accurate equation is 
tCK1 + tCO >  tCK2 + tH ie the clock arrival time to the the source
clock plus the clock to output delay should be greater than clock
arrival time to the target flop plus the hold time. This fact,
especially in an ASIC, is very helpful for fixing hold violations.

Now the answer to original question relates to the definition of hold.
This constraint requires that the data at the input of a flop should
stay stable a certain amount of time (tH) after the clock edge has
arrived. Assuming zero-skew clocks for the two flops, if tCO is larger
than tH, the input of the second flop will not change earlier than tCO
after the clock edge and this will satisfy the hold constraint.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Article: 136721
Subject: Re: how to read images from a microSD card ?
From: "papppanas" <raluca.florescu@gmail.com>
Date: Wed, 03 Dec 2008 01:32:40 -0600
Links: << >>  << T >>  << A >>

Thanks everyone for the help!

I need to read images, that were written by a computer. 
Thanks for the links, I will check them out as soon as I can today, but
the article about SDC/MMC was very helpful :)

Raluca

Article: 136722
Subject: Re: Hold Time Requirement
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Wed, 03 Dec 2008 02:30:39 -0600
Links: << >>  << T >>  << A >>

>May be a rare case, but formally correct.
>Inside FPGAs, where all the FFs are the same, this should not be an 
>issue at all.

It's not that the FFs are the same, it's that the hardware designers
decided to simplify things for the software guys by making all
FFs appear to have 0 hold time.

It's actually more complicated than that.  The hardware guys have to
promise that min clock-out and min routing has to cover the
max hold time and any clock skew using the normal clock distribution
network.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 136723
Subject: Re: simulation results is correct but synthesis result is not correct
From: bish <bisheshkh@gmail.com>
Date: Wed, 3 Dec 2008 01:22:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 2, 3:52=A0pm, "J.Ram" <jrgod...@gmail.com> wrote:
> On Dec 1, 12:15 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
> wrote:
>
>
>
>
>
> > On 1 Dez., 05:45, "J.Ram" <jrgod...@gmail.com> wrote:
>
> > > Hello,
> > > I have a problem in peice of code.
>
> > I see that you have a problem, but is more than just a piece.
> > Simulation accepts software, synthesis expects hardware description.
> > in vhdl you use for registered data transfer always a template in the
> > form
>
> > process (clk)
> > =A0 if rising_edge(Clk) then
> > =A0 =A0 =A0 <synchron change regs>
> > =A0 end if
>
> > or for asynchronous reset:
>
> > process(clk,reset)
> > =A0 if reset =3D active then
> > =A0 =A0 <reset regs asynchronous>
> > =A0 elsif rising_edge(Clk) then
> > =A0 =A0 <synchron update regs>
> > =A0 end if
>
> > Your first process does something you propably wouldn't expect, when
> > having a rising edge on clk, while reset=3D0 and ref_clk=3D1 This behav=
ior
> > is not synthesisable for most tools and need to be rewritten if
> > needed.
>
> > Three questions:
> > 1. Why do you name a process, if you don't like to name it properly?
> > =A0 =A0(eg. change u1 to registered_counter)
> > 2. Why do you write redundant code?
> > =A0 =A0 =A0 =A0a) if reset =3D 1 or..then...end if; if reset =3D 1 then=
...
> > =A0 =A0 =A0 =A0b) if sig_count >=3D 4 or sig_count >5 then
> > 3. Is there a reason to use the variables? Variables are good practice
> > for most code but I see no reason in this particular code.
>
> > bye Thomas
>
> hello,
> thanks for reply , i made some changes in previous code and reflected
> below.
> simulation is correct in this model, synthesizable but clk is
> unconnected in RTL view.
> can u suggest different code for same functionality.
> i am waiting your reply.
> =A0entity pn_clk is
> port(
> clk: in std_logic;
> ref_clk : in std_logic;
> reset : in std_logic;
> out_clk : out std_logic)
> end entity pn_clk;
>
> architecture behav of pn_clk is
> signal sig_count : natural range 0 to 8 :=3D 0;
> =A0begin
> u1: process(clk, reset, ref_clk)
> variable count : natural range 0 to 8 :=3D 0;

you don't need to use count variable here, you can directly work on
sig_count signal.

> begin
> if reset =3D '1' or ref_clk =3D '1' then
> count :=3D 0;
> end if;

use elsif rising_edge(clk) then     -- instead of end if here.


> if count =3D 8 then
> count :=3D 0;
> else
> count :=3D count + 1;
> end if;
> end if;
> sig_count <=3D count;
> end process u1;
> u2: process(sig_count)
> variable clk_var : std_logic :=3D '0';
> begin
> if sig_count >=3D 4 =A0then
> clk_var :=3D 0;
out_clk <=3D '0'; you don't need to use clk_var variable here too.

> else
> clk_var :=3D 1:
out_clk <=3D '1';
> end if;
> out_clk <=3D clk_var;
don't need this line if you don't use clk_var
> end process u2;
> end behav;- Hide quoted text -
>
> - Show quoted text -


Article: 136724
Subject: Dynamical alteration of signal path
From: "Josip" <josip@yopmail.com>
Date: Wed, 3 Dec 2008 10:34:35 +0100
Links: << >>  << T >>  << A >>
Hi
I would like to build DSP blocks in VHDL, and add a few instances of each in 
FPGA chip. After that I would use microcontroler to control the processing 
chain for one signal bus.
For example, 16-bit audio signal could be routed like this: input -> 
band-pass -> compressor -> echo -> output.
I would like to make as many combinations possible. If that's not possible, 
the blocks could be grouped in stages, and signal routing would be limited 
to choosing one block from each stage.
To summarise: all DSP blocks would be synthesised and programmed only once 
on FPGA device (I would have to make sure they are spread apart, so there's 
enough LUTs between for signal routing). While device is in use, it would be 
partially reprogrammed to redirect signal path through device.
How hard would it be to do this, and what are alternative ways to achieve 
something similar?

Josip 





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