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longbrmb@gmail.com wrote: > > This basically amounts to a hold time violation since my data did not > remain valid long enough at the receiving end. A solution I came up > with was to reverse the polarity of the clock at the output. I > changed the DDR register so that when the internal clock has a rising > edge, the output clock goes low. It seems to work, but I wanted to > get a second opinion on my solution. > > I'm wondering if my original method would have worked in the first > place even if there wasn't a significant load on the clock line? > Since my clock and data are both being generated by FFs at the > outputs, wouldn't the original configuration cause the rising edge of > the clock to occur at the same time as the data was changing thereby > inviting a whole host of metastability problems? Board test engineers ran into the same issue 15 years ago when they had to "daisy-chain" multiple chips for boundary scan. They did the same thing that you are doing. Note that by inverting your clock you are in effect removing the last stage of flops in your design. In the 1149.1 spec they keep the last stage and then resync the outputs to the negedge to provide the hold time. That works better if you have any amount of logic delay going to your last flops D input. John EatonArticle: 138776
Hello, I have a simple uC/OS II system with SRAM, LEDs, switches and 2 tasks as in the original example running on DE2 board. Both tasks successfully print the message to JTAG UART when the .sop file is generated with subscription version of the tools. However, when I regenerated it with Web edition, I started getting the following error: Verifying 00080000 ( 0%) Verify failed between address 0x80000 and 0x8FFFF Leaving target processor paused Reading from the forums, it is the problem with SRAM. 0x80000 is the start of its memory range. People mentioned problems with timing for SDRAM and tweaking settings, but SRAM for DE2 board should be already properly configured. The configuration screen is plain simple too-- there is only a selection for DE2. Both, Subscription and Web editions are 8.1. The University Cores are right in the project directory, so they are the same (http:// www.altera.com/education/univ/materials/ip-cores/unv-ip-cores.html). Do you know what might be the issue? Most of the time I do not have access to Subscription version, so I have to figure this problem out. ThanksArticle: 138777
Hello Everybody ! I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter with a Virtex 4 FX12. What troubles me is the movement of data words from the slow system clock to the faster serializer clock (fast clock is multiples of slow clock). Since the clocks are phase aligned by the dcm, i don't see nescessity for using an async fifo, but i fail to find a simpler solution. Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds word periods) and 140mhz(DDR serializer). Is there any possibility for each clock domain to mark the clock cycle which is aligned with all other clocks ? If all clock domains were conscious about their aligment with the other clocks, data transfers could be arranged in w way that avoids metastabilities. My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz => 7 bit cells): State machine running in fast clock: state_wait_sync_0 (reset_state): when slow clock is low go to state_wait_sync_1 state_wait_sync_1: when slow clock is high go to bitcell_1 bitcell_1 goto bitcell_2 .. bitcell_5 enable_load_data_from_slow_clock goto bitcell_6 bitcell_6: goto bitcell_0 bitcell_0 goto bitcell_1 enable_load_data_from_slow_clock enables a flipflop to register data from slow clock at bitcell_5 to grant the signal from slowclock FF enough setup time to fastclock FF. As simple as that, BUT, i am sampling a clock in transition with a phase aligned clock (at wait_sync_*). This obviously does not work. So how can this be done ? I am curious, there must me a standard method... Thanks and best regards, Julian Grahsl.Article: 138778
On 10 Mar, 12:48, "jag9624" <ma...@grahsl.net> wrote: > Hello Everybody ! > > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter > with a Virtex 4 FX12. > > What troubles me is the movement of data words from the slow system clock > to the faster serializer clock (fast clock is multiples of slow clock). > Since the clocks are phase aligned by the dcm, i don't see nescessity for > using an async fifo, but i fail to find a simpler solution. > > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds > word periods) and 140mhz(DDR serializer). > Is there any possibility for each clock domain to mark the clock cycle > which is aligned with all other clocks ? If all clock domains were > conscious about their aligment with the other clocks, data transfers coul= d > be arranged in w way that avoids metastabilities. > > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz > =3D> 7 bit cells): > > State machine running in fast clock: > > =A0state_wait_sync_0 (reset_state): > =A0 when slow clock is low go to state_wait_sync_1 > > =A0state_wait_sync_1: > =A0 when slow clock is high go to bitcell_1 > > =A0bitcell_1 > =A0 goto bitcell_2 > .. > =A0bitcell_5 > =A0 enable_load_data_from_slow_clock > =A0 goto bitcell_6 > > =A0bitcell_6: > =A0 goto bitcell_0 > > =A0bitcell_0 > =A0 goto bitcell_1 > > enable_load_data_from_slow_clock enables a flipflop to register data from > slow clock at bitcell_5 to grant the signal from slowclock FF enough setu= p > time to fastclock FF. > > As simple as that, BUT, i am sampling a clock in transition with a phase > aligned clock (at wait_sync_*). This obviously does not work. So how can > this be done ? I am curious, there must me a standard method... > > Thanks and best regards, > Julian Grahsl. Mhm... I don't prefer this kind of solution. What can I advice you is you use block RAM for repacking data, or use 140MHz clock with CLOCK_ENABLE. Then you be sure, that everything will work well. Kind Regards, Jerzy GburArticle: 138779
Hi Jerzy ! My main problem is synchronizing two processes: 1) My LVDS clock, which runs at 40 Mhz. 2) The serialiser which transmits 7 bits within each 40 Mhz period. The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate is effectively 280Mhz) The serialiser needs to lock on the LVDS Clock to figure out where to place the first bit. I dont know how to accomplish this. I cant observe the 40 Mhz clock from the 140Mhz domain without risking metastabilities... I fact i found a working solution, but i don't like it: I use the LOCKED signal created by the DCM (Virtex4) which gives me the exact point where all clocks are aligned. So synchronization is done only once and never checked again. regards, JulianArticle: 138780
If you are doing HDL-based design, you are probably using integer arithmetic regularly. In doing so, you may often be struggling with mysterious behaviour, sign bit extensions, resizings and type conversions, in order to get things to work as you want. I believe such efforts are a waste of your valuable engineering time, caused by bad language design choices in Verilog and VHDL. I have written an essay that explores these issues in detail, and proposes a solution: http://www.jandecaluwe.com/hdldesign/counting.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.orgArticle: 138781
Hi This is a good argument. It is why I prefered ieee.std_logic_arith an staying with bit vectors. It means the cast signed or unsigened is placed around each input std_logic_vector, and the output automatically casts to the required std_logic_vector. Ooooooh, don't you just miss the division operators from numeric_std? No. I don't even miss the multiplication operators. If I get to needing such things, I will use one from either synopsis free distribution files, or a homebrew one. So put simply the signed or unsigned just specifies the sign extension for the arithmetic. I find no problem in thinking in terms of std_logic_vector. It does not suffer from integer's lack of width generics. Although useful for generate statements integers be, ya , yoda. cheers jackoArticle: 138782
On Mar 9, 11:57=A0pm, John Eaton <nos...@spam.com> wrote: > Note that by inverting your clock you are in effect removing the last > stage of flops in your design. In the 1149.1 spec they keep the last > stage and then resync the outputs to the negedge to provide the hold > time. That works better if you have any amount of logic delay going to > your last flops D input. > > John Eaton Thanks for the input, I'm glad to hear that other people have run into this problem as well. I'm not sure I understand what you mean about "in effect removing the last stage of flops." I looked at the 1149.1 spec and if I understand correctly they have the controller and all slave devices operating on the same clock. The outputs are retimed (probably by a negedge flop) to occur on the falling edge of the clock. In my current solution the fpga is creating the clock for the slave devices. In this case, all my internal logic operates on the "positive" clock and I simply invert the clock output pin that is being sent to the slave devices. In terms of what the slave devices see, I don't see how this is any different than using the "positive" clock for everything and retiming the data outputs to change on the falling edge. Matt LongbrakeArticle: 138783
On Tue, 10 Mar 2009 08:59:47 -0500 "jag9624" <mail2@grahsl.net> wrote: > Hi Jerzy ! > > My main problem is synchronizing two processes: > > 1) My LVDS clock, which runs at 40 Mhz. > 2) The serialiser which transmits 7 bits within each 40 Mhz period. > > The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate > is effectively 280Mhz) > > The serialiser needs to lock on the LVDS Clock to figure out where to > place the first bit. I dont know how to accomplish this. I cant > observe the 40 Mhz clock from the 140Mhz domain without risking > metastabilities... > > I fact i found a working solution, but i don't like it: > I use the LOCKED signal created by the DCM (Virtex4) which gives me > the exact point where all clocks are aligned. So synchronization is > done only once and never checked again. > > regards, > Julian The DCM is, if I recall correctly, keeping all of your clocks rising edge aligned, i.e. every 50 ns you have a rising 140 MHz edge happening at (nearly) the same time as a 40 MHz rising edge, and 25 ns after that, you'll always have your next rising edge on the 40 MHz coincident with the falling edge of the 140 MHz clock. If you set a flip-flop to toggle on every tick of the 40 MHz clock, then sample that output with both rising and falling 140 MHz flop, you should be able to resolve the phase relationship unambiguously without any metastability risk. Not because it's a general solution, but specifically because you've got the DCM enforcing a known phase relationship. Really, all that is just a special case of the classic pulse-toggle-pulse synchronizer. You can just get away without the extra resynchronizer stages on the second side because of the known phases. Likewise, because of that, there's a way to force the static timing analysis to look at those paths if you need some verification, but what the exact syntax on that is I can't recall and I haven't had enough coffee yet to brave the depths of CGD.PDF again. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 138784
Hi, building a makefile to have things run from the command line. Synthesis, implementation, configure and programming is working. Now I am looking at how to do syntax checking on single files. Tried to run syntax check from ISE to see if the command line was displayed in the command log window, but all I could see was that my code was correct :-) Couldn't find very much in the documentation either and a search on google gave me mostly what I already know from ISE. -- SvennArticle: 138785
Svenn Are Bjerkem wrote:
> Now I
> am looking at how to do syntax checking on single files.
I use modelsim.
vlog mymodule.v
-- Mike Treseler
Article: 138786longbrmb@gmail.com wrote: > > I'm not sure I understand what you mean about "in effect removing the > last stage of flops." I looked at the 1149.1 spec and if I understand > correctly they have the controller and all slave devices operating on > the same clock. The outputs are retimed (probably by a negedge flop) > to occur on the falling edge of the clock. In my current solution the > fpga is creating the clock for the slave devices. In this case, all > my internal logic operates on the "positive" clock and I simply invert > the clock output pin that is being sent to the slave devices. In > terms of what the slave devices see, I don't see how this is any > different than using the "positive" clock for everything and retiming > the data outputs to change on the falling edge. > > Matt, The value that is latched into your output stage on the rising edge is then latched into the slaves input flop on the next falling edge. It passes through two flops in one clock cycle. If you retimed the output and used the positive edge then it would delay everything into the next clock cycle and look like you added an extra stage. John EatonArticle: 138787
On Mar 10, 7:03=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > If you are doing HDL-based design, you are probably using > integer arithmetic regularly. In doing so, you may often be > struggling with mysterious behaviour, sign bit extensions, > resizings and type conversions, in order to get things > to work as you want. > > I believe such efforts are a waste of your valuable > engineering time, caused by bad language design choices > in Verilog and VHDL. > > I have written an essay that explores these issues in > detail, and proposes a solution: > > http://www.jandecaluwe.com/hdldesign/counting.html Excellent treatise although I'm not convinced I want to use Python for hardware development. I use integers and naturals, with appropriate ranges, all the time. Perhaps the people on the VHDL committee could promulgate the following for the next update to the language, whenever that might be: a) the arbitrary 32-bit limit on the size of integers and naturals should be relaxed or eliminated, for the obvious reasons. And it's probably also obvious that everyone who does use integers and naturals in VHDL code already uses ranges. b) when dealing with signed and unsigned types, sign-extension should be implicit (no need for resize() calls) such that all operands on the RHS get extended to the size of LHS result. An error should be thrown if any operand on the RHS is larger than the LHS result -- no need for obscure truncation rules a-la Verilog. -aArticle: 138788
On Mar 10, 6:59=A0am, "jag9624" <ma...@grahsl.net> wrote: > Hi Jerzy ! > > My main problem is synchronizing two processes: > > 1) My LVDS clock, which runs at 40 Mhz. > 2) The serialiser which transmits 7 bits within each 40 Mhz period. > > The serialiser needs a 140Mhz clock (I am using a DDR FF, so bitrate is > effectively 280Mhz) > > The serialiser needs to lock on the LVDS Clock to figure out where to > place the first bit. I dont know how to accomplish this. I cant observe t= he > 40 Mhz clock from the 140Mhz domain without risking metastabilities... > > I fact i found a working solution, but i don't like it: > I use the LOCKED signal created by the DCM (Virtex4) which gives me the > exact point where all clocks are aligned. So synchronization is done only > once and never checked again. I agree with Jerzy -- use some sort of dual-port to cross the clock domain. I did a Camera Link serializer (DS90CR287 replacement) in a Spartan 3AN, and the only way to get it to work was to create a ping-pong buffer from a dual-port RAM in LUTs. The write side is clocked at the parallel data rate, and on each rising edge a new data word (28 bits) is written to one or the other location. The read side clock is at 3.5X the parallel rate, and a little state machine reads the pong buffer during the time the write side is updating the ping buffer (and the converse). The 3.5X also clocks the ODDR2s and a mux which determines which read bits drive the ODDR2 D0 and D1 input. (Hint: use DDR_ALIGNMENT =3D "C0" so you write both D0 and D1 on the rising edge of the clock.) Oh, yeah, there's a Xilinx app note about doing a 7:1 serializer, but it's typically awful. -aArticle: 138789
On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote: > Hello Everybody ! > > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter > with a Virtex 4 FX12. > > What troubles me is the movement of data words from the slow system clock > to the faster serializer clock (fast clock is multiples of slow clock). > Since the clocks are phase aligned by the dcm, i don't see nescessity for > using an async fifo, but i fail to find a simpler solution. > > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds > word periods) and 140mhz(DDR serializer). > Is there any possibility for each clock domain to mark the clock cycle > which is aligned with all other clocks ? If all clock domains were > conscious about their aligment with the other clocks, data transfers coul= d > be arranged in w way that avoids metastabilities. > > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mhz > =3D> 7 bit cells): > > State machine running in fast clock: > > =A0state_wait_sync_0 (reset_state): > =A0 when slow clock is low go to state_wait_sync_1 > > =A0state_wait_sync_1: > =A0 when slow clock is high go to bitcell_1 > > =A0bitcell_1 > =A0 goto bitcell_2 > .. > =A0bitcell_5 > =A0 enable_load_data_from_slow_clock > =A0 goto bitcell_6 > > =A0bitcell_6: > =A0 goto bitcell_0 > > =A0bitcell_0 > =A0 goto bitcell_1 > > enable_load_data_from_slow_clock enables a flipflop to register data from > slow clock at bitcell_5 to grant the signal from slowclock FF enough setu= p > time to fastclock FF. > > As simple as that, BUT, i am sampling a clock in transition with a phase > aligned clock (at wait_sync_*). This obviously does not work. So how can > this be done ? I am curious, there must me a standard method... > > Thanks and best regards, > Julian Grahsl. You might want to check out XAPP855 16-Channel, DDR LVDS Interface with Per-Channel Alignment. It is for a Virtex-5 but many of the components sited are in the Virtex 4. (oserdes, oddr, FIFO16 etc.)Article: 138790
Hi im working on an example design with a TEMAC Core from Xilinx Can any1 who has experience on this tell me whether ping will work with this example design...??? i assume it dont. * by ping i mean pinging from PC to a Tri mode wthernet mac wrapper in fpgaArticle: 138791
On Mar 11, 7:17=A0am, knight <krshe...@gmail.com> wrote: > Hi im working on an example design with a TEMAC Core from Xilinx > Can any1 who has experience on this tell me whether ping will work > with this example design...??? i assume it dont. > > * by ping i mean pinging from PC to a Tri mode wthernet mac wrapper in > fpga just take Xilinx ethernet PING reference design (Echo server) it does do respond to ping, but you need EDK the wrapper alone of course does nothing.. AnttiArticle: 138792
if i think of it, it should be doable? but i do not recall any projects that would use such transmit method normal FPGA LVDS are fast enough that it would be possible just capacitive decoupling sure some encoding should be applied but that shouldnt also be a problem AnttiArticle: 138793
Svenn Are Bjerkem wrote: > Hi, > building a makefile to have things run from the command line. > Synthesis, implementation, configure and programming is working. Now I > am looking at how to do syntax checking on single files. Tried to run > syntax check from ISE to see if the command line was displayed in the > command log window, but all I could see was that my code was > correct :-) > Couldn't find very much in the documentation either and a search on > google gave me mostly what I already know from ISE. > > -- > Svenn You could launch xtclsh and use the command process run "check syntax" -force -rerun_all but I think that does the whole file. Alternatively, run xst but you -top to tell it which file to synthesize, Alan -- Alan Fitch Doulos http://www.doulos.comArticle: 138794
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:64c04f8c-9f8e-4523-b592-5fa017181654@j39g2000yqn.googlegroups.com... > if i think of it, it should be doable? > > but i do not recall any projects that would use such transmit method > > normal FPGA LVDS are fast enough that it would be possible just > capacitive decoupling > sure some encoding should be applied but that shouldnt also be a > problem > > Antti Hi Antti, You should probably use Manchester encoding or CMI if you intend to AC couple. Long strings of ones or zeroes in NRZ could give you problems. Dunno how far you can send stuff without some pre-emphasis and receive compensation, depends on your bitrate. Cheers, Syms.Article: 138795
>if i think of it, it should be doable? > >but i do not recall any projects that would use such transmit method > >normal FPGA LVDS are fast enough that it would be possible just >capacitive decoupling >sure some encoding should be applied but that shouldnt also be a >problem > >Antti > Hi Antti ! I have not worked with AC-coupled systems yet, but i have read about AC-coupled LVDS transmission in an Xilinx Appnote, take a look at www.xilinx.com/support/documentation/application_notes/xapp756.pdf kind regards, julianArticle: 138796
Thank you all very much for your constructive inputs ! Kind regards, JulianArticle: 138797
>> Now I >> am looking at how to do syntax checking on single files. > > I use modelsim. > vlog mymodule.v I have Textpad set up to run vcom (VHDL compile) in the background, capture the results and provide a hot-link to any errors. I've configured a tool to launch this so it's a only click process! NialArticle: 138798
Hi all, looks like opencores.org changes it's hosting strategies without asking their user and core providers. At the moment the CVS access is down and it looks like they changed to SVN. Without a notice to the core providers. Any more information on this? Cheers, MartinArticle: 138799
Hi many fixes, now offered open licence, of 1 core per FPGA/CPLD/ASIC with the restriction that the K Ring logo must appear ontop the chip or close to it on the PCB, and any documentation produced must credit copyright to K Ring technologies, and provide the URL to the site http://nibz.googlecode.com The gforth port is not complete but contains many machine code examples, including a boot loader for sd card. cherrs Simon jackson, BEng. Creative technologist K Ring Technologies http://nibz.googlecode.com
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