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On Mon, 16 Feb 2009 16:38:45 -0800 (PST), rickman <gnuarm@gmail.com> wrote:
>
>I'm curious, why would you use a construct that you need to ask help
>on when you could easily use a nested IF ELSIF structure and make it
>perfectly clear what is intended to yourself as well as any other
>designers who need to maintain your code. Don't get me wrong, I'm not
>saying the above is a bad way to code. But obviously it is a little
>less clear. For example, even if you understand the VHDL rules
>governing this, it is not clear to someone else if it is *possible*
>for event1, event2 and event3 to be active at the same time. So if
>someone else has to change the code, they don't know if you are
>counting on the priority of the events or if it does not matter. If
>you use IF ELSIF ELSEIF THEN, you will be clearly indicating that you
>inend to enforce a priority on the assignments. Not only that, it is
>fewer lines of code so it will be easier to debug... ;^)
>
>Just a thought.
>
>Rick
OK, here is the relevant bit of the real code, it's part of a custom UART
which does some de-multiplexing of the received data into 2 different receive
buffers:
-- Receive FIFOs & overrun flags
-- Overrun flag set if write attempt made when FIFO full, cleared after reading status register
-- If overrun flag set and reset events occur in the same clock cycle, set takes priority over reset
-- to ensure overrun event is always detected
p_rx_fifo : process(master_clk) begin
if(master_clk'event and master_clk = '1') then
if(sts_reg_rd_stb = '1') then
rx_fifo_ovrun <= '0';
n_rx_fifo_ovrun <= '0';
end if;
if(rx_done_stb = '1') then
if((tx_sm = tsm_wait_rcv1) or (tx_sm = tsm_wait_rcv2)) then
-- NRSA Rx FIFO
if(n_rx_fifo_full = '0') then
n_rx_fifo_wr_stb <= '1';
else
n_rx_fifo_ovrun <= '1';
end if;
else
-- User Rx FIFO
if(rx_fifo_full = '0') then
rx_fifo_wr_stb <= '1';
else
rx_fifo_ovrun <= '1';
end if;
end if;
else
rx_fifo_wr_stb <= '0';
n_rx_fifo_wr_stb <= '0';
end if;
end if;
end if;
end process;
I coudn't see any other way of 'decoupling' the set and clear operations for the overrun flags.
The 'set' path through the code only occurs if a new character has been received, the
'clear' path only occurs if the status register is read. The process is also deciding which
FIFO to put the received character in, based on the state machine tx_sm, and generating the
write strobes for the FIFOs.
There's probably a neater way of doing this, I'm a relative newcomer to VHDL.
Regards
R.
Article: 138351On Feb 17, 3:45 am, n...@rblack01.plus.com wrote: > On Mon, 16 Feb 2009 16:38:45 -0800 (PST), rickman <gnu...@gmail.com> wrote: > > >I'm curious, why would you use a construct that you need to ask help > >on when you could easily use a nested IF ELSIF structure and make it > >perfectly clear what is intended to yourself as well as any other > >designers who need to maintain your code. Don't get me wrong, I'm not > >saying the above is a bad way to code. But obviously it is a little > >less clear. For example, even if you understand the VHDL rules > >governing this, it is not clear to someone else if it is *possible* > >for event1, event2 and event3 to be active at the same time. So if > >someone else has to change the code, they don't know if you are > >counting on the priority of the events or if it does not matter. If > >you use IF ELSIF ELSEIF THEN, you will be clearly indicating that you > >inend to enforce a priority on the assignments. Not only that, it is > >fewer lines of code so it will be easier to debug... ;^) > > >Just a thought. > > >Rick > > OK, here is the relevant bit of the real code, it's part of a custom UART > which does some de-multiplexing of the received data into 2 different receive > buffers: > > -- Receive FIFOs & overrun flags > -- Overrun flag set if write attempt made when FIFO full, cleared after reading status register > -- If overrun flag set and reset events occur in the same clock cycle, set takes priority over reset > -- to ensure overrun event is always detected > p_rx_fifo : process(master_clk) begin > if(master_clk'event and master_clk = '1') then > if(sts_reg_rd_stb = '1') then > rx_fifo_ovrun <= '0'; > n_rx_fifo_ovrun <= '0'; > end if; > if(rx_done_stb = '1') then > if((tx_sm = tsm_wait_rcv1) or (tx_sm = tsm_wait_rcv2)) then > -- NRSA Rx FIFO > if(n_rx_fifo_full = '0') then > n_rx_fifo_wr_stb <= '1'; > else > n_rx_fifo_ovrun <= '1'; > end if; > else > -- User Rx FIFO > if(rx_fifo_full = '0') then > rx_fifo_wr_stb <= '1'; > else > rx_fifo_ovrun <= '1'; > end if; > end if; > else > rx_fifo_wr_stb <= '0'; > n_rx_fifo_wr_stb <= '0'; > end if; > end if; > end if; > end process; > > I coudn't see any other way of 'decoupling' the set and clear operations for the overrun flags. > The 'set' path through the code only occurs if a new character has been received, the > 'clear' path only occurs if the status register is read. The process is also deciding which > FIFO to put the received character in, based on the state machine tx_sm, and generating the > write strobes for the FIFOs. > > There's probably a neater way of doing this, I'm a relative newcomer to VHDL. I can't say if there is a neater way to code this or not. But the if (sts_reg_rd_stb = '1') could be put in the ELSE part of the if (rx_done_stb = '1') structure. I'm not completely clear on what the code is doing, so I can't say if there is a better way to structure it. After looking at it for a bit, it actually looks fairly clear to me. I would move the first IF (lowest priority) to be an ELSIF to make that clear. Also, I just think it reads more clearly showing it in a single unified structure rather than using two structures and then having to rely on the order to create the final level of priority. Also, some comments might help. For example, why is tx_sm being checked in what appears to be the receiver code??? RickArticle: 138352
On Tue, 17 Feb 2009 08:45:09 +0000, news@rblack01.plus.com wrote:
>OK, here is the relevant bit of the real code, it's part of a custom UART
>which does some de-multiplexing of the received data into 2 different receive
>buffers:
It's not particularly bad code - one abstraction I would be tempted to make is
to abstract out this logic into a procedure local to the process...
procedure set_wr_strobe (signal fifo_full : std_logic;
OUT fifo_wr_stb, fifo_ovrun : std_logic) is
begin
> if(fifo_full = '0') then
> fifo_wr_stb <= '1';
> else
> fifo_ovrun <= '1';
> end if;
end procedure set_wr_strobe;
>-- to ensure overrun event is always detected
> p_rx_fifo : process(master_clk) begin
> if(master_clk'event and master_clk = '1') then
> if(sts_reg_rd_stb = '1') then
> rx_fifo_ovrun <= '0';
> n_rx_fifo_ovrun <= '0';
> end if;
> if(rx_done_stb = '1') then
> if((tx_sm = tsm_wait_rcv1) or (tx_sm = tsm_wait_rcv2)) then
> -- NRSA Rx FIFO
set_wr_strobe (n_rx_fifo_full,
n_rx_fifo_wr_stb, n_rx_fifo_ovrun);
> else
> -- User Rx FIFO
set_wr_strobe (rx_fifo_full,
rx_fifo_wr_stb, rx_fifo_ovrun);
> end if;
> else
> rx_fifo_wr_stb <= '0';
> n_rx_fifo_wr_stb <= '0';
> end if;
> end if;
> end if;
> end process;
>
But then I might be caught by a bug in XST which obeys variable assignment rules
for those OUT mode signals. (Which may not matter if those signals aren't read
in this same process). I really hope THIS one gets fixed in ISE 11...
I believe that tool defects and the need to work around them is doing more to
hold back progress in using VHDL at a higher level than anything in the language
itself.
- Brian
Article: 138353Gabor <gabor@alacron.com> wrote in news:e0edd268-99d3-44de-b126- 90be9409870d@m15g2000vbp.googlegroups.com: > On Feb 16, 5:37 am, Antti <Antti.Luk...@googlemail.com> wrote: >> On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: >> >> > Hi everybody, >> >> > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is >> > 100 MHz) the FPGA doesn't start up ! >> > whereas it is not the case for unencrypted one . Why ??? >> > I need to configure the FPGA as quickly as possible. >> >> > Thanks. >> >> you need to use parallel mode :( >> i think the 100mhz ecnrypted mode may not be supported, please >> check the datasheets >> >> Antti > > I've run into other problems at 100 MHz for unencrypted bitstreams > as well. When the DONE signal is allowed to float high, the > startup state logic can sample it in the threshold region > (yes the chip samples the pin unless you set "Internal Done Pipe") > and lock up. I solved this using the internal done pipe, but > another recommendation was to "Drive Done High". My external > DONE pullup was 330 ohms as recommended, but at 100 MHz, this > is not fast enough. Another approach to fix this might be to > slow down CCLK at or near the end of the bitstream. The last time I looked into this (Virtex2?), the specification for maximum frequency with encryption wasn't specified in the datasheets. The figure was specified in some obscure app note, and was something like 10MHz, much lower than the frequency allowed without encryption. Things may have improved with more recent FPGA families though. Regards, AllanArticle: 138354
hie..... i want to give external clk to my design from signal generator so that i can vary the frequency of clock in run time...here i am bypassing the system clock which is 50MHz for the board iam using(XSA-50) that is designed module uses this external signal as a clock..... So the question is,Can i use this external clock instead of system clock??... if yes, what it meant by the following error massage during implementing of design after pin assignment....I have assigned the external clock to the general i/o pin i.e Pin 80.... ERROR:MapLib:93 - Illegal LOC on IPAD symbol "clk" or BUFGP symbol "clk_BUFGP" and How can i fix this error?? any help would be greatly appreciated.....Article: 138355
On Feb 16, 7:53 pm, rickman <gnu...@gmail.com> wrote:
> On Feb 16, 3:43 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > See the well-informed discussion on the very recent thread
> > unsigned(), unsigned'(), to_unsigned()
> > on comp.lang.vhdl; and many other such over the
> > past few years.
>
> Jon,
>
> The problem you are seeing is due to the strong typing of VHDL and is
> intended to prevent you from shooting yourself in the foot. The above
> is, in a nutshell, what you need to learn to deal with this. After
> you fight... I mean *learn* the rules associated with this I'll let
> you tell me if it is worth it.
>
> I think if I had learned Verilog first, I would have never used VHDL.
> But I am pretty used to it now so no big deal. Still, there are
> millions of lines of code running the Internet or even satellites that
> have never been "protected" by strong typing. I think there are any
> number of other things that are much more important to correct design
> than strong typing.
>
> Rick
I have no problems with the rules of conversion, I just have to
unlearn a bunch
of lazy habits that C lets you get away with. in C, if its an 8 bit
storage location,
that's all that really matters, 8 bits is 8 bits.
I actually had the right solution here:
temp_label_index <= integer(unsigned(lbl_data(3 downto 0)));
I had simply misread my textbook, and used integer instead of
TO_integer.
I'm not even sure what "tempvar <= integer(xyz)" will do. I thought
the reserved word integer
was for variable declaration. It must have another definition in this
context that is different.
also from my reading I came across:
d <= signed'("00" & c);
what does the ' character do?
Article: 138356On Feb 17, 9:50=A0am, GrIsH <grishkun...@gmail.com> wrote: > hie..... > i want to give external clk to my design from signal generator so that > i can vary the frequency of clock in run time...here i am bypassing > the system clock which is 50MHz for the board iam using(XSA-50) that > is designed module uses this external signal as a clock..... > > So the question is,Can i use this external clock instead of system > clock??... > > if yes, what it meant by the following error massage during > implementing of design after pin assignment....I have assigned the > external clock to the general i/o pin i.e Pin 80.... > > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "clk" or BUFGP symbol > "clk_BUFGP" > > and How can i fix this error?? > > any help would be greatly appreciated..... Take a look at the manual at http://www.xess.com/manuals/xsa-manual-v1_2.pd= f Page 22 shows the clock inputs of the FPGA. FPGA pin 18 connects to the board's header pin # 1. So in this case you need a LOC statement that says that pin -18- is used as a clock input. Your signal generator has to produce square waves with a LO of 0 volts and a HI of 5 volts. HTH -Dave PollumArticle: 138357
On Tue, 17 Feb 2009 07:26:02 -0800 (PST), jleslie48 wrote:
>I'm not even sure what "tempvar <= integer(xyz)" will do. I thought
>the reserved word integer
>was for variable declaration. It must have another definition in this
>context that is different.
>also from my reading I came across:
> d <= signed'("00" & c);
>
>what does the ' character do?
PLEASE read, carefully, the thread on comp.lang.vhdl
that I cited:
> See the well-informed discussion on the very recent thread
> unsigned(), unsigned'(), to_unsigned()
> on comp.lang.vhdl; and many other such over the
> past few years.
In (very) brief:
* type_name(expression) is a TYPE CONVERSION. It is
a type-cast, like "(type_name)expression" in C, but
it works only between "closely related types":
std_logic_vector <-> unsigned, signed
integer <-> real
any array type <-> any other array type with
the same element type and the
same index (subscript) type
* type_name'(expression) is a TYPE QUALIFICATION.
It is useful only when the type of "expression"
is ambiguous: for example, is "1001" a string or
a std_logic_vector? string'("1001") disambiguates.
Type qualification cannot do any conversion;
"expression" MUST be a valid example of "type_name"
otherwise it doesn't work.
NOTE: I said "type_name" above; strictly speaking
I should have said "type mark" but that's
language-lawyer pedant stuff.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 138358Hi all, I've built a fairly large and complex design in VHDL and tried to implement it on a Xilinx virtex-4 FX100 fpga. I have verified the functionality of my design through the behavioural simulations. After that, I decided to implement it on the fpga. I chose a set of inputs the same as I used in the behavioural simulations and then run the hardware. When I read the outputs, which are some internal registers, they match the values read from the simulations. However, sometimes the results do not match. In all of these cases, I use the same inputs and moreover I reload the bitstream to the fpga to make the situation equal. I thought the timing constraints may be violated, so I reduced the clock frequency, however, no significant effect can be seen. I can conclude that the design is synthesized according to the desired functionality, since it generates the desired outputs in some instances. However, I cannot understand why it malfunctions occasionally for the fixed inputs. What type of errors can lead to this problem? What can I do when the error is not repeatable? My design is basically controlled by an FSM which has 16 states. I send the start command and then it goes through all the states and finally asserts a done signal. Once the register values are incorrect, the done signal is also not set. So, something should stop the FSM from moving forward. Thank you in advance for your comments.Article: 138359
On Feb 17, 8:24=A0am, Ehsan <ehsan.hosse...@gmail.com> wrote: > Hi all, > > I've built a fairly large and complex design in VHDL and tried to > implement it on a Xilinx virtex-4 FX100 fpga. I have verified the > functionality of my design through the behavioural simulations. After > that, I decided to implement it on the fpga. I chose a set of inputs > the same as I used in the behavioural simulations and then run the > hardware. When I read the outputs, which are some internal registers, > they match the values read from the simulations. However, sometimes > the results do not match. In all of these cases, I use the same inputs > and moreover I reload the bitstream to the fpga to make the situation > equal. I thought the timing constraints may be violated, so I reduced > the clock frequency, however, no significant effect can be seen. I can > conclude that the design is synthesized according to the desired > functionality, since it generates the desired outputs in some > instances. However, I cannot understand why it malfunctions > occasionally for the fixed inputs. What type of errors can lead to > this problem? What can I do when the error is not repeatable? > > My design is basically controlled by an FSM which has 16 states. I > send the start command and then it goes through all the states and > finally asserts a done signal. Once the register values are incorrect, > the done signal is also not set. So, something should stop the FSM > from moving forward. > > Thank you in advance for your comments. Do you have asynchronous inputs going from a pin straight into the FSM? If so, you are probably violating a setup time and causing your FSM to go crazy. Look through this news group for lots of discussion on this. One keyword of interest might be "metastable" John ProvidenzaArticle: 138360
On Feb 17, 10:26 am, jleslie48 <j...@jonathanleslie.com> wrote:
>
> I actually had the right solution here:
>
> temp_label_index <= integer(unsigned(lbl_data(3 downto 0)));
>
> I had simply misread my textbook, and used integer instead of
> TO_integer.
>
> I'm not even sure what "tempvar <= integer(xyz)" will do. I thought
> the reserved word integer
> was for variable declaration. It must have another definition in this
> context that is different.
> also from my reading I came across:
> d <= signed'("00" & c);
>
> what does the ' character do?
Jonathan gave you a reference above that looks to be very good.
Search google groups on "unsigned(), unsigned'(), to_unsigned()"
In a nutshell, the to_xxx function is just that, a function that is
defined to convert between various data types that are not closely
related. If that function is not defined, it won't work. That is why
Jonathan said to "(2) Trawl comp.lang.vhdl for references to
"numeric_std";" numeric_std provides for conversions between the
signed and unsigned types and other, not closely related types.
unsigned () allows the conversion of closely related types, that is
types that really don't need any conversion between them. I believe
this is equivalent to type casting in C (if I remember enough about
type casting in C). No conversion is made, so the types must have a
common element(s) and be defined according to
http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#ambiguous_expressions
unsigned' is used when the item used is not of a definite type. This
establishes the type. What does that mean??? A string can be several
different types for example. Often the usage of a string is clear
from the context (meaning clear according to the rules VHDL works
under). But sometimes the type is not clear. An example is when a
function is defined with overloaded parameter types such as bit vector
and slv. These types are not closely related, so the tool does not
know when function you intend. So the xxx' gives the tool a hint and
it is now happy and stops throwing errors at you. (not quite the same
as throwing arrows at you)
Do the search and read the other thread. Also check out the FAQ, that
is a great source of *good* information if you don't already use it.
This whole typing issue is where I have had the most trouble with VHDL
myself. That is one of many reasons why I limit my coding style.
Staying within my self imposed white lines keeps me from having to
remember all sorts of details about a rather Daedalian language.
Oh, one other caution, the fact that you program works with any given
tool does not mean it has been written correctly with respect to the
rules of VHDL. Tools often have "features" where they accept
constructs that are not actually correct and won't work on other
tools. But maybe that has gone by the wayside. I haven't been
pushing that issue in a while.
Rick
Article: 138361
"koethe.daniel.de@googlemail.com" <dkoethe@web.de> wrote:
>Hello Antti,
>on the webpage is a .ucf file available, but this contains NOT the
>DDR3-SDRAM pins.
>
>You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>
>Use the SSTL18_[I,II] at VCCO=1.5V and Vref=0,75V should be possible,
>but nobody guarantees the IO-Timing and Voltage Levels.
>
>But there is a second challenge. The maximal clock cycle with DDR3-
>SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
>Spartan-3A Memory-Controllers.
>
>Micron Datasheet:
>http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb%20DDR3%20SDRAM.pdf
>
>
>This DLL can disabled, but the relationchip between clk and data
>output delay is lost. Second you must disable the ODT (On Die
>Termination).
If you disable the DLL, the clock range of DDR3 is very wide. Actually
much wider when using DDR or DDR2 memory. So it makes perfect sense to
use DDR3 on an FPGA because its lower power and easier to design and
still have dual data rate memory. Running it at 80MHz or 100MHz is
very feasible IMHO.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 138362On Tue, 17 Feb 2009 08:24:27 -0800 (PST), Ehsan <ehsan.hosseini@gmail.com> wrote: >My design is basically controlled by an FSM which has 16 states. I >send the start command and then it goes through all the states and >finally asserts a done signal. Once the register values are incorrect, >the done signal is also not set. So, something should stop the FSM >from moving forward. One thing you have to make sure very early on is that all external signals which go into the FPGA are correctly synchronized. There are different ways of doing this for single values and busses. Let's take one example: your start command. Assuming this is a single wire, you have to register in your design with a series of flops (usually two is enough) with the clock of the receiving registers and use the output as the real start command. Similarly all input handshake signals are to be synchronized and all busses are to be timed correctly with respect to the handshake signals. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 138363
On Feb 17, 6:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > "koethe.daniel...@googlemail.com" <dkoe...@web.de> wrote: > >Hello Antti, > >on the webpage is a .ucf file available, but this contains NOT the > >DDR3-SDRAM pins. > > >You are right, spartan-3A DSP does not support DDR3-Voltage Levels. > > >Use the SSTL18_[I,II] at VCCO=3D1.5V and Vref=3D0,75V should be possible= , > >but nobody guarantees the IO-Timing and Voltage Levels. > > >But there is a second challenge. The maximal clock cycle with DDR3- > >SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the > >Spartan-3A Memory-Controllers. > > >Micron Datasheet: > >http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb%20DDR3%20SDRA... > > >This DLL can disabled, but the relationchip between clk and data > >output delay is lost. Second you must disable the ODT (On Die > >Termination). > > If you disable the DLL, the clock range of DDR3 is very wide. Actually > much wider when using DDR or DDR2 memory. So it makes perfect sense to > use DDR3 on an FPGA because its lower power and easier to design and > still have dual data rate memory. Running it at 80MHz or 100MHz is > very feasible IMHO. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- hmm enterpoint Press Release promotes the HB2 for: "aircraft, automotive, shipping and rail applications." would you recommend to design in a product with DDR3 and disabled DLL for aerospace use? for development it sure may be ok. AnttiArticle: 138364
On Tue, 17 Feb 2009 08:49:31 -0800 (PST), rickman wrote: [...] >Oh, one other caution, the fact that you program works with any given >tool does not mean it has been written correctly with respect to the >rules of VHDL. Tools often have "features" where they accept >constructs that are not actually correct and won't work on other >tools. But maybe that has gone by the wayside. I haven't been >pushing that issue in a while. To be fair to the tools, it is rare these days to get significant differences among VHDL _simulators_ except on truly trivial matters - for example, ModelSim tolerates time literals without a space between the number and the unit, such as 10ns, while VHDL officially demands the space like 10 ns. But we have had some interesting discussions recently about illegal VHDL constructs that got through XST compilation without error or warning. So Rick's caution is noteworthy. And it is ALWAYS a good idea to compile and elaborate your code in a simulator before letting the synthesis tool loose on it, even if you're one of those scary people who don't believe in simulation... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138365
Hello, Xilinx provides IBIS files for the spartan (and other) devices. In these files the IBIS model of each possible IO driver type is given. But because the IO can be configured, there is no fixed IBIS for a completed design. After P&R, there is a pin mapping file which tells which pin has which IO standard and drive strength. Together with the IBIS file per IO type, it seems a fairly simple task of generating a specific IBIS file for the completed design. Is there an option in ISE or a separate tool to generate such an IBIS file? The task seems so simple, I'm tempted to try it myself. But that would be a waste of effort if the tool already exists. :-) -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) When some people discover the truth, they just can't understand why everybody isn't eager to hear it.Article: 138366
Antti <Antti.Lukats@googlemail.com> wrote:
>On Feb 17, 6:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> "koethe.daniel...@googlemail.com" <dkoe...@web.de> wrote:
>> >Hello Antti,
>> >on the webpage is a .ucf file available, but this contains NOT the
>> >DDR3-SDRAM pins.
>>
>> >You are right, spartan-3A DSP does not support DDR3-Voltage Levels.
>>
>> >Use the SSTL18_[I,II] at VCCO=3D1.5V and Vref=3D0,75V should be possible=
>,
>> >but nobody guarantees the IO-Timing and Voltage Levels.
>>
>> >But there is a second challenge. The maximal clock cycle with DDR3-
>> >SDRAM DLL enabled is 3.3 ns (~300 Mhz) this should be above any the
>> >Spartan-3A Memory-Controllers.
>>
>> >Micron Datasheet:
>> >http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb%20DDR3%20SDRA...
>>
>> >This DLL can disabled, but the relationchip between clk and data
>> >output delay is lost. Second you must disable the ODT (On Die
>> >Termination).
>>
>> If you disable the DLL, the clock range of DDR3 is very wide. Actually
>> much wider when using DDR or DDR2 memory. So it makes perfect sense to
>> use DDR3 on an FPGA because its lower power and easier to design and
>> still have dual data rate memory. Running it at 80MHz or 100MHz is
>> very feasible IMHO.
>>
>> --------------------------------------------------------------
>
>hmm
>
>enterpoint Press Release promotes the HB2 for:
>"aircraft, automotive, shipping and rail applications."
>
>would you recommend to design in a product
>with DDR3 and disabled DLL for aerospace use?
As long as it meets timing and its operation is more or less
guaranteed by the manufacturor. Micron is not recommending operating
the memory with the DLL off, but they do specify the timing. Samsung
does the same. It seems the DDR3 devices operate similar with some
timing restrictions when the DLL is off. The biggest problem seems
that Jedec didn't specify the timing requirements with the DLL off.
This potentially kills interoperability between memories.
Back to the real world. Some DDR3 controllers require to read/write
the memory before enabling the DLL for timing calibrations. In other
words if the memory can't be read/written reliably with the DLL off
the memory might not work in every situation.
But lets see what John has to say about this.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 138367
I'm trying to run through simulation of the PIO example given with
Xilinx PCIe endpoint block plus. However, when I run modelsim with
the .do file given in the example, I get:
vmap work {C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/
pciex4/simulation/functional/work}
# Copying c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied c:\modeltech_pe_6.5\win32pe/../modelsim.ini to
modelsim.ini.
# Updated modelsim.ini.
vlib work
# ** Warning: (vlib-34) Library already exists at "work".
vmap work
# Reading modelsim.ini
# "work" maps to directory C:/Documents and Settings/PoojanW/My
Documents/PCIeEPBP/pciex4/simulation/functional/work.
vcom -work work -f board_rtl.f
# Model Technology ModelSim PE vcom 6.5 Compiler 2009.01 Jan 22 2009
# -- Loading package standard
# ** Error: ../../example_design/xilinx_pci_exp_ep.v(1): near "/":
syntax error
# ** Error: ../../../pciex4.v(1): VHDL Compiler exiting
# c:/modeltech_pe_6.5/win32pe/vcom failed.
(For illustration, I executed the .do file manually line by line).
I don't know much about ModelSim (thus the post), but it seems like it
thinks ../../example_design/xilinx_pci_exp_ep.v is a VHDL file
(rather than Verilog). How do I fix this misunderstanding?
Article: 138368
Poojan Wagh wrote:
> I'm trying to run through simulation of the PIO example given with
> Xilinx PCIe endpoint block plus. However, when I run modelsim with
> the .do file given in the example, I get:
>
> vmap work {C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/
> pciex4/simulation/functional/work}
> # Copying c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini
> # Modifying modelsim.ini
> # ** Warning: Copied c:\modeltech_pe_6.5\win32pe/../modelsim.ini to
> modelsim.ini.
> # Updated modelsim.ini.
> vlib work
> # ** Warning: (vlib-34) Library already exists at "work".
> vmap work
> # Reading modelsim.ini
> # "work" maps to directory C:/Documents and Settings/PoojanW/My
> Documents/PCIeEPBP/pciex4/simulation/functional/work.
> vcom -work work -f board_rtl.f
> # Model Technology ModelSim PE vcom 6.5 Compiler 2009.01 Jan 22 2009
> # -- Loading package standard
> # ** Error: ../../example_design/xilinx_pci_exp_ep.v(1): near "/":
> syntax error
> # ** Error: ../../../pciex4.v(1): VHDL Compiler exiting
> # c:/modeltech_pe_6.5/win32pe/vcom failed.
>
> (For illustration, I executed the .do file manually line by line).
>
> I don't know much about ModelSim (thus the post), but it seems like it
> thinks ../../example_design/xilinx_pci_exp_ep.v is a VHDL file
> (rather than Verilog). How do I fix this misunderstanding?
You could try right-clicking on the project, selecting Properties, and
setting the preferred language to Verilog? I don't know if this will
help, but it's worth a try,
Alan
--
Alan Fitch
http://www.doulos.com
Article: 138369http://www.aipst.com/aips7103.tar.gz http://www.aipst.com/AIPS7103.pdfArticle: 138370
On Feb 17, 4:19=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > But we have had some interesting discussions recently about > illegal VHDL constructs that got through XST compilation > without error or warning. =A0So Rick's caution is noteworthy. > And it is ALWAYS a good idea to compile and elaborate your > code in a simulator before letting the synthesis tool > loose on it, even if you're one of those scary people who > don't believe in simulation... > -- > Jonathan Bromley, Consultant That is always a good idea. I often will run synthesis on my code while still in the simulation stage just because the two tools with catch different types of errors. No point in finding an error in synthesis after you are done with simulation because you will just have to go back and verify your simulation again to make sure your fix didn't break anything. RickArticle: 138371
On 17 f=E9v, 15:16, Allan Herriman <allanherri...@hotmail.com> wrote: > Gabor <ga...@alacron.com> wrote in news:e0edd268-99d3-44de-b126- > 90be94098...@m15g2000vbp.googlegroups.com: > > > > > On Feb 16, 5:37 am, Antti <Antti.Luk...@googlemail.com> wrote: > >> On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > >> > Hi everybody, > > >> > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > >> > 100 MHz) the FPGA doesn't start up ! > >> > whereas it is not the case for unencrypted one . Why ??? > >> > I need to configure the FPGA as quickly as possible. > > >> > Thanks. > > >> you need to use parallel mode :( > >> i think the 100mhz ecnrypted mode may not be supported, please > >> check the datasheets > > >> Antti > > > I've run into other problems at 100 MHz for unencrypted bitstreams > > as well. When the DONE signal is allowed to float high, the > > startup state logic can sample it in the threshold region > > (yes the chip samples the pin unless you set "Internal Done Pipe") > > and lock up. I solved this using the internal done pipe, but > > another recommendation was to "Drive Done High". My external > > DONE pullup was 330 ohms as recommended, but at 100 MHz, this > > is not fast enough. Another approach to fix this might be to > > slow down CCLK at or near the end of the bitstream. > > The last time I looked into this (Virtex2?), the specification for > maximum frequency with encryption wasn't specified in the datasheets. > The figure was specified in some obscure app note, and was something like > 10MHz, much lower than the frequency allowed without encryption. > > Things may have improved with more recent FPGA families though. > > Regards, > Allan Hi ! I guess that decryption is done at the same frequency as the config rate, isent it ?Article: 138372
On 16 f=E9v, 11:37, Antti <Antti.Luk...@googlemail.com> wrote: > On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > > Hi everybody, > > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > > 100 MHz) the FPGA doesn't start up ! > > whereas it is not the case for unencrypted one . Why ??? > > I need to configure the FPGA as quickly as possible. > > > Thanks. > > you need to use parallel mode :( > i think the 100mhz ecnrypted mode may not be supported, please > check the datasheets > > Antti hello Antii, For encryption I am limited to x8 parallel mode, whereas for unencrypted one I could use x16 and x32 bus. Why ? There is a compromise between security and rapidity .Article: 138373
On Feb 18, 10:31=A0am, dajjou <swissiyous...@gmail.com> wrote: > On 16 f=E9v, 11:37, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On Feb 16, 12:16 pm, dajjou <swissiyous...@gmail.com> wrote: > > > > Hi everybody, > > > > When configuring my Virtex 5 with encrypted bitstream (CCLK rate is > > > 100 MHz) the FPGA doesn't start up ! > > > whereas it is not the case for unencrypted one . Why ??? > > > I need to configure the FPGA as quickly as possible. > > > > Thanks. > > > you need to use parallel mode :( > > i think the 100mhz ecnrypted mode may not be supported, please > > check the datasheets > > > Antti > > hello Antii, > > =A0For encryption I am limited to x8 parallel mode, whereas for > unencrypted one I could use x16 and x32 bus. Why ? There is a > compromise between security and rapidity . yes there is AnttiArticle: 138374
Hi, our development workstation is getting old and the project is getting bigger. We need to run more long modelsim simulations and each synthesis run take 20 minutes in ISE on a spartan-3A DSP 3400 which is only half full. It's a long time since I put together a maximum-performance computer and I am not up to date on the latest CPUs. Our IT is not of much help since they care for mobile phones and laptops and windows networks. We run our FPGA development on Linux and 3 people share one workstation for design, simulation and synthesis. It is most likely only one person who is doing heavy sim and synth at a time, but with tools like SmartXplorer it is nice to have as many cores or machines as possible to run many jobs in parallel. Are the new Nehalems (core i7) that much better than core 2 that the extra price is justified? A 4-core is a natural decision, but would an 8-core be better, or will 8 modelsim jobs just tie down disk and memory? Will DDR3 memory have an advantage over DDR2 memory for FPGA type work? I hope somebody who have just upgraded would share some of their experience. Kind regards, -- Svenn
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