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Messages from 137275

Article: 137275
Subject: Which revision control do fpga designers use (2009)
From: Svenn Are Bjerkem <svenn.bjerkem@googlemail.com>
Date: Wed, 7 Jan 2009 04:14:37 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,
found a thread on revision control from 2001 here, but obviously some
of the newer tools weren't available back then. We currently use
Subversion for anything and I find it kind of awkward to use for RTL.
Obvious alternatives are CVS and git. Have people found new favourite
tools since then?

Also configuration management has become a buzzword. Any favourite
tools in this category?

--
Svenn

Article: 137276
Subject: Re: Which revision control do fpga designers use (2009)
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 07 Jan 2009 13:49:58 +0100
Links: << >>  << T >>  << A >>
Svenn Are Bjerkem <svenn.bjerkem@googlemail.com> writes:

> of the newer tools weren't available back then. We currently use
> Subversion for anything and I find it kind of awkward to use for RTL.

Would you care to elaborate?

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 137277
Subject: Re: Which revision control do fpga designers use (2009)
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 07 Jan 2009 15:03:30 +0100
Links: << >>  << T >>  << A >>
Andreas Ehliar <ehliar-nospam@isy.liu.se> writes:

> I'm using SVN as well. I think the only real problem is when used in
> conjunction with ISE (because ISE's config files are mostly binary

So it's more an ISE rather than a RTL problem. I've been using SVN
with Altera, Xilinx and several ASIC based designs. I typically use a
Make or Tcl type of flow and find SVN to fit wery well. I use mostly
Emacs for writing HDL, programs, scripts, documentation (latex),
e-mail, news (like now). 

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 137278
Subject: Re: Which revision control do fpga designers use (2009)
From: Jan <1@2.3>
Date: Wed, 07 Jan 2009 15:18:15 +0100
Links: << >>  << T >>  << A >>
Svenn Are Bjerkem wrote:
> Hi,
> found a thread on revision control from 2001 here, but obviously some
> of the newer tools weren't available back then. We currently use
> Subversion for anything and I find it kind of awkward to use for RTL.
> Obvious alternatives are CVS and git. Have people found new favourite
> tools since then?
Try to give TortoiseSVN a go. It's very powerful and open source.

Regards
   Jan

Article: 137279
Subject: Re: Which revision control do fpga designers use (2009)
From: Chris Maryan <kmaryan@gmail.com>
Date: Wed, 7 Jan 2009 06:51:29 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 7, 4:39=A0am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:
> On 2009-01-07, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote:
>
> > Hi,
> > found a thread on revision control from 2001 here, but obviously some
> > of the newer tools weren't available back then. We currently use
> > Subversion for anything and I find it kind of awkward to use for RTL.
> > Obvious alternatives are CVS and git. Have people found new favourite
> > tools since then?
>
> I'm using SVN as well. I think the only real problem is when used in
> conjunction with ISE (because ISE's config files are mostly binary
> instead of text). To work around this (and to gain other advantages)
> I'm using a Makefile based build system for larger projects and a
> simple synthesis script for smaller projects (where it doesn't matter
> if everything has to be resynthesized every time).
>
> Anyway, I'm not involved in projects which has lots of participants,
> so I can't vouch for SVN:s greatness for HDL code in large projects,
> but it has worked very well for us when developing HDL code for
> various courses and research projects. (Around 3-5 developers who
> fiddle with the code occasionally.)
>
> /Andreas

We use CVS, which isn't great, but it gets the job done. I use the
Tortoise shell over top of that personally, because I'm a GUI kind of
guy. The trick is to get all your configuration files into a text
format. I don't use any of the ISE configuration utilities, maybe
occasionally to help guide what I'm doing. But everything else is is
captured in various constraint files or the synplify project file.

Our build is pretty straightforward. I use /bat files, others use
make, tcl, perl, etc.

Then it's all text and you can check in whatever is needed.

Chris

Article: 137280
Subject: Re: Which revision control do fpga designers use (2009)
From: Charles Gardiner <invalid@invalid.invalid>
Date: Wed, 07 Jan 2009 16:23:53 +0100
Links: << >>  << T >>  << A >>
Hi,

I converted my repository to subversion about four years ago (from cvs)
and find it great. My code base is a wide mix of VHDL/Verilog/C/C++. As
regards FPGA projects, all four main vendors but in the last on and a
half years with a slant towards Lattice.

I have found the properties (principally svn:externals) very helpful in
reusing code within other projects, once you get the directory structure
right. With the svn:externals settings I can keep track of which tagged
sub-block versions are contained in each project delivered, which I
suppose is the first stage of configuration management.
I then have a java-based workflow on top of everything to generate my
make files, top-level testbenches, Lattice Project Files etc.

In comparison, some of my customers use clearcase or synchronicity but I
can't say I find either of them better. I suppose there might be some
advantages for larger corporations with multi-site hosting etc.

Article: 137281
Subject: Re: Which revision control do fpga designers use (2009)
From: Alex Colvin <alexc@TheWorld.com>
Date: Wed, 7 Jan 2009 15:51:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
I've used CVS and bzr, both for small projects. I like bzr.

In general, I check in source and configuration files, enough that I can
reconstruct the project.

I also check in the *.bit files for quick regression testing. And the
*.ise file for quick recovery when I've screwed up the configuration
options. Also the *.syr file from XST, just so I can track resources. But
these ISE files are treated as disposable, since I seem to occasionally
get the project completely hosed, and have to reconstruct it from the HDL 
sources.

ISE uses lots of intermediate files and caches that don't get cleaned up,
and sometimes get locked. It's important to not include these.

-- 
	mac the naf

Article: 137282
Subject: Re: Which revision control do fpga designers use (2009)
From: Chris Maryan <kmaryan@gmail.com>
Date: Wed, 7 Jan 2009 08:40:42 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 7, 9:51=A0am, Chris Maryan <kmar...@gmail.com> wrote:
> On Jan 7, 4:39=A0am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:
>
>
>
>
>
> > On 2009-01-07, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote:
>
> > > Hi,
> > > found a thread on revision control from 2001 here, but obviously some
> > > of the newer tools weren't available back then. We currently use
> > > Subversion for anything and I find it kind of awkward to use for RTL.
> > > Obvious alternatives are CVS and git. Have people found new favourite
> > > tools since then?
>
> > I'm using SVN as well. I think the only real problem is when used in
> > conjunction with ISE (because ISE's config files are mostly binary
> > instead of text). To work around this (and to gain other advantages)
> > I'm using a Makefile based build system for larger projects and a
> > simple synthesis script for smaller projects (where it doesn't matter
> > if everything has to be resynthesized every time).
>
> > Anyway, I'm not involved in projects which has lots of participants,
> > so I can't vouch for SVN:s greatness for HDL code in large projects,
> > but it has worked very well for us when developing HDL code for
> > various courses and research projects. (Around 3-5 developers who
> > fiddle with the code occasionally.)
>
> > /Andreas
>
> We use CVS, which isn't great, but it gets the job done. I use the
> Tortoise shell over top of that personally, because I'm a GUI kind of
> guy. The trick is to get all your configuration files into a text
> format. I don't use any of the ISE configuration utilities, maybe
> occasionally to help guide what I'm doing. But everything else is is
> captured in various constraint files or the synplify project file.
>
> Our build is pretty straightforward. I use /bat files, others use
> make, tcl, perl, etc.
>
> Then it's all text and you can check in whatever is needed.
>
> Chris- Hide quoted text -
>
> - Show quoted text -

Quick addendum regarding the project build: using the ISE tools from
the command line is very easy. A typical build is just a single
execution of ngdbuild, map, par, trce and then bitgen. The command
line options for each are fairly simple and map directly to the
options you set for yor build in ISE. There's an option in ISE
somewhere to get it to show you what the command line version of your
last build is, you can use that as a starting point. Then copy it all
to a script file and you're set - and you can check it into a text
only revision control system.

Chris

Article: 137283
Subject: Re: MAX7000 power and slew rate control
From: MarkAren <markaren10@yahoo.com>
Date: Wed, 7 Jan 2009 08:41:00 -0800 (PST)
Links: << >>  << T >>  << A >>
Arnim,

Many thanks, just the job.

I have been looking everywhere for these.

Regard, Mark

On Jan 6, 10:42=A0am, Arnim <clv.5.min...@spamgourmet.com> wrote:
> Mark,
>
> > The data sheet for the MAX7k implies that every macro cell has a Turbo
> > bit - is there a global setting to set the whole device into low power
> > mode by default ?
>
> > Any other places I should be poking about in Quartus to find more
> > power saving features ?
>
> I usually apply the following settings in the project's qsf file
> (EPM7032S and EPM7064S)
> =A0 set_global_assignment -name SLOW_SLEW_RATE ON
> =A0 set_global_assignment -name AUTO_TURBO_BIT OFF
>
> Also found in "More Settings..." from the Fitter Settings pane.
>
> They globally enable slow slew rate at the outputs and switch off the
> turbo bits for all LCELLs. Fitter provides feedback on these settings in
> the .fit.rpt file as "Cells using turbo bits x / 64" and the "Output
> Pins" listing.
> I found that these settings influence the self heating of the CPLD to
> some extent. However, I've never bothered to actually measure the
> current consumption.
>
> Arnim


Article: 137284
Subject: Re: beginner synthesize question - my debounce process won't
From: jleslie48 <jon@jonathanleslie.com>
Date: Wed, 7 Jan 2009 09:02:47 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 6, 7:48 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> ... notice the assignment outside the "if CLK..." statement?
>
> You have 2 options:
> (a) restore SIGNAL_OUT_TEMP to the sensitivity list;
> (b) move the assignment where it belongs, outside the process.
> Then it is a separate parallel process sensitive only to SIGNAL_OUT_TEMP
> (but a trivial one).
>
> - Brian

Brian,

Confirmed and thank you.  That makes perfect sense.  This is the
fix I tried:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    08:06:38 12/31/2008
-- Design Name:
-- Module Name:    VhdlModule1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity VhdlModule1 is
	port(	CLK 			: in std_logic;
			SIGNAL_IN	: in std_logic;
			SIGNAL_OUT	: out std_logic);
end VhdlModule1;


architecture Behavioral of VhdlModule1 is

constant DEBOUNCE_COUNT : integer := 5;
signal SIGNAL_OUT_TEMP 	: std_logic := '0';

begin

P1: process (CLK) --, SIGNAL_IN, SIGNAL_OUT_TEMP)
variable mycount : integer := 0;
begin
	if (CLK = '1' and CLK'event ) then --{1
   	if (SIGNAL_OUT_TEMP /= SIGNAL_IN) then --{2
		    mycount := mycount + 1;
		    if (mycount >= DEBOUNCE_COUNT) then  --{3
			     SIGNAL_OUT_TEMP <= SIGNAL_IN;
			     mycount := 0;
		        end if; --3}
	    else
		   mycount := 0;
       end if; --2}

	end if; --1}

end process P1;

SIGNAL_OUT <= SIGNAL_OUT_TEMP;       --line 62

end Behavioral;
----------------------------------------------------------------------------------

Note line 62 is the old line 56 but now has moved outside the domain
of the process p1. So now that line is a bit of concurrent logic, and
while
concurrent logic is generally to be avoided, in this case as it is a
simple
output assignment its clocking is not required to be exact.

The error message makes sense now; SIGNAL_OUT was "sensitive" to the
value SIGNAL_OUT_TEMP, but I never declared it formally in the
sensitivity
list.



From rgaddi@technologyhighland.com Wed Jan 07 09:22:28 2009
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Date: Wed, 7 Jan 2009 09:22:28 -0800
From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: Re: Which revision control do fpga designers use (2009)
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References: <46d1f79c-4f9a-45a7-932a-1cb4c2ad0128@i24g2000prf.googlegroups.com>
	<slrngm9au1.f36.ehliar-nospam@sabor.isy.liu.se>
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On Wed, 7 Jan 2009 09:39:39 +0000 (UTC)
Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote:

> On 2009-01-07, Svenn Are Bjerkem <svenn.bjerkem@googlemail.com> wrote:
> > Hi,
> > found a thread on revision control from 2001 here, but obviously
> > some of the newer tools weren't available back then. We currently
> > use Subversion for anything and I find it kind of awkward to use
> > for RTL. Obvious alternatives are CVS and git. Have people found
> > new favourite tools since then?
> 
> I'm using SVN as well. I think the only real problem is when used in
> conjunction with ISE (because ISE's config files are mostly binary
> instead of text). To work around this (and to gain other advantages)
> I'm using a Makefile based build system for larger projects and a
> simple synthesis script for smaller projects (where it doesn't matter
> if everything has to be resynthesized every time).
> 
> Anyway, I'm not involved in projects which has lots of participants,
> so I can't vouch for SVN:s greatness for HDL code in large projects,
> but it has worked very well for us when developing HDL code for
> various courses and research projects. (Around 3-5 developers who
> fiddle with the code occasionally.)
> 
> /Andreas

Just said everything that I was going to.  Especially with TortoiseSVN
as an interface into the system, I really find Subversion to be plenty
good enough to check in/out my VHDL, Xilinx schematic entry files
(text, underneath it all), configuration option text files, Makefiles,
and a few pre-post processing scripts.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 137285
Subject: UPDATE: HSMC General Purpose Interface Board, example FPGA design and Excel interface
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 7 Jan 2009 17:29:23 -0000
Links: << >>  << T >>  << A >>
At the end of November we released the HSMC GPIB, this provides much
needed functionality to any Altera dev kit with an HSMC connector
including....

8 * 10 bit ADC Inputs
8 * 10 bit DAC Outputs
2 * General Purpose 8 bit Digital IO ports
3 * RS232 Interfaces
2 * RS484 Interfaces
3 * One Wire Interfaces (2 of these can be combined for 5V I2C communications, all 3 can be used as
jumper selection inputs)
Micro SD card socket (SPI lines connected)
Header for an FTDI Vinculum VDIP1 or pin compatible NSD FT245R USB slave board, this can also be
used as a 16 bit general purpose digital IO header.
8 * LEDs
2 * SPI Interfaces


We have since released the USB interface board that used the FT245R use with the GPIB.

A user guide was initially posted, this has been followed with an example
FPGA project with driver modules including the FT245R interface.

This is probably a useful example design for anyone starting in FPGA design.

An small example Excel app has been posted, this demonstrates how the
board (or anything else) can easily be driven from Excel via a PC's serial port.

Details at...

http://www.nialstewartdevelopments.co.uk/products.htm


We have a USB interface board based on the new FTDI FT2232H device in the pipeline. This
will plug in the GPIB USB socket and should allow data transfers at 25M Byte/second.


Nial Stewart


----------------------------------------------------------
Nial Stewart Developments Ltd        Tel: +44 131 516 8883
32/12 Hardengreen Business Park      Fax: +44 131 663 8771
Dalkeith, Midlothian
EH22 3NX
www.nialstewartdevelopments.co.uk








Article: 137286
Subject: Re: beginner synthesize question - my debounce process won't
From: jleslie48 <jon@jonathanleslie.com>
Date: Wed, 7 Jan 2009 09:36:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 6, 8:21 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Tue, 6 Jan 2009 15:24:31 -0800 (PST), jleslie48
>
>
>
> <j...@jonathanleslie.com> wrote:
> >">for example in c:
> >>x = 0;
> >>While (x < 10) {
> >>   x++;
> >>   // do something 10 times
> >>  }//while loop 1
>
> >>This one in a VHDL process could translate successfully; however it
> >>will generate ten identical instances of "do something"; possibly with a
> >>very long combinatorial path through 10 strings of gates... "
> >this doesn't make sense to me.  ~will generate ten identical instances
> >of "do something"~
> >it can't be that raw.  what if that loop was (x< 10000000)?   it can't
> >simply make yyy copies
> >of the same line by brute force. YOu'd fill your memory in 2 seconds.
>
> Ohhhh yes it can!  you'd fill your FPGA, sure.
> But I said it would work; not that it was always a good idea!
>
> Now if you wanted to generate a single instance of "do_something" which
> took 10 clock cycles, you would use a different pattern; possibly with a
> "wait for rising_edge(clk)" inside the while loop. Or in the process
> style you have seen so far, maintain a separate counter to know when
> you're done.
>
> One thing we don't have, yet, is any semi-automatic way to combine both;
> unroll your loop to 1000 parallel instances, and count 10000 cycles.
> That level of detail you have to handle yourself. Not just the
> compromise; how fast do you need it, and how big is your FPGA? but the
> execution details.
>
> >and what if the initial
> >value of x was not a "synthesize" fixed value?   what if :
>
> >-- read x from a UART
>
> >-- for x number of times
> >    -- do something.
>
> >then there would be no way to make the right number of instances at
> >synth time.
>
> This is a good question. The short answer is that x has to be locally
> static, since you can't (yet!) grow more hardware at runtime.
>
> So transform the problem into something achievable.
>
> The usual pattern is to agree an upper bound on x, and implement that
> upper bound in hardware, executing do_something conditional on the
> actual value.
>
> constant x_max:integer := 15;
>
> for i in 1 to x_max loop
>   if i < x then
> ... No, it's better, safer and tidier to use the type system properly:
>
> subtype x_type is integer range 0 to 15;
> signal x : x_type;
>
> -- this is inside a process of course!
> for i in x_type loop
>   if i < x then
>     do_something;
>   end if;
> end loop;
>
> If do_something is synthesisable, so is this.
	end if; --1}


>
> - Brian

You still have me scratching my head on this. Lets look at my example:


 if (mycount >= DEBOUNCE_COUNT) then  --{3
     SIGNAL_OUT_TEMP <= SIGNAL_IN;
     mycount := 0;
     end if; --3}

in this code, DEBOUNCE_COUNT is a constant 5, so are you saying
that the lines:
     SIGNAL_OUT_TEMP <= SIGNAL_IN;
     mycount := 0;

are repeated 5 times?

or this is fundamentally different than a while loop by the nature of
using IF instead of WHILE?

In other words, if I re-write my repeat 10 loop as such:

looper10_proc: process (CLK,RESET)
variable icount : integer := 0;
begin
   if (reset = SWITCH_ON) then
         icount := 0;
    elsif (CLK = '1' and CLK'event ) then --{1
   	if (icount <= 10 ) then --{2
		    icount := icount +1;
                    -- do that same something
       end if; --2}

    end if; --1}

end process looper_10_proc;

I think I'm back to keeping the hardware in mind at all times....


Article: 137287
Subject: Re: DFFR using DFF (only, may be extra gates)
From: jprovidenza@yahoo.com
Date: Wed, 7 Jan 2009 09:40:47 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 5, 10:28=A0am, John Eaton <no_s...@spam.com> wrote:
> John Eaton wrote:
> > santhosh_h...@yahoo.com wrote:
> >> Hi,
>
> >> I know DFF is:
>
> >> module DFF(d,clk,q) ;
> >> =A0 =A0 =A0input d, clk ;
> >> =A0 =A0 =A0output reg q ;
>
> >> =A0 =A0 =A0always @(posedge clk)
> >> =A0 =A0 =A0 =A0 =A0 =A0q<=3D d ;
> >> endmodule
>
> >> Now I need to implement ASYNCHRONOUS RESET flip flop
> >> using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
>
> >> The implemented circuit MUST WORK AS FOLLOWS:
>
> >> module DFFR(d,clk,r, q) ;
> >> =A0 =A0 =A0input d, clk,r ;
> >> =A0 =A0 =A0output reg q ;
>
> >> =A0 =A0 =A0always @(posedge clk or posedge r)
> >> =A0 =A0 =A0 =A0 =A0 if (r) q <=3D 0 ;
> >> =A0 =A0 =A0 =A0 =A0 else =A0q<=3D d ;
> >> endmodule
>
> >> Please give the code or diagram. I am curious about this.
>
> >> Sant
>
> > My first question is where does your reset (r) come from? If it comes
> > from an external pin then it will be difficult to design something that
> > works if reset pulses and is gone before the first clock edge or starts
> > out active so that you never see a rising edge.
>
> > But if you do that then your circuit can't work because the reset is no=
t
> > synchronized to the clock and you will not meet setup/hold time. You
> > have to have a filter on the reset to meet timing. Make sure the filter
> > has at least two stages to sync reset to the clock.
>
> > If you filter your reset signal then your design becomes easy.
>
> > module DFFR(d,clk,r, q) ;
> > =A0 =A0 =A0 input d, clk,r ;
> > =A0 =A0 =A0 output wire q ;
>
> > =A0 =A0 =A0 reg q_p;
>
> > =A0 =A0 =A0 always @(posedge clk )
> > =A0 =A0 =A0 =A0 =A0 =A0if (r) q_p <=3D 0 ;
> > =A0 =A0 =A0 =A0 =A0 =A0else =A0 q_p <=3D d ;
>
> > =A0 =A0 =A0assign q =3D q_p & r;
>
> > =A0endmodule
>
> > But even this is overkill. If your q output goes to another flop that
> > also has a sync reset then the only time that you gate the q output is
> > during reset when the output is never used because the receiving flop i=
s
> > being reset.
>
> > You can leave out all the output gating unless the signal is an output
> > that leaves the chip. You can gate all those signals in a wrapper and
> > never touch your core rtl logic.
>
> > John Eaton
>
> Missed an inversion. I'm used to always using active low async resets.
>
> module DFFR(d,clk,r, q) ;
> =A0 =A0 =A0 =A0 input d, clk,r ;
> =A0 =A0 =A0 =A0 output wire q ;
>
> =A0 =A0 =A0 =A0 reg q_p;
>
> =A0 =A0 =A0 =A0 always @(posedge clk )
> =A0 =A0 =A0 =A0 =A0 =A0 =A0if (r) q_p <=3D 0 ;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0else =A0 q_p <=3D d ;
>
> =A0 =A0 =A0 =A0assign q =3D q_p & (~r);
>
> =A0 =A0endmodule

I don't see how this logic would work properly.  Assume q_p is a 1,
then pulse
the reset signal for a very short time.

In a real DFFR, the flop would clear and stay cleared.
In this code, the output will pulse low then go back to a high
state (assuming the clock has not wiggled while reset is asserted).

John Providenza

Article: 137288
Subject: Re: beginner synthesize question - my debounce process won't
From: Andy <jonesandy@comcast.net>
Date: Wed, 7 Jan 2009 11:11:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 5, 6:14=A0pm, rickman <gnu...@gmail.com> wrote:
> If you make mycount a
> signal, then the input to everything within the process will be the
> direct output of the register and the resulting circuit will be very
> clear. =A0

While the structure of the circuit may be more clear, the behavior is
not. Take for example:

This snippet, using a signal for mycount:
  mycount <=3D mycount + 1;
  if (mycount >=3D DEBOUNCE_COUNT) then
  ...
  end if;

is equivalent to this one (also using a signal for mycount):
  if (mycount >=3D DEBOUNCE_COUNT) then
  ...
  end if;
  mycount <=3D mycount + 1;

With variables, these two descriptions, which "read" differently,
would implement different behavior, and correspondingly different
circuitry. The latter example would result in the registered (clock-
cycle-delayed) version of mycount being compared to debounce_count.
Using variables in clocked processes allows you to choose where to put
registers and where to chain combinatorial paths together, without
having to use separate processes, or re-state complex expressions.

With signals, since updates are always postponed, all references are
the same relative to last update. We unkowingly simplify that to say
that a signal assigned in a clocked process is always a register*.
With variables, it is not the variable that implies a register or not,
it is each reference to it that determines whether a register is used,
and only for that reference. In other words, you can easily have
multiple references to the same variable, some of which imply a
register, others do not. Of course multiple registers implied from
multiple references to the same variable are combined into one
register.

The basic rule is that if the variable referenced was last updated in
a prior clock cycle, then a register must be used to "remember" the
value for that specific reference. Otherwise, the combinatorial value
is implied for that reference.

* The OP's final signal assignment outside the clocked if-statement is
not synthesizeable (at least not correctly) because it it is from
another signal (signal_out_temp). If however, signal_out_temp were a
variable, then it would be synthesizeable, at least by some tools.
Signals assigned from expressions of variable(s), after and outside
the clocked if-statement, result in registered references to the
variable(s) being combinatorially assigned to the output signal. If
there were operators or function calls in the expression, those would
be implemented combinatorially after the registered variable values.

For example:
if rising_edge(clk) then
  a :=3D ina;
  b :=3D inb;
  c <=3D a + b;
end if;

'c' is a register output with the sum of ina and inb on its input.

but in this example:
if rising_edge(clk) then
  a :=3D ina;
  b :=3D inb;
end if;
c <=3D a + b;

C is the output of the adder driven by registers with ina and inb on
their inputs.


I also noticed the OP's comments delineating the nested levels of if
statements. It should also be noted that if-statements can be labeled,
and if they are, the corresponding end if must include the label:

clock: if rising_edge(clk) then
  ...
end if clock;

The advantage of this over comments is that labels are checked and
enforced by the compiler; comments are not.

Andy

Article: 137289
Subject: Re: DFFR using DFF (only, may be extra gates)
From: John Eaton <no_spam@spam.com>
Date: Wed, 07 Jan 2009 12:16:25 -0800
Links: << >>  << T >>  << A >>
jprovidenza@yahoo.com wrote:
> On Jan 5, 10:28 am, John Eaton <no_s...@spam.com> wrote:
>> John Eaton wrote:
>>> santhosh_h...@yahoo.com wrote:
>>>> Hi,
>>>> I know DFF is:
>>>> module DFF(d,clk,q) ;
>>>>      input d, clk ;
>>>>      output reg q ;
>>>>      always @(posedge clk)
>>>>            q<= d ;
>>>> endmodule
>>>> Now I need to implement ASYNCHRONOUS RESET flip flop
>>>> using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
>>>> The implemented circuit MUST WORK AS FOLLOWS:
>>>> module DFFR(d,clk,r, q) ;
>>>>      input d, clk,r ;
>>>>      output reg q ;
>>>>      always @(posedge clk or posedge r)
>>>>           if (r) q <= 0 ;
>>>>           else  q<= d ;
>>>> endmodule
>>>> Please give the code or diagram. I am curious about this.
>>>> Sant
>>> My first question is where does your reset (r) come from? If it comes
>>> from an external pin then it will be difficult to design something that
>>> works if reset pulses and is gone before the first clock edge or starts
>>> out active so that you never see a rising edge.
>>> But if you do that then your circuit can't work because the reset is not
>>> synchronized to the clock and you will not meet setup/hold time. You
>>> have to have a filter on the reset to meet timing. Make sure the filter
>>> has at least two stages to sync reset to the clock.
>>> If you filter your reset signal then your design becomes easy.
>>> module DFFR(d,clk,r, q) ;
>>>       input d, clk,r ;
>>>       output wire q ;
>>>       reg q_p;
>>>       always @(posedge clk )
>>>            if (r) q_p <= 0 ;
>>>            else   q_p <= d ;
>>>      assign q = q_p & r;
>>>  endmodule
>>> But even this is overkill. If your q output goes to another flop that
>>> also has a sync reset then the only time that you gate the q output is
>>> during reset when the output is never used because the receiving flop is
>>> being reset.
>>> You can leave out all the output gating unless the signal is an output
>>> that leaves the chip. You can gate all those signals in a wrapper and
>>> never touch your core rtl logic.
>>> John Eaton
>> Missed an inversion. I'm used to always using active low async resets.
>>
>> module DFFR(d,clk,r, q) ;
>>         input d, clk,r ;
>>         output wire q ;
>>
>>         reg q_p;
>>
>>         always @(posedge clk )
>>              if (r) q_p <= 0 ;
>>              else   q_p <= d ;
>>
>>        assign q = q_p & (~r);
>>
>>    endmodule
> 
> I don't see how this logic would work properly.  Assume q_p is a 1,
> then pulse
> the reset signal for a very short time.
> 
> In a real DFFR, the flop would clear and stay cleared.
> In this code, the output will pulse low then go back to a high
> state (assuming the clock has not wiggled while reset is asserted).
> 
> John Providenza


Thats why you must filter your reset. The external reset could be a very 
short pulse but the filter will sync it to clk and stretch it to at 
least two clock periods. The first clock will reset the flop.


John Eaton





Article: 137290
Subject: Re: Classifying different kinds of FPGA optimizations
From: rickman <gnuarm@gmail.com>
Date: Wed, 7 Jan 2009 13:14:19 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 7, 12:51=A0am, nav_tiw...@rediffmail.com wrote:
> On Jan 6, 3:34=A0pm, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:
>
> > On 2009-01-05, Andy <jonesa...@comcast.net> wrote:
>
> > > Are you writing a paper on this or what?
>
> > Good guess. In fact, quite many of the papers I've been involved with
> > have mentioned "FPGA optimizations" somewhere without truly defining
> > it. Many other papers I have read also say that a design is (or sometim=
es
> > isn't) optimized for FPGAs. Besides, we talk about optimizing designs
> > for FPGAs here all the time.
>
> > I know what I'm doing to optimize my designs for FPGAs (as opposed to
> > optimizing a design for ASIC or just plainly optimizing a design
> > for a generic architecture), and I have seen many interesting ideas
> > on this group for example. Even so, I have never really seen a good
> > definition of "FPGA optimized".
>
> > > Small memories are often easier to use in FPGAs because most FPGA
>
> > How well I know... :) On the other hand, relatively small memories such
> > as register files (and I'm not thinking about the Cell processors 128x1=
28
> > bit register file here :)) can be implemented using standard cells with=
out
> > losing that much area. (And unless your volumes are huge you might even
> > gain by not having to worry about the extra verification cost required =
for
> > verifying a design with many custom blocks in it.)
>
> > Anyway, thanks for the comments.
>
> > /Andreas
>
> Hey
> I have one more point
> 7. Writing the Constraint File in a very logical and intelligent way.
> I believe Constraints play a major role in the design Optimizations
> and finally improves the Quality of result.

I agree and I also feel that vendors have largely ignored this aspect
of FPGA design.  They provide software to meet your timing
constraints, but they do nothing to help you set them up.  If you have
a design with complex timing constraints, there is no way to verify
that your constraints are interpreted the way you *think* they are.
So a corollary to this is to choose a vendor who helps you verify your
timing constraints are correct and not just that the software met
constraints that may not be correct.

Rick

Article: 137291
Subject: Re: beginner synthesize question - my debounce process won't
From: rickman <gnuarm@gmail.com>
Date: Wed, 7 Jan 2009 13:39:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 7, 2:11=A0pm, Andy <jonesa...@comcast.net> wrote:
> On Jan 5, 6:14=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > If you make mycount a
> > signal, then the input to everything within the process will be the
> > direct output of the register and the resulting circuit will be very
> > clear. =A0
>
> While the structure of the circuit may be more clear, the behavior is
> not. Take for example:
>
> This snippet, using a signal for mycount:
> =A0 mycount <=3D mycount + 1;
> =A0 if (mycount >=3D DEBOUNCE_COUNT) then
> =A0 ...
> =A0 end if;
>
> is equivalent to this one (also using a signal for mycount):
> =A0 if (mycount >=3D DEBOUNCE_COUNT) then
> =A0 ...
> =A0 end if;
> =A0 mycount <=3D mycount + 1;

I don't follow your assertion.  You get the same behavior from two
descriptions using signals and get two different behaviors using
variables.  Isn't one behavior more clear than two behaviors?   There
are lots of ways that different code can result in the same behavior.
That does not make any of these code examples more complex to
understand.  You stated some rules for determining what value is used
for variables and when registers are synthesized.  These rules are
much more complex than the rules for signals.  That was my point.

The OP is a beginner and I recommend that any beginner stick with
signals until they have mastered those rules.  Then they can add in
the confusion factor of variables.  I especially recommend this for
software people learning an HDL.  Signals are new to them and they
will do better to learn up front the parts of HDL that are different
from software.  Signals are required, variables are not.  Start with
the minimum that you need to learn, then branch out.

Rick

Article: 137292
Subject: Re: beginner synthesize question - my debounce process won't
From: rickman <gnuarm@gmail.com>
Date: Wed, 7 Jan 2009 13:52:48 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 6, 6:24=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
> ">for example in c:
>
> >x =3D 0;
> >While (x < 10) {
> > =A0 x++;
> > =A0 // do something 10 times
> > =A0}//while loop 1
> >This one in a VHDL process could translate successfully; however it
> >will generate ten identical instances of "do something"; possibly with a
> >very long combinatorial path through 10 strings of gates... "
>
> this doesn't make sense to me. =A0~will generate ten identical instances
> of "do something"~
> it can't be that raw. =A0what if that loop was (x< 10000000)? =A0 it can'=
t
> simply make yyy copies
> of the same line by brute force. YOu'd fill your memory in 2 seconds.
> and what if the initial
> value of x was not a "synthesize" fixed value? =A0 what if :
>
> -- read x from a UART
>
> -- for x number of times
> =A0 =A0 -- do something.
>
> then there would be no way to make the right number of instances at
> synth time.

This violates Rick's first rule of writing HDL code; "Write a
description of the hardware, not a program."

When you say you want to do something 10 times, what do you mean?  Are
you saying you want to use the same piece of hardware 10 times in
succession to do the same thing?  For example, pulse an output 10
times.  That can't be done in a simple loop.  You have to construct a
counter to count the iterations, you likely also have to have a
counter divide down the clock to measure the length of a pulse.  So
you "describe" the counters rather than expecting the tool to know
that a loop is supposed to count the usage of a piece of hardware.

Seriously, when you want to design hardware, always start with a block
diagram showing the various registered signals.  The logic can be
shown as other blocks like muxes or adders or just clouds.  They can
be easily synthesized.  But you need to specify where the registers
will be and that controls the structure of your design and code.

Loops are good for describing things that get done the same way, but
on different signals.  An example is a bit shifter.  You can say

A(n downto 1) <=3D A(n-1 downto 0);

This is simple and clear.  But I have seen people write,

  for i in n-1 downto 0 loop
    A(i+1) <=3D A(i);
  end loop;

This is not unclear and I am sure there are times when it is
preferred, especially when the range of i varies.  I may be reaching
beyond my experience as I don't know that a non-constant range for i
can be synthesized.

I tend to stick with simple constructs because they are most portable
and simple to understand.  If I have a need for a more complex
construct, I am not afraid of it, but I have found little need.

Rick

Article: 137293
Subject: Re: beginner synthesize question - my debounce process won't
From: rickman <gnuarm@gmail.com>
Date: Wed, 7 Jan 2009 14:06:20 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 7, 12:36=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> You still have me scratching my head on this. Lets look at my example:
>
> =A0if (mycount >=3D DEBOUNCE_COUNT) then =A0--{3
> =A0 =A0 =A0SIGNAL_OUT_TEMP <=3D SIGNAL_IN;
> =A0 =A0 =A0mycount :=3D 0;
> =A0 =A0 =A0end if; --3}
>
> in this code, DEBOUNCE_COUNT is a constant 5, so are you saying
> that the lines:
> =A0 =A0 =A0SIGNAL_OUT_TEMP <=3D SIGNAL_IN;
> =A0 =A0 =A0mycount :=3D 0;
>
> are repeated 5 times?
>
> or this is fundamentally different than a while loop by the nature of
> using IF instead of WHILE?

The IF is not a while.  The loop of a process is repeated on the same
hardware (process) on each clock tick.  Each time the process is run
an explicit loop repeats N times.  Very different.


> In other words, if I re-write my repeat 10 loop as such:
>
> looper10_proc: process (CLK,RESET)
> variable icount : integer :=3D 0;
> begin
> =A0 =A0if (reset =3D SWITCH_ON) then
> =A0 =A0 =A0 =A0 =A0icount :=3D 0;
> =A0 =A0 elsif (CLK =3D '1' and CLK'event ) then --{1
> =A0 =A0 =A0 =A0 if (icount <=3D 10 ) then --{2
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 icount :=3D icount +1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- do that same something
> =A0 =A0 =A0 =A0end if; --2}
>
> =A0 =A0 end if; --1}
>
> end process looper_10_proc;
>
> I think I'm back to keeping the hardware in mind at all times....

Good boy!!!

Remember that each process (that includes each line of concurrent
code) is a description of a piece of hardware that runs when an input
changes (implied in concurrent code or explicit in a process).  Every
line of code that is executed within a process is defining what the
hardware will do on that one trigger event.  If you want a process to
do 10 things on 10 different clock cycles, you need to give it a way
to know which clock cycle it is on (a counter perhaps) and then
describe those different behaviors.  That is what you have done in the
above code.  You use icount to tell what clock cycle you are on and
you use the IF statement to tell the process what to do on the
different clock cycles.  If you want to do something multiple times on
separate hardware (parallel operations) you can use an explicit loop
to define that.  Variables can be used in this case but will often
result in multiple copies of hardware.

HDL is complex and simple at the same time.  I recommend that you
think in terms of the hardware and then describe the hardware in the
HDL because that tends to take away the complex parts of the HDL and
you can use cookie cutters to create your code.  I've been doing this
for over 15 years and I am still using the cookie cutter method.
Others have been doing this for less time, but spend a higher
percentage of their time on HDL and so have learned more complex
methods that reduce their effort.  But they didn't learn those methods
the first day on the job.

Rick

Article: 137294
Subject: problems with symbols and how to debug Quartus block diagrams with Modelsim?
From: Frank Buss <fb@frank-buss.de>
Date: Thu, 8 Jan 2009 00:13:48 +0100
Links: << >>  << T >>  << A >>
I've tried to use block diagrams (BDF files) for simpler composing
sub-entities. This works nice and I even can create symbols from diagrams
(BSF files) and use it in higher-level diagrams. One problem with this is
that if I add some pins the the file, from which the symbol was generated
(which can be a VHDL file, too), this is not updated in the symbol file. I
can regenerate it, but if I change the arrangements of the pins to better
fit in a diagram, I have to do this again. Any ideas how to solve this? A
workaround, which works: I can edit the BSF files in a text-editor (it is
in a s-exp-format, like a Lisp-program) and add the additional pin
manually.

Today I've tried Modelsim (the free Altera version) and looks like it is a
good simulator, which can even set breakpoints in VHDL code and unlike the
integrated Quartus simulator, it supports VHDL testbenches with "wait for"
etc. But how can I test Quartus BDF entities with it? It is possible to
generate VHO files from the top-level entity, but then I don't see the VHDL
code of the sub-entities any more, because looks like if I have a main.bdf
file, which has the sub-entity foo.vhd, it is all generated in one big
main.vho file, with a special syntax for Modelsim, which doesn't make sense
to debug any more.

Setting breakpoints is nice, but not required. So I think I could define
the entity or diagram under test as a top-level entity, let Quartus create
the vho file and then start a testbench in Modelsim. But would be much
better, if I could create a project in Modelsim and specify the top-level
entities or diagram, and testbenches in this program, to avoid changing the
Quartus proejct all the time when I need to test another entity. Is there
an easy way to test diagrams with Modelsim? Maybe someone has written some
Tcl scripts to automate it?

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 137295
Subject: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Wed, 07 Jan 2009 23:30:39 +0000
Links: << >>  << T >>  << A >>
On Thu, 8 Jan 2009 00:13:48 +0100, Frank Buss wrote:

> Is there
>an easy way to test diagrams with Modelsim? Maybe someone has
> written some Tcl scripts to automate it?

In the version of Quartus I'm using (8.0, I'm behind the 
game as usual) you can choose menu File, Create/Update, 
Create HDL Design File for Current File.  This gives you
a plain VHDL entity/architecture pair with appropriate
component declarations and instances for all the blocks
in your diagram.  You can go the other way too - create
a symbol file from a VHDL design file.  I sometimes
do this when I'm stitching together a bunch of big 
VHDL blocks at the top level of a project, where a
schematic can sometimes make more sense than a VHDL
design that's just a dreary list of instances.
The resulting files are straightforward vanilla
VHDL much as you might write yourself; the only 
hiccup is that sometimes Quartus needs to create
internal nets if you have fed back an output port
into the design, so you get signals with silly names
like SYNTHESIZED_NET_28.

Certainly beats editing .BDF and .BSF files by hand :-)

Or have I missed your point?

cheers
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 137296
Subject: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
From: Frank Buss <fb@frank-buss.de>
Date: Thu, 8 Jan 2009 00:43:40 +0100
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:

> In the version of Quartus I'm using (8.0, I'm behind the 
> game as usual) you can choose menu File, Create/Update, 
> Create HDL Design File for Current File.  

With Quartus 8.1 this is possible, too.

> This gives you
> a plain VHDL entity/architecture pair with appropriate
> component declarations and instances for all the blocks
> in your diagram.

Maybe this could be a idea to use it with Modelsim. I just need to generate
the VHDL files (which is not always possible from BDF files, but for my
simple cases, used as a collection of sub-entites, it should be no proble).
Then I can create a Modelsim project and import these VHDL files. The only
drawback would be that I have to regenerate the VHDL files, if I change the
diagrams, but at least this is better than adjusting the top-level entity
in Quartus all the time when running different testbenches.

> You can go the other way too - create
> a symbol file from a VHDL design file.  I sometimes
> do this when I'm stitching together a bunch of big 
> VHDL blocks at the top level of a project, where a
> schematic can sometimes make more sense than a VHDL
> design that's just a dreary list of instances.

Yes, this is the way I use it, too. My problem was, that for nicer layout
of the diagrams, I edit the BSF files in the BSF GUI editor from Quartus
and move the pins to different locations. Then sometimes I need more ports
in my VHDL entity, from which the symbol file was created (or in a BDF
diagram, from which it is possible to generate symbols, too), but this is
not updated in the symbol file. After regnerating the symbol file, I have
to move the ports again, which was the reason why I edited the BSF files in
a text editor to add the ports.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 137297
Subject: Re: problems with symbols and how to debug Quartus block diagrams
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 07 Jan 2009 16:31:13 -0800
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> I think I could define
> the entity or diagram under test as a top-level entity, let Quartus create
> the vho file and then start a testbench in Modelsim. But would be much
> better, if I could create a project in Modelsim and specify the top-level
> entities or diagram, and testbenches in this program, to avoid changing the
> Quartus project all the time when I need to test another entity.

Have you played with the Quartus RTL viewer?
I use this to make .pdf block diagrams from my source code.
Note that modelsim works faster and easier with vhdl source
files than it does with .vho netlists.

> Is there
> an easy way to test diagrams with Modelsim? Maybe someone has written some
> Tcl scripts to automate it?

No, but there are editors that can work out the text
for your instances in the top level architecture.
Let the RTL viewer fuss with drawing the pins and wires,
and let modelsim and quartus share the same source files.

Good luck.

  -- Mike

Article: 137298
Subject: Re: problems with symbols and how to debug Quartus block diagrams
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 07 Jan 2009 16:31:38 -0800
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> I think I could define
> the entity or diagram under test as a top-level entity, let Quartus create
> the vho file and then start a testbench in Modelsim. But would be much
> better, if I could create a project in Modelsim and specify the top-level
> entities or diagram, and testbenches in this program, to avoid changing the
> Quartus project all the time when I need to test another entity.

Have you played with the Quartus RTL viewer?
I use this to make .pdf block diagrams from my source code.
Note that modelsim works faster and easier with vhdl source
files than it does with .vho netlists.

> Is there
> an easy way to test diagrams with Modelsim? Maybe someone has written some
> Tcl scripts to automate it?

No, but there are editors that can work out the text
for your instances in the top level architecture.
Let the RTL viewer fuss with drawing the pins and wires,
and let modelsim and quartus share the same source files.

Good luck.

  -- Mike

Article: 137299
Subject: Re: problems with symbols and how to debug Quartus block diagrams with Modelsim?
From: Frank Buss <fb@frank-buss.de>
Date: Thu, 8 Jan 2009 01:51:41 +0100
Links: << >>  << T >>  << A >>
Mike Treseler wrote:

> Have you played with the Quartus RTL viewer?

Yes, I have tried it, but maybe the wrong one? It shows many more enties
than I've coded in the VHDL file, e.g. generated glue logic and I don't
like how it layouts the components.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de



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