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Hi all, I'm working on a project with a virtex4 fx60 target. The project is pretty big, it needs about 65% of slices and 90% of BRAMs and 75% of DSP48. It requires many clocks (50MHz,25MHz,100MHz,200MHz), derived from a single DCM. Sometimes even changing little particulars the timing constraints are not respected any more. Often the constraints not respected are inside the parts instantiated from Xilinx IP-Cores like FFT or FIFO, so I don't know what to do to solve the problem. Which strategy should I use to try to get the timing constraints respected? Thanks for your attention.Article: 137351
GrIsH wrote:
> The books that i have read,...they suggest to prefer two process model
> for STATE MACHINE DESIGN
Yes. All the books say that.
......but the daybefore i
> think i read somewhere that people prefer one process model for FSM
> nowdays......
I do. Many don't.
> so what is the difference having two process or one process model for
> FSM other than ofcourse the presence or absence of combinational nx
> state decoder......
I find combinational processes annoying.
Many don't.
-- Mike Treseler
Article: 137352
On Thu, 8 Jan 2009 12:31:26 -0800 (PST), jleslie48
<jon@jonathanleslie.com> wrote:
>On Jan 8, 2:52 pm, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:
>
>>
>> >In other words, if I re-write my repeat 10 loop as such:
>>
>> >looper10_proc: process (CLK,RESET)
>> >variable icount : integer := 0;
>> >begin
>> > if (reset = SWITCH_ON) then
>> > icount := 0;
>> > elsif (CLK = '1' and CLK'event ) then --{1
>> > if (icount <= 10 ) then --{2
>> > icount := icount +1;
>> > -- do that same something
>> > end if; --2}
>>
>> > end if; --1}
>>
>> >end process looper_10_proc;
>>
>> As Rick says, good!
>> That is a good example of a pattern to iterate ten times with one
>> "do_something".
>>
>> - Brian
>
>My turing machine, language processing, LL(1) grammar, and compiler
>design Professors are turning over in their graves,
>but it seems to be a consensus that this is the way it works.
Why are they unhappy?
This is not so very different from the implementation of a round robin
scheduler (e.g. providing a "do_something" service to 10 processes) in a
software system, when you don't impose the straitjacket of a single
process on the design.
Sure, there are cleaner ways of hiding the details under an abstraction;
wrap the process in a component and you can do the same here. But
someone still has to implement those details.
You could ask if there is a better pattern to implement this.
There nearly is...
I previously suggested the possible use of "wait for rising_edge(clk)"
inside the while loop. Just for fun I got around to trying this last
night.
-- (A,B are 10-element 1D arrays of unsigned)
Scale_Vec: process
begin
wait for rising_edge(clk);
for i in A'range loop
-- wait for rising_edge(clk);
B(i) <= A(i) * Scale;
end loop;
end process;
in Xilinx XST 10.1.3 synthesises, as expected, to use 10 multipliers.
But with the Wait moved inside the loop (as commented out) it should use
one, and service each vector entry in turn. (Note: the above is
incomplete; you would need some externally visible synchronisation
mechanism to know when the n-cycle loop had finished!)
I don't see anything fundamentally impossible to synthesise; however XST
doesn't support this construct.
Next time I turn a Windows machine on I'll try it in Altera's free
edition.
I think the problem with synthesis is not so much the low level of the
language; but the low level at which it is normally used. Result: HW
engineers don't complain enough about poor synthesis support for useful
higher level constructs. So synthesis is only getting better slowly.
- Brian
Article: 137353Bob Smith wrote: > HT-Lab wrote: >> "Bob Smith" <usenet@linuxtoys.org> wrote in message > >>> I'd like to announce the availability of a Spartan 3E >>> FPGA development board that, while usable under Windows, >>> is particularly easy to use under Linux. > >> Any url? :-) > > Do'h! http://www.demandperipherals.com So what happened to baseboards 1-3? Looks good so far but you need to spruce up your technical marketing a bit. For a product like this I would expect to see: 1) A large enough photo of the board so that I could read the part numbers. 2) Downloadable user manual that explains how I can get a xilinx bit file that I generate into your board. This covers software installs and a walk thru for a download. 3) Board schematic. John EatonArticle: 137354
Hi, I have created "XBD" file for EDK that implements the wizard for Darnaw1. Download: http://secureasm.netsons.org/doku.php?id=xilinx:darnaw1 http://secureasm.netsons.org/files/Enterpoint%20Darnaw1%20EDK%20Board.rar Someone who owns the card could test it ? Thansk. Kappa.Article: 137355
"GrIsH" <girish_thesingh@hotmail.com> wrote in message news:1eb9b0a2-8a25-4bc3-a560-712d502fbe9e@w39g2000prb.googlegroups.com... > hi...... > > The books that i have read,...they suggest to prefer two process model > for STATE MACHINE DESIGN i.e sequential and combinational...... Textbooks are many times written by smart folks who haven't necessarily faced a deadline to get something working correctly so that product can be shipped though. Their priorities are different, they teach, do research and write, that's their job. > and iam > also follow two process model till nowdays...... Sorry to hear that. > but the daybefore i > think i read somewhere that people prefer one process model for FSM > nowdays...... Many do...but some also cling to and defend the two process approach. But even those who do and have done so for a while still can't verbalize anything that is actually better about that approach, mostly their reason boils down to being something that they are comfortable with. > so what is the difference having two process or one process model The difference is - One unneeded process - Less typing for the one process model - More chance for error in the two process model with the current design languages in use today. > for > FSM other than ofcourse the presence or absence of combinational nx > state decoder...... It goes even beyond just state machines, for the most part you should try to avoid any unclocked processes at all. Stick with concurrent signal assignments and a clocked process. Rather than preaching, I would suggest you simply take some simple two process state machine code that you have and convert it to a single process form (simulating it to make sure that the two actually perform the same thing). What you will find is that in the two process approach, 1. *You* need to make sure that every path through the process assigns something to every output of that process. 2. *You* need to make sure that every signal that is referenced in the process is in the sensitivity list. Neither of these applies when using the one process form. Violating either of these two principles will result in a situation where what you simulate will be different from what gets synthesized into a real part...that is a hugely bad situation to find yourself in since it means your best tool for finding functional problems (i.e. the simulator) is not reflecting the dysfunctional board that you've got to get working...and it's not the simulators fault, it's yours for violating the above rules and it's up to you to find that out, by sifting through synthesizer warning messages. If you want to do more work than is necessary, by all means stick with the two process approach but like I said, don't take my word for it, take an existing two process thing that you have and convert it to a single clocked process and see for yourself that there isn't much of a difference in how you actually write your code, but the end result you'll have more confidence in because it will not be possible to violate either of the above two principles. Kevin JenningsArticle: 137356
On Jan 10, 8:32=A0am, John Eaton <nos...@spam.com> wrote: > Bob Smith wrote: > > HT-Lab wrote: > >> "Bob Smith" <use...@linuxtoys.org> wrote in message > > >>> I'd like to announce the availability of a Spartan 3E > >>> FPGA development board that, while usable under Windows, > >>> is particularly easy to use under Linux. > > >> Any url? :-) > > > Do'h! =A0http://www.demandperipherals.com > > So what happened to baseboards 1-3? > > Looks good so far but you need to spruce up your technical marketing a > bit. For a product like this I would expect to see: > > 1) A large enough photo of the board so that I could read the part number= s. > > 2) Downloadable user manual that explains how I can get a xilinx bit > file that I generate into your board. This covers software installs and > a walk thru for a download. > > 3) Board schematic. > > John Eaton You should list your company and product at FPGA Central (http:// www.fpgacentral.com ). You can add a vendor and then product for FREE. It is a great place to get some exposure. Visit http://www.fpgacentral.com= /add -VikramArticle: 137357
On Jan 8, 3:31=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Jan 8, 2:52 pm, Brian Drummond <brian_drumm...@btconnect.com>
> wrote:
>
>
>
>
>
> > >In other words, if I re-write my repeat 10 loop as such:
>
> > >looper10_proc: process (CLK,RESET)
> > >variable icount : integer :=3D 0;
> > >begin
> > > =A0 if (reset =3D SWITCH_ON) then
> > > =A0 =A0 =A0 =A0 icount :=3D 0;
> > > =A0 =A0elsif (CLK =3D '1' and CLK'event ) then --{1
> > > =A0 =A0if (icount <=3D 10 ) then --{2
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0icount :=3D icount +1;
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- do that same something
> > > =A0 =A0 =A0 end if; --2}
>
> > > =A0 =A0end if; --1}
>
> > >end process looper_10_proc;
>
> > As Rick says, good!
> > That is a good example of a pattern to iterate ten times with one
> > "do_something".
>
> > - Brian
>
> My turing machine, language processing, LL(1) grammar, and compiler
> design Professors are turning over in their graves,
> but it seems to be a consensus that this is the way it works.
If what we describe is not what you expected, what hardware *do* you
expect from the above code?
I may have understood what you are confused about some 10 or 15 years
ago. But I have been using this stuff for so long that the ways it
works is second nature to me. Help me understand what you are
confused about.
Rick
Article: 137358Something that surprised me as a beginner is that much HDL compilation is done by template matching, rather than from e.g., denotational semantics. This results in syntactically correct programs which are semantically equivalent with different synthesis behavior. A good reference is IEEE 1076.6, which describes standard templates. Rising-edge clocks, for example, allows a) RISING_EDGE(clk_signal_name) b) clk_signal_name = '1' and clk_signal_name'EVENT c) clk_signal_name'EVENT and clk_signal_name = '1' d) clk_signal_name = '1' and not clk_signal_name'STABLE e) not clk_signal_name'STABLE and clk_signal_name = '1' which can appear in various IF or WAIT templates. Note also that these are intended to be commonly supported templates. Your synthesizer may differ. -- mac the naïfArticle: 137359
Vikram wrote: >>> Do'h! http://www.demandperipherals.com >> So what happened to baseboards 1-3? "4" refers to the number of connectors of course. :) >> For a product like this I would expect to see: >> 1) A large enough photo of the board so that I could read the part numbers. OK. I'll make one of the photos a link that does this. >> 2) Downloadable user manual that explains how I can get a xilinx bit >> file that I generate into your board. This covers software installs and >> a walk thru for a download. A manual is next on our to-do list. Take a look in the downloads section. There is a PDF that explains how to install ISE and use it with Makefiles to download to our board. >> 3) Board schematic. It is in the Downloads section. > You should list your company and product at FPGA Central (http:// > www.fpgacentral.com ). You can add a vendor and then product for FREE. > It is a great place to get some exposure. Visit http://www.fpgacentral.com/add Wow, thanks, Vikam!! Bob SmithArticle: 137360
Hi, I've got some spare Spartan3-200's (XC3S200TQ144) which are left over from a project. I have ~40 non-RoHS compliant parts & 50 that are RoHS compliant. I'll take =A350+postage for the lot! Let me know if you're interested. DaveArticle: 137361
hi all i had designed a module for controlling a steeper motor using vhdl in modelsim where it worked perfectly fine. but while trying to synthesize the same code in ise the following error message was displayed. FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at http://www.xilinx.com/support. can adybody suggest what this problem is actually about and how this can be solved. any suggestions would be highly appreciated. prashant.Article: 137362
prashant.gyawali@gmail.com wrote: > any suggestions would be highly appreciated. Do what the message says, or try it on modelsim. -- Mike TreselerArticle: 137363
uraniumore238@gmail.com wrote: > I bought a spartan 3an board from digilent which comes with a usb > connector. I tried to program the board through the usb connector > using the impact software tool; however, the software tells me that > "usb connection failed". I have also tried programming the board using > the ise software package--still a failure. I have tried re-installing > installing the drivers for the usb cable (downloading the xusbdrivers > and installing them using the command line in windows vista), but > nothing seems to work. Has anyone gone through this issue ... ? The digilent usb is not compatible with xilinx impact. They provide a free software suite that lets you program it from windows via usb. If you have a xilinx programmer then you can make a jtag connection to the digilent board and use impact software. John EatonArticle: 137364
> This application has discovered an exceptional condition from which it > cannot recover. Create a new project with a new directory with File - Project New ... Copy all your VHDL to the new directory with Project - Add Copy of Source ... Change any Properties if your are not using the defaults. See if the problem goes away. If it doesn't you have introduced something in your VHDL that fools the elaboration process which can be narrowed down by copying one VHDL file at a time. Brad Smallridge Ai VisionArticle: 137365
Hi, I am currently using ISE 9.2i Simulator. I have noted that the waveform viewer cannot display the corresponding states of an state machine if you have more than eight states and you are using your own state type definition. Is this problem exist in the later versions? BTW, I am using Lite version of the simulator, maybe the Professional version does not have this limit. Any ideas or experience? Ehsan DSIArticle: 137366
Hi all, I'm trying to use the Area Group Constraint to improve the timing of my design. I defined the constraint using Floorplanner, it says that there are no problems with the constraint ... but during the map process i get a lot of errors like this : ERROR:Place:543 - Due to placement constraint, the followin 1 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. FF user_dsp_inst/ddc_pc_top_inst/ddc_inst/I_da_filter/N2683 (0,0) what I'm doing wrong??Article: 137367
There is also a 3-process approach with separate processes for: i. Selecting the next state (combinatorial) ii. Registering the state variable (clocked) iii. Driving outputs for Moore model (combinatorial) The most important question is - "can this code be maintained?" I have yet to meet anyone who can maintain a 200+ line all-in-one state machine & ancilliary logic single process FSM design, but I have met several people who have tried to. Write it so that your colleagues can understand it. Then you probably will be able to in 6 months!Article: 137368
"RCIngham" <robert.ingham@gmail.com> wrote in message news:Bvadna0XY5DBuPbURVn_vwA@giganews.com... > There is also a 3-process approach with separate processes for: > > i. Selecting the next state (combinatorial) > ii. Registering the state variable (clocked) > iii. Driving outputs for Moore model (combinatorial) > There is even less good to say about the three process approach versus the one process. > Write it so that your colleagues can understand it. Then you probably will > be able to in 6 months! > Having combinatorial processes will not be helping your colleagues understand or support it down the road. Kevin JenningsArticle: 137369
I have done a string of projects for the last decade including literally hundreds of FSMs and only used one process for FSM. It is clean, readable, debuggable, sensible and pleasant. I don't see any reason to go for two. Three is mad. kadhiemArticle: 137370
On Jan 12, 5:02=A0am, Nemesis <gnemesis2...@gmail.com> wrote: > Hi all, > I'm trying to use the Area Group Constraint to improve the timing of > my design. > I defined the constraint using Floorplanner, it says that there are no > problems with the constraint ... but during the map process i get a > lot of errors like this : > > ERROR:Place:543 - Due to placement constraint, the followin 1 > components cannot be placed. The relative offsets of the components > are shown in brackets next to the component names. > =A0 =A0FF user_dsp_inst/ddc_pc_top_inst/ddc_inst/I_da_filter/N2683 (0,0) > > what I'm doing wrong?? I don't know this exact constraint, but are you sure there are enough of whatever type of resources you need (slices, dsp, bram, etc.) in the area group? ChrisArticle: 137371
On Jan 12, 12:56=A0am, Ehsan <ehsan.hosse...@gmail.com> wrote: > Hi, > > I am currently using ISE 9.2i Simulator. I have noted that the > waveform viewer cannot display the corresponding states of an state > machine if you have more than eight states and you are using your own > state type definition. Is this problem exist in the later versions? > BTW, I am using Lite version of the simulator, maybe the Professional > version does not have this limit. Any ideas or experience? > > Ehsan > DSI I had this problem as well. It seems to have been fixed in ISE 10.1 You can also use the free version of Modelsim XE, which I feel is a much better simulator. You can download it from the Xilinx website, and then change your project properties to reflect Modelsim XE as the simulator instead of the ISE simulator. DaveArticle: 137372
On Jan 12, 6:11=A0am, "RCIngham" <robert.ing...@gmail.com> wrote: > There is also a 3-process approach with separate processes for: > > i. Selecting the next state (combinatorial) > ii. Registering the state variable (clocked) > iii. Driving outputs for Moore model (combinatorial) > > The most important question is - "can this code be maintained?" I have ye= t > to meet anyone who can maintain a 200+ line all-in-one state machine & > ancilliary logic single process FSM design, but I have met several people > who have tried to. > > Write it so that your colleagues can understand it. Then you probably wil= l > be able to in 6 months! I feel that the one-process style is more concise, clear, and maintainable. For one, all of the code related to a particular state are in one place, and can usually all fit on the screen at once. Also, I often find that the conditions for making a certain state transition are the same as those for setting an output of the FSM. In the two-process style, this results in redundant code, since the same if-then-else with the same conditions is in both processes. If that condition should need to change during the course of design or debug, I would need to change it in two places, and make sure that both remain in sync. To me, that seems like a bug waiting to happen. DaveArticle: 137373
On 12 Gen, 15:44, Chris Maryan <kmar...@gmail.com> wrote: > On Jan 12, 5:02=A0am, Nemesis <gnemesis2...@gmail.com> wrote: > > > Hi all, > > I'm trying to use the Area Group Constraint to improve the timing of > > my design. > > I defined the constraint using Floorplanner, it says that there are no > > problems with the constraint ... but during the map process i get a > > lot of errors like this : > > > ERROR:Place:543 - Due to placement constraint, the followin 1 > > components cannot be placed. The relative offsets of the components > > are shown in brackets next to the component names. > > =A0 =A0FF user_dsp_inst/ddc_pc_top_inst/ddc_inst/I_da_filter/N2683 (0,0= ) > > > what I'm doing wrong?? > > I don't know this exact constraint, but are you sure there are enough > of whatever type of resources you need (slices, dsp, bram, etc.) in > the area group? I enlarged the area and it seemed to work fine ... but Floorplanner has an option "Check Floorplan" that should test if the constraint you are creating is big enough for the logic you want to place ... and I didn't get any error messages from it.Article: 137374
On Mon, 12 Jan 2009 07:09:09 -0800 (PST), Dave <dhschetz@gmail.com> wrote: >On Jan 12, 12:56 am, Ehsan <ehsan.hosse...@gmail.com> wrote: >> Hi, >> >> I am currently using ISE 9.2i Simulator. I have noted that the >> waveform viewer cannot display the corresponding states of an state >> machine if you have more than eight states and you are using your own >> state type definition. Is this problem exist in the later versions? >> BTW, I am using Lite version of the simulator, maybe the Professional >> version does not have this limit. Any ideas or experience? >> >> Ehsan >> DSI > >I had this problem as well. It seems to have been fixed in ISE 10.1 > >You can also use the free version of Modelsim XE, which I feel is a >much better simulator. You can download it from the Xilinx website, >and then change your project properties to reflect Modelsim XE as the >simulator instead of the ISE simulator. Modelsim is undoubtedly better. But ISIM in 10.3 is getting nearly good enough for serious use, and it already has a few advantages: - it is cross-platform, while Modelsim XE is Windows only (and I don't know about Vista). Modelsim on Linux is either VERY expensive or (deliberately?) crippled to not run VHDL. - it is dual language (which costs extra with Modelsim PE). I haven't tried dual language on XE; I only need it for those pesky memories where the vendors stopped supplying VHDL models - it has the SmartModels built in; these are an extra cost option for PE, and I believe completely unavailable for XE. So far, simulating EDK projects and PCIe on ISIM are unsupported, but the PCIe example simulates just fine. (EDK projects require rework to bypass a major bug in ISE, but can eventually be made to work. This bug is supposed to be fixed in ISE 11; we'll see...) Given another year's improvements in ISIM, I suspect Modelsim will have to start making some changes or lose a lot of market share. - Brian
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