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>PLLs/DCMs/DLLs (or whatever your favourite FPGA >happens to offer) provide a wonderful way to create >multiplied-up clocks within the device. What's more, >you can line up the active clock edges so closely >that you can treat the x1 and xN clock domains as >if they were one single clock domain; hold times >can be avoided when crossing the boundary in either >direction. Do the vendors actually support that mode? It seems reasonable, but I remember some discussion from a year or three ago where somebody eventually tracked a bug down to it not quite working. Newer silicon might take that into account.. The basic idea is that the Xilinx tools don't bother checking hold times. All their FFs have "0 hold time". What that really means is that the min clock-to-out time plus min prop delays are enough to cover the hold time and the clock skew. The catch is that you can get additional skew if you are using two clocks even though they should be aligned. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136476
jleslie48 wrote: (snip) > Ok, I've reviewed the two links. They do a nice job of explaining the > theory, and even give some nice snippets of code; I'm really looking > for a from start to finish example of an fpga program that can be > loaded and run. It is better not to think of working with FPGA's as "loading and running a program" but as digital logic design. You should have some idea how to wire up gates and flip-flops to build working devices. > the fpga4fun.com rs232 page had a zip file with two .v files and a .c > program. I assume I'm supposed to unpack those 3 files, and then use > them somehow... Most likely they have comments, but maybe that isn't enough. > A good "hello world" programming example, starts with unpacking the > zip file, and then step by step opens the building programs, shows you > the buttons/switches to call, shows you what files are generated, > walks you through powering up, downloading the exe image, and then > running the program and verifying that it is functioning correctly. One of the favorite projects from some years ago was a digital clock. (Before you could buy one for a few dollars made in China. The LED displays cost a few dollars each.) > Are there any "soup to nuts" test programs for the xilinx evaluation > kit out there??? If your board has a seven-segment LED display, design and load a digital clock. -- glenArticle: 136477
Alessandro wrote: > deep wrote: >>board.i am trying to interface the vga port for displaying image >>stored in the memory(may be BRAM or distributed).in the vga port there >>are 2 timing signals vsync and hsync and 3 color signals for RGB.i can >>display 8 colors from the 3 bit combinations RGB (snip) > You will need a soldering iron to solve this issue: your only option is > adding more bits to each color, through proper resistors, until you get the > desired color depth. Not the only option, but it is the best one. It could also be time multiplexed, maybe on alternate frames. (If you have a longer than two frame cycle it will likely have a lot of flicker.) Change the logic to supply six bits of color information, and select which three are sent out such that they alternate by frames. You will then have three levels for each color for 27 different colors. Another choice is to dither. Increase the dot clock and combine neighboring dots to generate intermediate colors. You might be above the frequency response of the monitor, in which case it will most likely average them for you. -- glenArticle: 136478
does anybody have a clear opinion about code generators ( c-> vhdl , matlab-> vhdl, etc..) that are around? Are they really irreplaceable in complex applications (i.e DSP) as the vendors say?Article: 136479
abe wrote: > does anybody have a clear opinion about code generators ( c-> vhdl , > matlab-> vhdl, etc..) that are around? Are they really irreplaceable > in complex applications (i.e DSP) as the vendors say? Having written some complex algorithms in verilog that (in the form of systolic arrays), I am not convinced at all that such generators are the way to go. I am willing to be convinced, but at least for the problems I have worked on the algorithm looked so different that there is no way a program could figure it out. -- glenArticle: 136480
Jonathan > Every cloud has a silver lining, but it seems > every rose has its thorns too. > > PLLs/DCMs/DLLs . . . > > We've easily enough got around this for the present > design, but I'd love to know what all you seasoned > PLL/DCM users out there do about it. Do you > introduce small non-zero time delays in all the > signals crossing the clock domains, so that it all > works in simulation? Do you treat the various > clock domains as if they were asynchronous, thereby > losing one of the nicest benefits of the PLLs? Or > do you simply accept that it's necessary to do timing > simulation in order to see what will really happen? Haven't had to do this, so I will introduce a fourth question, if all clocks are truely aligned have you tried removing delta cycle differences via adding a small non-zero time delay (less than tperiod_Clk/2) to the clock outputs? Clk_X1_DS <= Clk_X1 after 1 ns ; Clk_X2_DS <= Clk_X2 after 1 ns ; Clk_X4_DS <= Clk_X4 after 1 ns ; Since synthesis tools ignore after (or at least are supposed to), this should be ok to add to the RTL code. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis SynthWorks VHDL Training http://www.synthworks.com A bird in the hand may be worth two in the bush, but it sure makes it hard to type.Article: 136481
Glen Herrmannsfeldt wrote: > Not the only option, but it is the best one. I've also heard of using PWM output on the RGB lines to produce more colours... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136482
Symon wrote : > > It also seems that if the design only uses the outputs from the DCM only, > i.e. CLK0, CLKDV, CLK2X, which is the way they are 'meant' to be used, then > they are already aligned. > That's how the DCM model is _supposed_ to work, but I've encountered problems with delta delay offsets in the Xilinx DCM models in years past: http://groups.google.com/group/comp.arch.fpga/msg/6e5b0b6da92b4ad1 Other thoughts: As suggested elsewhere on the thread, I usually attempt to bundle all the DCM's into a clock module that can be replaced by a simpler model for functional sims. This module also gives a handy spot to take care of any DCM reset sequencing, unlock logic, and the startup enables needed to avoid the insidious initialized BRAM corruption feature. ( IIRC, xapp873.zip has an example of this sort of thing ) One additional suggestion: even if one replaces the DCM module for functional sims, it is very helpful to thoroughly beat up the actual DCM module in it's own simulation testbench to make sure all of the required startup and unlock recovery sequencing is done properly without the simulation model throwing any errors. BrianArticle: 136483
Hi everyone. For shortage of memory in FPGA, I need an exteranl memory. In this case, is it possible to implement my application in ISE? I means how to initiate the external memory in ISE tool. If possible, I want to do simulation in PC without configuring it to real board.Article: 136484
On Nov 18, 5:15=A0pm, abe <a.bergn...@gmail.com> wrote: > does anybody have a clear opinion about code generators ( c-> vhdl , > matlab-> vhdl, etc..) that are around? Are they really irreplaceable > in complex applications (i.e DSP) as the vendors say? Maybe they work great, maybe not. I think that it is safe to say, however, that the statement that they are irreplaceable for complex applications is ridiculous, pure marketing with no technical basis. DaveArticle: 136485
Jonathan Bromley wrote: > We've easily enough got around this for the present > design, but I'd love to know what all you seasoned > PLL/DCM users out there do about it. Do you > introduce small non-zero time delays in all the > signals crossing the clock domains, so that it all > works in simulation? Do you treat the various At least one trick I use with modelsim is to force clock signal to the DCM outputs from the simulator. When forced signals are created they work on the same delta cycle. The same trick can be used also with asics that contain clock buffers for clock tree roots etc. --KimArticle: 136486
Hello, On 18 Nov., 23:15, abe <a.bergn...@gmail.com> wrote: > does anybody have a clear opinion about code generators ( c-> vhdl , > matlab-> vhdl, etc..) that are around? Are they really irreplaceable > in complex applications (i.e DSP) as the vendors say? You could typically abstract on a higher level when using matlab or reuse existing c code when using c. This is really a benefit, when it comes to complex systems. But you also loose in abstraction. It is usually not possible to model more than clocked events on description as well as during simulation. This speeds up your simulation drastically on cost of the benefits of timing aware simulation. The tools I inspected are not able to handle even two independend clock domains properly. If your design is not timing critical nor area critical, has only one clock domain and needs no special cells, than you should be the perfect customer for tools like CatapultC or mathlab synthesis. DSP may be a good field for such designs. But I doubt at the moment that such a customer has the need to spend lot of money to design in an other language. bye ThomasArticle: 136487
KJ wrote: > Hi everyone. > > For shortage of memory in FPGA, I need an exteranl memory. > In this case, is it possible to implement my application in ISE? > > I means how to initiate the external memory in ISE tool. > If possible, I want to do simulation in PC without configuring it to > real board. Could You please be a bit more precise on what You'd like to do? Yes it is possible to add the controller for external memory to Your design. Though You seriously should think about Your problem. After You know Your problem look for the right tool that solves Your problem. I am quite sure You do not want to use ISE as Your solution. I strongly believe You want to use EDK/XPS as Your solution, but that's just some guess from what I think Your problem might be. Regards, LorenzArticle: 136488
Hello, does somebody have Quatech SPPXP-100 Express card to parallel port (lpt) adapter? I need to know if it is working with: 1) Quartus II and Byteblaster II 2) Code Composer Studio 3.3 and XDS510PP+ -- PawelArticle: 136489
weg22@drexel.edu wrote: > Hi all, > > I'm developing a video processing application using a digitial video > camera and a FPGA. In an ideal world, I would interface the camera > directly to the FPGA via an IEEE 1394 interface. I'd still like to > extract the video from the camera using 1394 but I'm trying to avoid > spending the time to develop the IEEE 1394 software interface for the > FPGA. > > I know TI makes a chipset that converts 1394 to PCI-Express, but I > don't think that will work for an embedded system. I was wondering if > there was some IC out there that converted the IEEE 1394 protocol into > something I already have software for (e.g. USB, EIA 485, etc.)? I > know I'm losing speed, but I can live with that. > > Thanks in advance, > weg22 Hi I've been involved in a design, using a TI 1394B phy+LLC chip which bridges to a PCI bus. The PCI bus was bridged to the OPB/PLB buses of a PowerPC system in a Virtex-4 FPGA. Standard OHCI linux drivers were used for the interface. You may be able to do the same using a smaller (=cheaper) FPGA and microblaze if cost is an issue. Regards, FinnArticle: 136490
Hello All, Does anyone know if there is a cheaper alternative to the Xilinx USB JTAG programmer. ? The price of $300 from avnet is rather expensive in my opinion (and for my budget..). I've been using xilinx cable IV, but it's not really working as reliable or fast as one could wish for. Another problem is that my laptop doesn't have a parallel port which is very annoying. Thanks, JohnArticle: 136491
Hallo.
When using a Spartan3 SliceM in 2x SRL16-Mode,
the Slice-FlipFlops and the SRLs must share the same clock
(and from the FPGA-Editor, it looks like if that clock's
polarity must be the same for both, SRLs and FFs).
Now, if I want to use the FFs (I don't think they can be
used for anything else then buffering the SRL's Output),
I'm not fully sure the FF clk will be early enough
to not sample the SRL during undefined output.
I think it's very likely that the FF clk is early enough,
but I don't see a way to ask the xilinx tools about that
(apart from the module attached compiles without errors
in ISE10.1 web).
Has anyone tried a simulation about this?
Gruss
Jan Bruns
module shiftreg16F(di,o,clk,cke,cke2,a);
input di;
output o;
input clk;
input cke;
input cke2;
input [3:0] a;
reg [15:0] shiftdata;
reg tmp;
always @(posedge clk)
begin
if (cke) begin
shiftdata[15:1] <= shiftdata[14:0];
shiftdata[0] <= di;
end
if (cke2) begin
tmp <= shiftdata[a];
end
end
assign o = tmp;
// synthesis attribute RLOC of shiftdata[15:0] is "X0Y0"
// synthesis attribute RLOC of tmp is "X0Y0"
// synthesis attribute BEL of shiftdata[15:0] is "F"
// synthesis attribute BEL of tmp is "FFX"
endmodule
Article: 136492"Eric Smith": > "guestuser1" <guestuser1@nowhere.net> writes: >> *ANY* softcore FPGA embedded CPU (Microblaze, Nios-II) is so slow, >> why would you even try to run a full Linux (MMU) kernel on it? > > Sometimes you need the MMU more than you need the performance. Otherwise > we'd all be running uCLinux on our x86 boxes. What's the difference between uClinux and win32? Gruss Jan BrunsArticle: 136493
Jan Bruns wrote: > "Eric Smith": >> "guestuser1" <guestuser1@nowhere.net> writes: >>> *ANY* softcore FPGA embedded CPU (Microblaze, Nios-II) is so slow, >>> why would you even try to run a full Linux (MMU) kernel on it? >> Sometimes you need the MMU more than you need the performance. Otherwise >> we'd all be running uCLinux on our x86 boxes. > > What's the difference between uClinux and win32? > The main differences between uCLinux and full Linux are that full Linux implements fork (uCLinux has just vfork, or fork+exec), it properly separates the memory space and resources of the kernel and each user process from each other, it supports virtual memory, and it has much more flexible and efficient dynamic memory allocation. Mind you, when you look at Win32 (especially earlier versions, but still relevant for later windows versions), you don't have a proper fork, user processes and the kernel are not properly separated from each other, and the virtual memory handling is terrible. So I see your point - there is not much difference between uCLinux and Win32....Article: 136494
On Wed, 19 Nov 2008 11:50:57 +0100, John Evans <nospam_john_evans@gmail.com> wrote: >Hello All, > >Does anyone know if there is a cheaper alternative to the Xilinx USB >JTAG programmer. ? The price of $300 from avnet is rather expensive in >my opinion (and for my budget..). > >I've been using xilinx cable IV, but it's not really working as reliable >or fast as one could wish for. > >Another problem is that my laptop doesn't have a parallel port which is >very annoying. Digilent has one but it's not a direct substitute for the Xilinx model so Xilinx's Impact tool doesn't operate with it. Digilent supplies their JTAG toolset, the Adept suite, which works with both the Xilinx (and Digilent) parallel cables and with Digilent's USB-JTAG cable. For less than US$40, it's a minor inconvenience. http://digilentinc.com/Products/Detail.cfm?Prod=JTAG-USB&Nav1=Products&Nav2=Cables HOWEVER, you will need to make one small configuration change in the development setup to use the JTAG port as the startup clock. >From their FAQ: "The configuration state machine inside the FPGA needs a "startup clock" to clock the final startup sequence after configuration. This clock source is controlled by a bit in the binary configuration file (.bit file). The startup clock source is controlled by an option setting in the "Generate Program File" process in the Xilinx ISE Foundation or Xilinx ISE WebPACK Project Navigator tool. The clock source should be set to JTAG to create a .bit file to be used for configuring the FPGA using a JTAG interface. The clock source should be set to CCLK for .bit files that are intended to be programmed into a Platform Flash ROM." The complete FAQ is at http://digilentinc.com/Support/FAQs.cfm?Nav1=Support&Nav2=FAQ -- Rich Webb Norfolk, VAArticle: 136495
On 19 Nov, 11:50, John Evans <nospam_john_ev...@gmail.com> wrote: > Hello All, > > Does anyone know if there is a cheaper alternative to the Xilinx USB > JTAG programmer. ? The price of $300 from avnet is rather expensive in > my opinion (and for my budget..). > > I've been using xilinx cable IV, but it's not really working as reliable > or fast as one could wish for. > > Another problem is that my laptop doesn't have a parallel port which is > very annoying. > > Thanks, > > John I use an amontec jtag key tiny driven with a svf player. the svf file is produced by Impact.Article: 136496
On 18 Kas=FDm, 18:37, KJ <lkj...@gmail.com> wrote: > Hi everyone. > > For shortage of memory in FPGA, I need an exteranl memory. > In this case, is it possible to implement my application in ISE? > > I means how to initiate the external memory in ISE tool. > If possible, I want to do simulation in PC without configuring it to > real board. You can download simulation models for the ram that you will use. Afterwards you should write a controller for it and you can use the model in your testbench.Article: 136497
"Jan Bruns":
> I think it's very likely that the FF clk is early enough,
> but I don't see a way to ask the xilinx tools about that
> (apart from the module attached compiles without errors
> in ISE10.1 web).
> always @(posedge clk)
> begin
> if (cke) begin
> shiftdata[15:1] <= shiftdata[14:0];
> shiftdata[0] <= di;
> end
> if (cke2) begin
> tmp <= shiftdata[a];
> end
> end
The following also compiles without error:
always @(posedge clk)
begin
if (cke2) begin
tmp = shiftdata[a];
end
if (cke) begin
shiftdata[15:1] = shiftdata[14:0];
shiftdata[0] = di;
end
end
but the opposite blocking behaviour compiles, but infers flipflops
instead of srl16:
always @(posedge clk)
begin
if (cke2) begin
tmp = shiftdata[a];
end
if (cke) begin
shiftdata[15:1] = shiftdata[14:0];
shiftdata[0] = di;
end
end
I didn't notice that xst now has better blocking assignment support
(or maybe I got a false impression about older xst versions when
learning verilog).
Gruss
Jan Bruns
Article: 136498It's been a month now and Xilinx is just now getting all the accounts to work. So I have been pounding out Webcases now for about a week. When they moved away from the DVDs, forced us to purchase from Avnet and dropped phone support, we were screwed. Avnet was zero help. Xilinx would not talk to us on the phone. As Xilinx worked to get the licenses sorted out I actually got a letter from them that I was shocked when I read but I thought it really summed up the new Xilinx. It's a new company for sure. I can't explain it but after running the built-in web updater, ISIM has gotton much more stable. I went ahead and installed 10.1.03 onto my normal PC which runs XP 64. ISIM seems to run fine on this PC as well, while in 32-bit mode. In the past two days I have had only one crash where I had to flush the entire design to get it working again. This was the only crash. Before I was seeing 6 - 10 crashes per day. More strange also is that my evalution is now much more complex. There was nothing in the release notes that talked about improving ISIMs stability so the two may have nothing to do with one another. I am finding some missing features that I would really like to have, like the analog display. The graphing is some of the worst code I have seen wrote. Zoom out for example and you may not see all the state changes. Zoom and pan, don't even get me started.. I think this part was given to the intern. I have been told that the graphing in 11.1 is much better and I am trying to see what it takes to get a beta copy. There was another post where a person had asked about using ModelSim rather than ISIM. Just to be clear, we have been using Aldec but they really started to fall behind (that lawsuit IMO was like the dog that bit the hand that fed him) . Now that they are partners with Xilinx, I am hoping that they get their act together. I am using ISIM just for evaluation.Article: 136499
Hi, One of Altera application note uses Atlantic Interface. On the new SOPC, I cannot find Atlantic Interface component. I wonder whether it is replaced by Avalon Streaming interface?
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z