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Hi, On 25 Okt., 12:18, "500milesaway" <500milesa...@gmail.com> wrote: > I just want to know the steps to > download the program to FPGA. You need to build a programming File using the xilinx software, than use the manual of your development board to learn how to download the bit stream to your board > I have few questions as well: > > 1. How will I assign me signals (clk, a, b, y) to the ports/pins of FPGA? Using the .ucf-File you can assign the names to actual pins. > 2. How should I give the inputs (clk, a, b)? Can I do this using switches > of the FPGA board? How to connect the FPGA ports to the switches? Don't use a switch for clock, as it is very likely to bounce and you have no way of debounce your master clock. Most boards have an onboard clock source. Else you need to connect an external clock source. Your inputs will very likely bounce as well if you use an switch, you need to select the clock in a way, that your rising edge of clock is in a timeframe where the inputs A and B are stable. > 3. How should I take output (y)? Should I use the LED of the board? How to > connect output port of FPGA with the LED? You need to select the pin that drives the led for output y. Else it is always possible to solder a wire from pin to led..... > 4. Do I have to code any .ucf file manually? How to code .ucf for this > simple program? http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/entry8.html#1017947 bye ThomasArticle: 136001
Hi Michael, "Michael Brown" <see@signature.below> wrote in message news:48fc54df$0$18427$afc38c87@news.optusnet.com.au... > At the start of the year, there were suggestions that WebPack 10.1 would > support Windows x64, but this has turned out not to be the case. Is there > any newer news on when an x64-supporting WebPack will come out? I don't > care about WebPack being a 32-bit application or 64-bit; the 32-bit > version of WebPack works fine (if as slow as molassas) on XP x64 (and > Vista x64) except for iMPACT. Has Xilinx intentionally prevented the > 32-bit iMPACT from using the 64-bit USB drivers (which install fine), or > is it simply a case of poor software engineering tying the USB driver > bitness to the application layer bitness? > > Currently, I'm using a spare machine that does nothing except run 32-bit > XP solely for ISE to upload designs to the board, but with summer coming > here in Australia, I'd like to get rid of the extra heat source. I use 10.1 on a WinXP32 VMware setup here. Host machine is quad-core VistaX64. iMPACT has no trouble talking through the VMWare virtual USB device to my USB platform cable, with ML403 and S3A1800 target boards. Did try tinkering with the 10.1 setup to see if it would play on VistaX64, but with only minor success. The 10.1.2 update screwed it up completely, so I gave up! Where in Oz are you? Cheers, RedArticle: 136002
"laserbeak43" <laserbeak43@gmail.com> wrote in message news:fca56164-4132-4596-80e3-835f2370f0e4@x41g2000hsb.googlegroups.com... > Hi, > I'm trying to write a driver for my LCD, the Sitronix ST7066U on > my Spartan 3E starter kit and i'm having a bit of trouble > understanding something. The user guide tells you > that there is 4-bit data bus and the lower 4-bits are unused. But a > page or 2 down the user guide it tells you that you need to use these > lower 4-bits to access characters. That's very confusing. > Check out Roni's page at: http://ronivon.costa.googlepages.com/z80computer Has a Z80 project which drives the LCD on the S3E starter kit. RedArticle: 136003
hi, if you have one of the new (red) DLC9-cables, the driver from http://www.rmdir.de/~michael/xilinx/ will not work (LED stays off). it works fine with the old (black) cables and the LED should turn orange or green if you connect it. i took a short try to get the red cables to run and succeeded temporarily with the windrv6 module under ubuntu64. i think i accidently took a evaluation version of the driver because it worked only for some hours: http://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK_10.1_wUSB_cable_on_ArchLinux-2.6.24 please report if you have more luck or if you find another solution! regards, heiko thecreator schrieb: > Hi! > > I'm trying to connect my virtex-4 ML403 board with the DLC9 cable > (USB) under Linux (Fedora). > Installed the linux usb-driver from http://www.rmdir.de/~michael/xilinx/ > and preloaded it (LD_PRELOAD). Also put the .hex files and the .rules > files to the correct dir. > > I 've chosen output->cable setup -> usb cable. > The output of impact is this: > > INFO:iMPACT:501 - '1': Added Device xc4vfx12 successfully. > .... > Connecting to cable (Usb Port - USB22). > Checking cable driver. > File version of /vlsi_soft/xilinx_ise9.1i/bin/lin/xusbdfwu.hex = > 1025(dec), 0x0401. > File version of /usr/share/xusbdfwu.hex = 1025(dec), 0x0401. > libusb-driver.so version: 2007-10-16 14:54:24. > Cable connection failed. > > The LED on the USB cable box is still OFF. > lsusb shows the follwing: > Bus 004 Device 003: ID 03fd:0007 Xilinx, Inc. > > Do I have to install any other drivers or software additionally to > this usb-driver wrappers? > > Thanks for hints! > regards, RalphArticle: 136004
http://vmagic.sf.net/ The vMAGIC library provides functionality for reading, manipulating and writing VHDL code, enabling users to create their own code- generators, code-analyzers and more. Apart from a VHDL'93 compliant parser and writer, a high level programming model is provided: This model gives easy access to both high-level (registers, muxes,...) and low-level VHDL objects (declarations, assignments, assertions), resulting in a toolset for reliable and fast VHDL code generation. Currently the project is in alpha phase, though it is rather stable. Please report any problems or errors that you find to the project forums. More complex examples will be available soon.Article: 136005
On Oct 25, 11:18=A0am, "500milesaway" <500milesa...@gmail.com> wrote: > Hello, > > I want to download a simple VHDL program to FPGA Xilinx Virtex-4. I am > using ISE 10.1 and iMPACT 10.1. the code is very simple. it is an AND gat= e > that works at clock high > ------------------------------ > process(clk) > begin =A0 =A0 =A0 =A0 =A0 =A0 > =A0 =A0 =A0 =A0 if (clk'event and clk =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 y <=3D a and b; > =A0 =A0 =A0 =A0 end if; > end process; > ------------------------------ > I am very new in FPGA programing. the behavioral,post-translate,post-map > and post-route simulation works fine. I just want to know the steps to > download the program to FPGA. > > I have few questions as well: > > 1. How will I assign me signals (clk, a, b, y) to the ports/pins of FPGA? > 2. How should I give the inputs (clk, a, b)? Can I do this using switches > of the FPGA board? How to connect the FPGA ports to the switches? > 3. How should I take output (y)? Should I use the LED of the board? How t= o > connect output port of FPGA with the LED? > 4. Do I have to code any .ucf file manually? How to code .ucf for this > simple program? > > Someone may think these questions very childinsh. But as I am very new in > this field and getting no advisor/instructor to help me, these are very > crucial to me. Hope to get help from you soon. > > Best regards, > > Pantho Probably the best easiest way to program your FPGA will be to use the JTAG port. You will need a download cable (such as Platform USB cable), and the downloading can be performed with the iMPACT software. It's all pretty straight forward, you'll know if everything is connected up correctly and powered correctly if you do a scan on the JTAG chain: your Virtex-4 device should be found. > 1. How will I assign me signals (clk, a, b, y) to the ports/pins of FPGA? Put a line in the UCF for eaach pin assignment i.e. NET "a" LOC =3D P1; #assuming you are assigning "a" to location pin 1 For UCF editing you can either just edit the text file manually, or use the ISE constraints editor. I personally prefer manual editing. > 2. How should I give the inputs (clk, a, b)? Can I do this using switches Switches will work fine, provided they are hooked up correctly. You need to make sure that when the switch is on it is driving the correct voltage into the IO pin of the FPGA and when it is off, it is either connecting the pin to ground, or there is a pull-down resistor to give 0Volts. You might want to specify the IO voltage for each signal in the UCF i.e. NET "a" IOSTANDARD =3D LVCMOS33; #assuming 3.3V CMOS > 3. How should I take output (y)? Should I use the LED of the board? How t= o > connect output port of FPGA with the LED? Again, an LED will work fine, provided it is connected up correctly. I think the default current output of the V5 IOs is 12mA. If you want more, you can use the constraint DRIVE i.e. NET "y" DRIVE =3D 24; Have a look at the contraints guide in the software manuals here: http://toolbox.xilinx.com/docsan/xilinx10/books/manuals.pdf Good luck! RobArticle: 136006
eubanksster@gmail.com wrote: > I am fairly new to CPL development, and I need to create an emulation > of a number of old bipolar Proms (256x4) being used in a very old > system by using a CPLD and WInCUPL. What are the PROMS doing ? > My approach was to use the example "Lookup.pld" as a basis for my LUT, > with the exception that I am trying to use 8 bits of address to > produce a 4 bit output for each of the possible 256 inputs. > > Using an AT22V10, I am able to (sometimes) create a table of 256 > elements in length. -which I have verified to function in a circuit > BTW- However, I have noticed that there are certain sequences of > values (most, in fact) that will give me errors: "too many Product > terms" for each bit of the 4 bit output. So my approach is apparently > not the "general solution" that I need. (I have the data for the parts > that I need to emulate, and they appear to be "random" values) There > does not appear to be any optimization selection that helps either. <snip> If you consider no logic optimisation, you will need 256 Product terms. The good news is, CUPL will optimise (and has -M2/M3/M4 switches to do so, and it CAN reduce the PTs needed - but (more bad news:) only so far. You CAN pack a 7 segment decoder, to around 20 charatcers into 8 PT, or a Decimal-7 segment into 2-3-4 product terms, so a typical 'packing ratio' of up to 3:1 is indicated. That drops your 256 to the region of 80! So any solution is VERY prom content dependant. You have to hope those proms, are 'coarse' in what they do, if they are granular, and more random, you are sweet out of luck. What does CUPL actually report as the PT usage, with highest optimise setting, for each BIT of your PROMS ? That should be in the report files. Knowing what the proms are actually DOING, would help here. It is unlikely they are _really_ random You CAN trade off some outputs as INTERMEDIATE product terms, and so cascade PTs, but a 22V10 must average under ~34.5PT/4 bits, to fit (working from memory). Doing that cascade is not something the tools automate, but CUPL WILL swallow intermediate terms not PIN defined, so you can code the PROM into blocks, and see how the block compress. <paste> > Is there by chance a vendor that that you know of that currently > provides CPLDs that would meet my capacity requirements but packaged > as a small SOIC or similar? (IOW, something that could easily fit > within the size of a 16 pin DIP) I have looked around, but most go > down to 44pin QFP which would still be too large. PLCC32 is not far off ? - that would allow a 27E512, which is a curent device and will exactly emulate your PROM. (unless the last ns matters) -jgArticle: 136007
Hi John, Yes, I was looking at enterpoint products as well, but currently couldn't find the one that would satisfy my requirements. Perhaps, Darnaw1 looks good, but will involve designing the communication interface. Alex Darnaw1 > It's possible that a development board we have scheduled for release > later in this quarter will meet your requirements. It's not the one I > will probably announce next week, or even the release after that, so > don't think they are the ones to look at. > > We also do have the possiblity of doing a small solution based on our > Drigmorn1 board, > http://www.enterpoint.co.uk/component_replacements/drigmorn1.html, > and an add-on module. For add-on modules we have an ethernet phy > module and also a usb2 module based on CY7C68014. The later isn't as > fast as it could be but I hope we will improve that shorly. > > John Adair > Enterpoint Ltd. - Making FPGA Technology Work. > > On 24 Oct, 17:31, Alex <al.lop...@gmail.com> wrote: >> Hi Guys, >> >> I am currently looking for a small board with FPGA and USB/Ethernet >> module on it. Some time ago we used to use OpalKelly 3010 boards, and >> they were just fine, and now they are on of the main candidates. But >> since some time has passed, I thought maybe there are some others >> interesting products that would satisfy my basic requirements: >> 1. Plenty of free user I/Os. >> 2. Fast communication interface (USB1 wouldn't do) >> 3. Relatively small form factor >> 4. Developed firmware, so that not much hacking would need to be >> involved. >> >> I would be very grateful if somebody could share his experience (known >> bugs, etc) with >> š the following boards (or if you used different ones and can >> compare - even better!!) >> 1. OpalKelly >> 2. TQM HS3/HV5 šfrom tq-components >> šhttp://tq-components.de/produktdatenbank+M5d637b1e38d.html >> š š interesting boards, but haven't heard anything from people using >> š š them >> 3. TE0300 modules from šTrenz-electronic š >> šhttp://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/... >> š š same story as in 2. >> 4. SUZAKU series fromwww.atmark-techno.com/ >> >> There are some others such as Easyfpga and FTDI Fpga boards, but they >> offer slow data-rate and very limited in terms of user I/O pins. >> >> Although all listed here products are based on XIlinx chips, this >> certainly doesn't have to be case. >> >> Alex > -- AlexArticle: 136008
Starting with the PCI104 connector and if my count is right 65 are available here. On the PC104 90 are available. The PS2 connector (12x1 sil) can also be reused as 8 general I/O and has pullups to 5V if you need to make CMOS levels. The VGA connector can be used as 5 more with some restrictions. There is also a ZIF for a further 3 inputs and 1 output. One of the nice things is that if the PC/PCI104 connectors are not being used for those standard connections they are totally reuseable and are 5V tolerant by virtue of the in-line bus switches. We should be doing some application notes on other uses such as point to point LVDS connections and even hybrid signalling structures. These application notes will appear as the companion boards we have planned for this are designed and made so probably 2-3 months before they start appearing. Another thing worth mentioning is that the PC104 and PCI104 connectors include the entire set of bus grants etc allowing the board to be a master handling arbitration or a slave on either interface or even both. This will also allow the board to operate as a bridge which may be useful in extending the life of legacy cards and motherboards. John Adair Enterpoint Ltd. On 24 Oct, 23:35, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > Finally photos of new baby PC104/PC104+ board Hollybush2 are now > > Nice. > > How many IO pins are available on the connectors? > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel.=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A006151=A0162516=A0= =A0=A0=A0=A0=A0=A0-------- Fax. 06151 164321 ----------Article: 136009
>> >Check out Roni's page at: >http://ronivon.costa.googlepages.com/z80computer > >Has a Z80 project which drives the LCD on the S3E starter kit. > >Red > > Oh saaaweet!! thanks!Article: 136010
Hi Symon, everyone, Symon wrote: > ----- Original Message ----- > From: "Paul Boven" <p.boven@xs4all.nl> >> I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock. This >> clock goes out of a pad towards the sampler, and the bits come back from >> the sampler. But, depending on rather unrelated changes in my VHDL, >> sometimes I get perfect samples showing the sine output from my signal >> generator, and sometimes there are all kinds of 'jaggies' indicating that >> I'm catching some bits either too late or too early. > OK, I guess your 62.5M clock is coming from a bufg, right? Make the clock > that goes to your ADC by using the output IOB's DDR registers with the clock > connected to the DDR's clock, D1 <= '1' and D2 <= '0'. Also, make sure that > the data from the ADC is clocked into your design using the FFs in the IOBs > where the data comes in. This way your clock out and clock in are quite > tightly constrained and the P&R variability should disappear. > There are also delay elements in the input IOBs that are there to provide > the 'zero hold time' feature. You may or may not want to adjust whether > these are used after thinking about your timing. The 62.5MHz is generated in the FPGA, first by a DCM and now simply by a clocked FF, and then goes into a BUFG that I had to instantiate. Adding the BUFG made the thing a whole lot more stable already, and took care of the original 'jaggies' problem I mentioned. The trick to clock a DDR output register to replicate the clock on an output pad is very neat, and should prevent the whole 'could not be routed by a clock template' problem. I'm not sure yet whether the input IOBs are clocking in the data directly, I will try and find out through the FPGA editor. If not, I'll add an extra level of registers, I guess. It also seems that I have quite a bit of jitter [1] on my sampling clock, which makes it unsuitable for undersampling the input signal (at around 120MHz) as I originally planned. I'll try and have a look at it with a faster oscilloscope to see whether the FPGA is causing this jitter. An external clock oscillator might have been a better idea. [1] http://www.xs4all.nl/~epboven/S3ADC-jitter.png Regards, Paul Boven.Article: 136011
Also, see www.fpgaz.com/usbp. Basic FPGA board with same cypress USB chip. Can be purchased from http://www.dehalastech.com/fpgaboard.html.Article: 136012
On Oct 21, 9:52=A0am, "lecroy7...@chek.com" <lecroy7...@chek.com> wrote: > I have setup the latest ISE with latest updates. =A0I can't seem to find > the ISIM tool. =A0 We normally run Aldec, but they have gotten a little > behind and just became partners with Xilinx. =A0I wanted to see if ISIM > could be used. > > Looking on the Xilinx site, it seems like the full blown copy of ISE > should have at least the lite version of ISIM and Planahead. =A0 I > loaded ISE from the DVD but we don't buy the version with the > simulator. =A0 I can't seem to find a seperate download for ISIM. > > Do I need to download the web version to evaluate ISIM? > > I tried to call Xilinx support and was told I can't talk to anyone in > tech support and have to use the webcase. =A0We currently have 5 seats > so I guess we are no longer considered a big enough customer. =A0 I tied > to use the webcase but need to open a new account which takes some 30 > minutes to setup. =A0 So, if you can halp me figure out how to get ISIM > running it would be great. It's probably easiest to use from the command line (like a DOS shell). Look for the executables vhpcomp.exe, vlogcomp.exe, and fuse.exe. The waveform viewer can be run standalone as isimwave.exe. -KevinArticle: 136013
On Oct 26, 5:38=A0am, thecreator <gruber.ra...@gmail.com> wrote:
> Hi!
>
> I'm trying to connect my virtex-4 ML403 board with the DLC9 cable
> (USB) under Linux (Fedora).
> Installed the linux usb-driver fromhttp://www.rmdir.de/~michael/xilinx/
> and preloaded it (LD_PRELOAD). Also put the .hex files and the .rules
> files to the correct dir.
>
> I 've chosen output->cable setup -> usb cable.
> The output of impact is this:
>
> INFO:iMPACT:501 - '1': Added Device xc4vfx12 successfully.
> ...
> Connecting to cable (Usb Port - USB22).
> Checking cable driver.
> File version of /vlsi_soft/xilinx_ise9.1i/bin/lin/xusbdfwu.hex =3D
> 1025(dec), 0x0401.
> File version of /usr/share/xusbdfwu.hex =3D 1025(dec), 0x0401.
> =A0libusb-driver.so version: 2007-10-16 14:54:24.
> Cable connection failed.
>
> The LED on the USB cable box is still OFF.
> lsusb shows the follwing:
> =A0 =A0 Bus 004 Device 003: ID 03fd:0007 Xilinx, Inc.
>
> Do I have to install any other drivers or software additionally to
> this usb-driver wrappers?
>
> Thanks for hints!
> regards, Ralph
Hi Ralph,
I believe you need to update the firmware for your cable - see the
instructions below (from the usb-driver readme file):
Notes for the USB cable
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
To use the device as an ordinary user, put the following line in a new
file "libusb-driver.rules" in /etc/udev/rules.d/ and restart udev:
ACTION=3D=3D"add", BUS=3D=3D"usb", SYSFS{idVendor}=3D=3D"03fd", MODE=3D"666=
"
If your cable does not have the ID 03fd:0008 in the output of lsusb,
the initial firmware has not been loaded (loading it changes the
product-ID from another value to 8). To load the firmware follow
these steps:
1. If you have no /etc/udev/rules.d/xusbdfwu.rules file, copy it from
/path/to/ISE/bin/lin/xusbdfwu.rules to /etc/udev/rules.d/
xusbdfwu.rules
2. Install the package containing /sbin/fxload from your linux
distribution.
It is usually called "fxload"
3. copy the files /path/to/ISE/bin/lin/xusb*.hex to /usr/share/
4. restart udev and re-plug the cable
Cheers,
David
Article: 136014Hi, I would like to model the Virtex-II Pro FPGA using PSpice, and run some simulations on this model. Right now I have everything set up, but I am using two models that are not representative of the specific FPGA I am using (I included the models at the end of this post). I am not so well versed on the fabrication side of the issue, and I therefore don't know how to tweak these parameters. I don't need a very exact model, just some of the basic parameters would be sufficient. Can anybody help my find what these parameters are? I downloaded some HSpice models from the Xilinx website, but those seem to be just for the input/output pins, and not for the FPGA itself. Thanks, Berk .model cmosn nmos level = 1 VTO = 0.77 KP = 7.7e-5 GAMMA = 0.71 PHI = 0.73 LAMBDA = 0.0625 TOX = 3e-8 LD = 2e-7 U0 = 670 NSUB = 2e16 CGDO=1.6908E-10 CGSO=1.6908E-10 CGBO=5.0932E-10 CJ=2.8901E-04 MJ=5.3532E-01 CJSW=1.4790E-10 MJSW=1.0000E-01 PB=9.9000E-01 .model cmosp pmos level = 1 VTO = -1.1 KP = 2.1e-5 GAMMA = 0.355 PHI = 0.66 LAMBDA = 0.053 TOX = 3e-8 LD = 5e-8 U0 = 180 NSUB = 5e15 CGDO=1.6260E-10 CGSO=1.6260E-10 CGBO=4.2445E-10 CJ=2.8670E-04 MJ=4.2120E-01 CJSW=1.6584E-10 MJSW=1.2657E-01 PB=7.3408E-01Article: 136015
My PCIE SATA host controller , PCIE NIC ,pcie-pci bridge controller for ML555 have worked sucessfully. It is full RTL design,except for PCIE/GMAC GTP SerDes . It can be retargeted ASIC.any need plz email: arcdoos@yahoo.comArticle: 136016
Hi, In my FPGA design I will connect a ZBT ram to a Virtex4 FPGA. My question will be about the clock signal. I will create a clock signal in FPGA and connect it to the clock pin of the RAM through usual I/O pin. My doubt is that shall I use a clock buffer in between FPGA and RAM. I am using ISSI IS61NLP25636A ram. Thanks in advance. --enesArticle: 136017
austin schrieb:
> Virtex 5 has AES256, and Virtex 4 does also. These are strictly
> speaking, encryption, not authentication, but can be used to prevent
> cloning.
> ...
Thanks, I already knew about all the products/security mechanisms except
the Virtex 2 Pro.
> Search for papers by Saar Drimer (he is finishing his studies at
> Cambridge) who has done some good work in this area.
>
> http://www.cl.cam.ac.uk/~sd410/
Already did, his papers and the bibliography he put on his page are
really good. Another paper worth readinf is "Cryptography on FPGAs" by
Wollinger, Paar, Guajardo.
http://www.crypto.rub.de/imperia/md/content/texte/wollingeretal_acmtransembeddedsysfpgacryptooverview_final.pdf
In almost all papers I read on the subject it is said that it's easy to
read an unecrypted bitstream on an SRAM based FPGA during start up.
Exactly how easy is this? What kind of equipment/skill or education and
time would be required?
Regards,
Tobias
Article: 136018Paul Boven <p.boven@xs4all.nl> writes: > I'm not sure yet whether the input IOBs are clocking in the data > directly, I will try and find out through the FPGA editor. If not, > I'll add an extra level of registers, I guess. I don't know if you've come across this, but I've found in the past (ISE9.1) that the extra level of regs *has* to go in the top level for them to be packed into the IOs. I spent a while putting the extra level into the module that needed them, with no effect :( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 136019
Tobias <tobi_wan@gmx.de> writes: > In almost all papers I read on the subject it is said that it's easy > to read an unecrypted bitstream on an SRAM based FPGA during start > up. Exactly how easy is this? What kind of equipment/skill or > education and time would be required? Reading the bitstream is easy, just hang a logic analyser off the configuration interface and log the data. That gives you what you need to clone it. Understanding what that bitstream is a non-trivial task though... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 136020
Hi, In one of my project, I am using two FPGAs on a custom board. The first one is Xilinx Virtex-2 Pro XC2VP20 and the other one is Spartan-3 (XC3S400). Virtex-2 Pro FPGA is driven by a clock of 32MHz while Spartan-3 FPGA is driven by 19.6608MHz. A trivial approach to establish inter connectivity between the FPGAs working in different clock domains is through a FIFO. (Just a thought), I need to know if it is possible to provide 199.6608 MHz clock to Virtex-2 Pro FPGA as an output from Spartan-3 FPGA. Both the FPGA lie within 1.5 inches on multilayered board and whether the current requirement of input clock can be met from the output of FPGA pin ? Regards /MHArticle: 136021
On 2008-10-28, Philipp <Patrick.Bateman23@gmx.at> wrote: > Hi > > I have implemented a very simple processor architecture and I was now > taking a closer look at the floorplan using the Xilinx toolset. What I > saw there is rather strange. It not only seems that all the Registers of > the register file are > distributed all over the FPGA, even the single bits of the registers are > located at completly different locations. So I wonder if there is a > chance to tell ISE that it should instantiate a logic block that holds > all the registers of the register file in logic cells located next to > each other? There is a constraint called RLOC_RANGE which you might want to look into. It could probably help you with this. However, I would recommend that you look at your timing report to see if you would actually benefit from trying to optimize the register file at this point. If your critical path is not located in the register file you don't gain much by optimizing the register file... /AndreasArticle: 136022
"Enes Erdin" <eneserdin@gmail.com> wrote in message news:387d9650-4a23-46aa-abc4-c7b20d6ba866@t42g2000hsg.googlegroups.com... > Hi, > > In my FPGA design I will connect a ZBT ram to a Virtex4 FPGA. My > question will be about the clock signal. > > I will create a clock signal in FPGA and connect it to the clock pin > of the RAM through usual I/O pin. My doubt is that shall I use a clock > buffer in between FPGA and RAM. I am using ISSI IS61NLP25636A ram. > A clock buffer is not needed. I'm assuming that this is just a single RAM connected to the FPGA so the net is a simple two point net. If so, then simply put a series termination resistor near the source, and you'll be done. Kevin JenningsArticle: 136023
On 2008-10-28, Philipp <Patrick.Bateman23@gmx.at> wrote: > Its not about optimizing for speed or area. But for my purposes (we > wanna measure the EM of the register file) it would be helpful if the > registers are grouped all together! I see. This sounds pretty interesting, perhaps you could post something to this newsgroup once you have some results? In what context are you trying to measure this? Security research? /AndreasArticle: 136024
Hello, we're using EDK version 10.1 (with SP3) and have found the xps_tft controller in the project IP catalog which we're trying to implement. But we've run into some problems which we think is related to the DDR SDRAM because when using the MPMC IP we can't select the VFBC (Video frame buffer) option. Is there any information available on the xps tft controller or a tutorial on howto interface this IP block with the XUPV2P board (Virtex 2 Pro). Thanks
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