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On Oct 24, 12:20=A0pm, eubankss...@gmail.com wrote: > I am fairly new to CPL development, and I need to create an emulation > of a number of old bipolar Proms (256x4) being used in a very old > system by using a CPLD and WInCUPL. > > My approach was to use the example "Lookup.pld" as a basis for my LUT, > with the exception that I am trying to use 8 bits of address to > produce a 4 bit output for each of the possible 256 inputs. > > Using an AT22V10, I am able to (sometimes) create a table of 256 > elements in length. -which I have verified to function in a circuit > BTW- =A0However, I have noticed that there are certain sequences of > values (most, in fact) that will give me errors: "too many Product > terms" for each bit of the 4 bit output. So my approach is apparently > not the "general solution" that I need. (I have the data for the parts > that I need to emulate, and they appear to be "random" values) There > does not appear to be any optimization selection that helps either. > > I have also tried using the AT750x series, hoping that the additional > gates would help. -Same issue. > > Atmel technical support tried to help, however, I was unable to > communicate my problem well enough. I was provided a modified example > of "Lookup.pld". The issue I have with the example they sent is that > there are still only 6 bits of input used, and even though I tried my > best to expand the provided solution, I almost always (eventually) > ended up with the same issue -not enough product terms. > > I am wondering if its possible to use some of the address bits (lets > say 2 for example), that would be used to "select" which table to use. > IOW, the 2 bits would select one of 4 tables, each of six bits in > length to address the proper element in the table. Would doing this > save product terms? > > I cannot get the above approach to work either. This was the approach > I pitched to Atmel tech support, and was told that it should work, > although like I said earlier, the example provided, was not > sufficient. perhaps I am missing something(???) > > What bothers me the most about the issue is that I am trying to re- > create something that was created back in the late '70s to early '80s, > the chips obviously function, so I am wondering how it was done. I am > using a 21st century development tool with optimizers, etc.... > > I was up until 2:30 last night struggling with this. (and I'm not > counting the countless hours already spent over the past few weeks) > > Please Help if you have any ideas!. I do not want to resort to using > High-density CPLDs or FPGAs (size & cost are the main isssues with > that) > > Sorry if this email was long-winded, but I wanted to explain my > problem with enough fidelity to hopefully get some real help. Thank > you for reading all of this! If you can live with more than one macrocell delay you may be able to get more tables to work. Using just the 8 ins and 4 outs will always be limited by the product terms and rule out certain tables even if they have very simple structure like the exclusive OR of all the inputs. Using more than one level of logic (with a 22V10 you can have 6 macrocells feeding back into your design in addition to the 4 outputs) you may be able to get your job done, but it will cost you in the output delay time. I had similar issues making a parallel 8b10b encoder and decoder, but found that with mach210 I could use two levels of logic and do it quite handily. The other obvious approach is to actually use a PROM if you can find one within your budget (speed, size and $$). I had used small synchronous PROMs from Cypress in my original 8b10b design, but back then they were more expensive than a CPLD. Regards, GaborArticle: 135976
On Oct 24, 9:20 am, eubankss...@gmail.com wrote: > > What bothers me the most about the issue is that I am trying to re- > create something that was created back in the late '70s to early '80s, > the chips obviously function, so I am wondering how it was done. I am > using a 21st century development tool with optimizers, etc.... > It's not a 'this century' vs/ 'last century' issue. It's a device capability issue. Decoding in the PROM you mention is like having 256 OR terms for every output. You PAL has (IIRC) 12 OR terms max per output. And 256 is larger than 12. True last century, true this. ;)Article: 135977
On Oct 23, 2:50 am, adventurer <hry...@gmail.com> wrote: > Hello newsgroup! > > I=92m going to implement my FPGA based SoC with embedded processor. Now > I=92m trying to choose soft processor. The main feature for me it=92s a > good CAD performance and ease to use. I start to work with Xilinx > EDK, and the questions is : Can I integrate my EDK processor system in > some top-level schematic, like a component, such as I can do this in > Quartus. There are many threads about problem of choose a software > processor: Nios vs MicroBlaze and others, but it=92s interesting to > hear opinions the people who work with both of them, or who study this > problem more thoroughly. What are the advantages and disadvantages of > every cores? Both NIOS and MicroBlaze really want you to create your custom logic as a system (Avalon/OPB) core, and let the processor system instantiate it. And both allow you to create a soft core and instantiate that in another module of your choosing. But it's a (minor) pain to do with either. I work with both, and I really have no preference. Whatever the customer wants, that's what they get. G.Article: 135978
In article <29f6f706-9a1a-4a31-b7df-bca8733765d7@p10g2000prf.googlegroups.com>, <steveu@coppice.org> wrote: <SNIP> > >Going to market with an impractical product is much worse than toying >and figuring out its impractical before you spend the big bucks. I >remember when the Inmos people kept trying to sell their filter chip >into a board I was doing. The board's BOM target was about 130 pounds >(more or less met in the end), while their chip in 100k volume was >something like 800 pounds. I guess the salesman had few other leads to >follow if he kept wasting his time on us. What is "impractical" about the first device to manage doing the first quantum chromatic calculation? What was "impractical" about the interactive graphical displays of oil wells on the Meico's at Shell Rijswijk? (Hint, the alternative at the time was tying up Shell's Cray. The transputer boxes where an order of magnitude less expensive.) I don't argue with the lack of commercial prowess though. If they just had managed to keep up with increasing clock speeds, instead of going to 9000, they might still be in business. > >Regards, >Steve Groetjes Albert -- -- Albert van der Horst, UTRECHT,THE NETHERLANDS Economic growth -- like all pyramid schemes -- ultimately falters. albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horstArticle: 135979
John Adair <g1@enterpoint.co.uk> wrote: > Finally photos of new baby PC104/PC104+ board Hollybush2 are now Nice. How many IO pins are available on the connectors? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 135980
eubanksster@gmail.com wrote: > I am fairly new to CPL development, and I need to create an emulation > of a number of old bipolar Proms (256x4) being used in a very old > system by using a CPLD and WInCUPL. > > My approach was to use the example "Lookup.pld" as a basis for my LUT, > with the exception that I am trying to use 8 bits of address to > produce a 4 bit output for each of the possible 256 inputs. > > Using an AT22V10, I am able to (sometimes) create a table of 256 > elements in length. -which I have verified to function in a circuit > BTW- However, I have noticed that there are certain sequences of > values (most, in fact) that will give me errors: "too many Product > terms" for each bit of the 4 bit output. So my approach is apparently > not the "general solution" that I need. (I have the data for the parts > that I need to emulate, and they appear to be "random" values) There > does not appear to be any optimization selection that helps either. > > I have also tried using the AT750x series, hoping that the additional > gates would help. -Same issue. > > Atmel technical support tried to help, however, I was unable to > communicate my problem well enough. I was provided a modified example > of "Lookup.pld". The issue I have with the example they sent is that > there are still only 6 bits of input used, and even though I tried my > best to expand the provided solution, I almost always (eventually) > ended up with the same issue -not enough product terms. > > I am wondering if its possible to use some of the address bits (lets > say 2 for example), that would be used to "select" which table to use. > IOW, the 2 bits would select one of 4 tables, each of six bits in > length to address the proper element in the table. Would doing this > save product terms? > > I cannot get the above approach to work either. This was the approach > I pitched to Atmel tech support, and was told that it should work, > although like I said earlier, the example provided, was not > sufficient. perhaps I am missing something(???) > > What bothers me the most about the issue is that I am trying to re- > create something that was created back in the late '70s to early '80s, > the chips obviously function, so I am wondering how it was done. I am > using a 21st century development tool with optimizers, etc.... > > I was up until 2:30 last night struggling with this. (and I'm not > counting the countless hours already spent over the past few weeks) > > Please Help if you have any ideas!. I do not want to resort to using > High-density CPLDs or FPGAs (size & cost are the main isssues with > that) > > Sorry if this email was long-winded, but I wanted to explain my > problem with enough fidelity to hopefully get some real help. Thank > you for reading all of this! > > If you look in detail, I think you can see the difficulty in what you are doing. Look at one bit. You want that bit to be high at a certain number of 8 bit addresses. To decode this, you need to decode each of those addresses (subject to some small amount of optimization but ignore that for a minute) and then OR the results together. If a bit is high for 100 addresses, you need to have 100 8 bit decoders and a 100 bit OR gate. That is very expensive in terms of logic resources. If you want a memory, it is better to use a memory. > >Article: 135981
Brian Drummond wrote: > > In ISE10 it doesn't seem painfully slow to me, unless you have exceeded > the project size limitation, though I haven't raced it against Modelsim. > As I mentioned, I haven't installed 10.1 at home yet; with 9.2, under the code size limit, it takes about 4 minutes (3 min. compile / 1 min. run) for a testbench that requires about 13 seconds (2s/11s) in another tool. BrianArticle: 135982
On Oct 24, 12:24=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > But it has to be stable.Then if I feed a square wave of say > > 10ns period. > > Do you allways have periodic signals? That is a completely different > story than random signal. If you want to phase shift a periodic signal > you can use delay locked loops or phase locked loops. > > I get the effective delay between the original and the > > > delayed signal as 0 ps. If I increase the input period to 10.001ps, I > > get the delay to be 1ps and similarly for an input period of 9.999ns I > > get a delay of -1ps. So all I require here is a fixed constant delay > > like that of a passive element. > > Any signal inside an FPGA will have more than 100ps jitter. All you > can hope > for is an average delay resolution in that order. > Even with specialized discrete analog hardware it is hard to get into > the range of 1ps jitter even for clock signals let alone for logic. > > Kolja Sulimmawww.cronologic.de I am actually not interested in instantaneous delay(jitter)...all I want is the average delay over a period of time to be constant. Finally I was able to get the delay... I had to tell the mapper not to touch the intermediate signals and not to eliminate the buffers by using the statement like this....Now it synthesizes each and every inverter and I get the delay I require... :-) . . . signal inv1 : STD_LOGIC; attribute s: string; attribute s of inv1: signal is "yes"; A0 : INV port map(inv1,core_clk); . . . Thanks, PratapArticle: 135983
Hello, I want to download a simple VHDL program to FPGA Xilinx Virtex-4. I am using ISE 10.1 and iMPACT 10.1. the code is very simple. it is an AND gate that works at clock high ------------------------------ process(clk) begin if (clk'event and clk = '1') then y <= a and b; end if; end process; ------------------------------ I am very new in FPGA programing. the behavioral,post-translate,post-map and post-route simulation works fine. I just want to know the steps to download the program to FPGA. I have few questions as well: 1. How will I assign me signals (clk, a, b, y) to the ports/pins of FPGA? 2. How should I give the inputs (clk, a, b)? Can I do this using switches of the FPGA board? How to connect the FPGA ports to the switches? 3. How should I take output (y)? Should I use the LED of the board? How to connect output port of FPGA with the LED? 4. Do I have to code any .ucf file manually? How to code .ucf for this simple program? Someone may think these questions very childinsh. But as I am very new in this field and getting no advisor/instructor to help me, these are very crucial to me. Hope to get help from you soon. Best regards, PanthoArticle: 135984
Pratap wrote: > > I am actually not interested in instantaneous delay(jitter)...all I > want is the average delay over a period of time to be constant. > Finally I was able to get the delay... > I had to tell the mapper not to touch the intermediate signals and not > to eliminate the buffers by using the statement like this....Now it > synthesizes each and every inverter and I get the delay I > require... :-) > . > . > . > signal inv1 : STD_LOGIC; > attribute s: string; > attribute s of inv1: signal is "yes"; > A0 : INV port map(inv1,core_clk); > . > . > . > Thanks, > Pratap THis delay has absolutely none of the requirements you asked for. You do not have 1ps class resolution. The stability is not there with temperature and local activity affecting your overall delay by as much as 10%. Part of the art of getting useful information from a pool of experienced individuals on a newsgroup is asking the right question!Article: 135985
Thank you for offering this solution. I would like to experiment with this approach. But I am not sure if I understand what the CUPL code would look like to do this. Are you saying that instead of 4 bit outputs (what I have now) that I would instead use some bits of the outputs going back into the chip? For example, if I used 6 bits of output, are you saying that I would use the additional 2 bits to somehow perform a 1-of-4 selector that would select a given table of each table having a length of -in this example- 64 addresses? If I could see a short code snippet, I think it would help me to understand this better. > If you can live with more than one macrocell delay you may be able to > get more tables to work. =A0Using just the 8 ins and 4 outs will always > be limited by the product terms and rule out certain tables even if > they have very simple structure like the exclusive OR of all the > inputs. =A0Using more than one level of logic (with a 22V10 you > can have 6 macrocells feeding back into your design in addition > to the 4 outputs) you may be able to get your job done, but > it will cost you in the output delay time. =A0I had similar issues > making a parallel 8b10b encoder and decoder, but found that > with mach210 I could use two levels of logic and do it quite > handily.Article: 135986
I have tried to locate a "real" datasheet for the PROM's (MB7052) but have only found pinouts, no detailed description of how they were used. Were MB7052s also programmed using a compiled form of Boolean expressions just like the part(s) I am using? Since you describe them as having 256 OR terms, then I am thinking that the architecture of these older devices is somewhat similar to the one I am using. Due to the small size (16 pin DIP) then I am curious if perhaps there is an alternate solution by using a different (modern) part. It seems that from a functional point-of-view, I need a 256-by-4 memory chip. (these days its easy to find 256 *MegaBytes*! but 256-by-4 sounds like a joke by today's standards ;>) My form- factor requirements preclude the use of most of the high-density CPLDs (I think) Is there by chance a vendor that that you know of that currently provides CPLDs that would meet my capacity requirements but packaged as a small SOIC or similar? (IOW, something that could easily fit within the size of a 16 pin DIP) I have looked around, but most go down to 44pin QFP which would still be too large. thanks again for your input. On Oct 24, 5:01=A0pm, d_s_kl...@yahoo.com wrote: > On Oct 24, 9:20 am, eubankss...@gmail.com wrote: > > > > > What bothers me the most about the issue is that I am trying to re- > > create something that was created back in the late '70s to early '80s, > > the chips obviously function, so I am wondering how it was done. I am > > using a 21st century development tool with optimizers, etc.... > > It's not a 'this century' vs/ 'last century' issue. =A0It's a device > capability issue. > > Decoding in the PROM you mention is like having 256 OR terms for every > output. > > You PAL has (IIRC) 12 OR terms max per output. > > And 256 is larger than 12. =A0True last century, true this. =A0;)Article: 135987
Pantho, Pin assignments are done through the ucf file. Since you are using an evaluation board you must have an example ucf file for this board. Take a look at it. Compare it against the board's schematics. All you need is 3 lines describing your 3 pins. At the next step you might want to add timing constraints, but I guess they are not required for what you are doing now. In ISE10.1 there is a way of editing the ucf file indirectly, but I think in your case it will be easier to manually edit the existing file. When you are done with the ucf file add it to the project, run synthesis and implementation phases and then run Generate Programming File. This will produce a bit file, which you will be able to load into the device with iMPACT (which can be called through Configure Target Device in the processes window in ISE10.1, but I recommend to open it separately) using one of the Xilinx programming cables. /Mikhail "500milesaway" <500milesaway@gmail.com> wrote in message news:UcadneCzaI_znZ7U4p2dnAA@giganews.com... > > Hello, > > I want to download a simple VHDL program to FPGA Xilinx Virtex-4. I am > using ISE 10.1 and iMPACT 10.1. the code is very simple. it is an AND gate > that works at clock high > ------------------------------ > process(clk) > begin > if (clk'event and clk = '1') then > y <= a and b; > end if; > end process; > ------------------------------ > I am very new in FPGA programing. the behavioral,post-translate,post-map > and post-route simulation works fine. I just want to know the steps to > download the program to FPGA. > > I have few questions as well: > > 1. How will I assign me signals (clk, a, b, y) to the ports/pins of FPGA? > 2. How should I give the inputs (clk, a, b)? Can I do this using switches > of the FPGA board? How to connect the FPGA ports to the switches? > 3. How should I take output (y)? Should I use the LED of the board? How to > connect output port of FPGA with the LED? > 4. Do I have to code any .ucf file manually? How to code .ucf for this > simple program? > > Someone may think these questions very childinsh. But as I am very new in > this field and getting no advisor/instructor to help me, these are very > crucial to me. Hope to get help from you soon. > > Best regards, > > Pantho >Article: 135988
eubanksster@gmail.com wrote: > I have tried to locate a "real" datasheet for the PROM's (MB7052) but > have only found pinouts, no detailed description of how they were > used. Were MB7052s also programmed using a compiled form of Boolean > expressions just like the part(s) I am using? These are memory chips, they are not CPLDs. Each address is programmed with the data they wanted. > > Since you describe them as having 256 OR terms, then I am thinking > that the architecture of these older devices is somewhat similar to > the one I am using. No, they do not have the same architecture at all. The memory chip has 1024 memory locations set up as 256x4, each group of four is addressed by an 8 bit AND to pick the address. There is effectively a 256 to 1 multiplexer to select which of the memory elements is sent to the output pins. Often this was a wired OR for simplicity. The CPLD is intended as a logic device. Since you do not have 1024 memory storage units in the CPLD, you have to make it up with logic. Suppose bit 1 is high at address 1 and 10. You have to decode adresses 1 with an 8 bit AND and you have to decode address 10 with another 8 bit AND. You then need a 2 bit OR to allow both addresses. In general, a memory would be done as something like bit1 = addra or addrb or addrc or addrd ... Where addra, addrb etc are the addresses that you want to have the bit =1. Each of the addra etc are 8 bit ANDs (assuming that each of the inputs has a polarity invert. If not, then you need 16 line available). If an output bit is high for half of the addresses, you have used up 128 8 bit ANDs. Times 4 that is a lot of logic. Your CPLD has maybe 10 of these. They are not meant to be memories. Due to the small size (16 pin DIP) then I am > curious if perhaps there is an alternate solution by using a different > (modern) part. It seems that from a functional point-of-view, I need a > 256-by-4 memory chip. (these days its easy to find 256 *MegaBytes*! > but 256-by-4 sounds like a joke by today's standards ;>) My form- > factor requirements preclude the use of most of the high-density CPLDs > (I think) If you need a memory, use a memory. Get a large memory and only use part of it. You can get flash memory in a variety of small packages and even though you will have megabytes of memory, you only need to use what you want. > > Is there by chance a vendor that that you know of that currently > provides CPLDs that would meet my capacity requirements but packaged > as a small SOIC or similar? (IOW, something that could easily fit > within the size of a 16 pin DIP) I have looked around, but most go > down to 44pin QFP which would still be too large. You want a memory chip, not a CPLD. > > thanks again for your input. > > > On Oct 24, 5:01 pm, d_s_kl...@yahoo.com wrote: > >>On Oct 24, 9:20 am, eubankss...@gmail.com wrote: >> >> >> >> >>>What bothers me the most about the issue is that I am trying to re- >>>create something that was created back in the late '70s to early '80s, >>>the chips obviously function, so I am wondering how it was done. I am > > > > >>>using a 21st century development tool with optimizers, etc.... >> >>It's not a 'this century' vs/ 'last century' issue. It's a device >>capability issue. >> >>Decoding in the PROM you mention is like having 256 OR terms for every >>output. >> >>You PAL has (IIRC) 12 OR terms max per output. >> >>And 256 is larger than 12. True last century, true this. ;) > >Article: 135989
Hi!
I'm trying to connect my virtex-4 ML403 board with the DLC9 cable
(USB) under Linux (Fedora).
Installed the linux usb-driver from http://www.rmdir.de/~michael/xilinx/
and preloaded it (LD_PRELOAD). Also put the .hex files and the .rules
files to the correct dir.
I 've chosen output->cable setup -> usb cable.
The output of impact is this:
INFO:iMPACT:501 - '1': Added Device xc4vfx12 successfully.
...
Connecting to cable (Usb Port - USB22).
Checking cable driver.
File version of /vlsi_soft/xilinx_ise9.1i/bin/lin/xusbdfwu.hex =
1025(dec), 0x0401.
File version of /usr/share/xusbdfwu.hex = 1025(dec), 0x0401.
libusb-driver.so version: 2007-10-16 14:54:24.
Cable connection failed.
The LED on the USB cable box is still OFF.
lsusb shows the follwing:
Bus 004 Device 003: ID 03fd:0007 Xilinx, Inc.
Do I have to install any other drivers or software additionally to
this usb-driver wrappers?
Thanks for hints!
regards, Ralph
Article: 135990hmmm... I've replied to some of the posts here (thanks for your input) but my new posts do not show up! I am not sure if my replies have actually been sent!.Article: 135991
<lichaoji@gmail.com> wrote in message news:uhc77tlny.fsf@CNCJ03.i-did-not-set--mail-host-address--so-tickle-me... > > Hi, guys > > I learned fpga and vhdl years ago in university, built a toy cpu and > something like that. Not much. > > Now I want to pick up and do some hobby project, but I have no idea what > board in the market is for people like me. It has to be robust and > cheap. > > Any recommendation? > > thanks a lot. > > chaoji Hi Chaoji, Perhaps these free online videos may also assist your selection: Video #3 - part 1/2: Five questions to ask before you choose an FPGA board Video #3 - part 2/2: FPGA boards and general advice on what to get http://www.burched.com/freevideos.ag.php Best regards, Tony BurchArticle: 135992
The problem is strange. Our platform is ML555 with Xilinx V5. We need transport data from PC to DRAM on the board through PCI Express Edge. And we successfully did this on DELL XPS with nForce 680i motherboard. But when we set up to do it on DELL t5400 workstation with Intel 5400 we got random errors that the data we loopback from the SDRAM on the board were wrong and out of order. I just wondering that which part can produce such errors, PCI Express DMA app or DDR2 Controller? By the way, what we using are all sample application provided by Xilinx. Thanks, Sam LiuArticle: 135993
Thank you very much, Mikhail. I am using Xilinx Virtex-4 LX MB Development Kit, FPGA is Virtex-4 xc4vlx60-ffg668. I dont have any example ucf file for the board. how can i get the example ucf for the board? Thanks in advance panthoArticle: 135994
500milesaway wrote: > I am using Xilinx Virtex-4 LX MB Development Kit, FPGA is Virtex-4 > xc4vlx60-ffg668. I dont have any example ucf file for the board. how can i > get the example ucf for the board? I don't have this board, but searching Google for Xilinx Virtex-4 LX MB Development Kit ucf results in this PDF: http://www.xilinx.com/support/documentation/boards_and_kits/ug078.pdf and on page 7 is written, that the UCF file is on the CD-ROM. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 135995
Hi, I need to perform some Spice simulations for a Virtex-II Pro FPGA. I downloaded the HSpice files from Xilinx' web site, but it turns out those are only for the input-output pins. What I need to do is to find out what a signal looks like after going through the look-up tables. Is there a way I can get spice models for those? As a matter of fact, if only I can roughly figure out the values for the various parameters in the CMOS model, I believe I should be fine. For instance, right now I am using the model I included below. The values for VTO, KP, GAMMA etc.. are not representative of the Virtex-II fabrication process. How can I find some of these values for the specific FPGA I am using? I don't even need all of the parameters, just some of the major ones. Any help would be greatly appreciated! Best, Berk This is the model that I am using right now: .model cmosn nmos level = 1 VTO = 0.77 KP = 7.7e-5 GAMMA = 0.71 PHI = 0.73 LAMBDA = 0.0625 TOX = 3e-8 LD = 2e-7 U0 = 670 NSUB = 2e16 CGDO=1.6908E-10 CGSO=1.6908E-10 CGBO=5.0932E-10 CJ=2.8901E-04 MJ=5.3532E-01 CJSW=1.4790E-10 MJSW=1.0000E-01 PB=9.9000E-01Article: 135996
samliu wrote: > The problem is strange. > Our platform is ML555 with Xilinx V5. We need transport data from PC to > DRAM on the board through PCI Express Edge. And we successfully did this on > DELL XPS with nForce 680i motherboard. But when we set up to do it on DELL > t5400 workstation with Intel 5400 we got random errors that the data we > loopback from the SDRAM on the board were wrong and out of order. > I just wondering that which part can produce such errors, PCI Express DMA > app or DDR2 Controller? By the way, what we using are all sample > application provided by Xilinx. > > Thanks, > Sam Liu Hi, This problem bit me some months ago, and it's actually documented in the PCIe specification. The completions coming back to the board responding to non-posted requests, are split in several smaller packets. This small packets can 'pass' other packets. ie. Requests NPA, NPB, NPC come back on some motherboards like you'd expect: CA1, CA2, CA3, CB1, CB2, CB3, CC1, CC2, CC3 But, on other mo-bos: CA1, CB1, CC1, CA2, CB2, CC2, CA3, CB3, CC3. I know it looks crazy. If you were stacking the data as it comes (ie. into a FIFO), you'd need to sort it before storing it. I used an array of 8 FIFOs to hold the data temporarily until all pieces of a completion were received. Another approach would be to store the data by their packet address, so it orders it as it is received. This way is how I perceive they intended the interface to be used, ie. mapped into memory. HTH, -P@Article: 135997
PatC wrote: > samliu wrote: >> The problem is strange. >> Our platform is ML555 with Xilinx V5. We need transport data from PC to >> DRAM on the board through PCI Express Edge. And we successfully did >> this on >> DELL XPS with nForce 680i motherboard. But when we set up to do it on >> DELL >> t5400 workstation with Intel 5400 we got random errors that the data we >> loopback from the SDRAM on the board were wrong and out of order. >> I just wondering that which part can produce such errors, PCI Express DMA >> app or DDR2 Controller? By the way, what we using are all sample >> application provided by Xilinx. >> >> Thanks, >> Sam Liu > > Hi, > > This problem bit me some months ago, and it's actually documented in > the PCIe specification. The completions coming back to the board > responding to non-posted requests, are split in several smaller packets. > This small packets can 'pass' other packets. > > ie. > Requests NPA, NPB, NPC come back on some motherboards like you'd expect: > > CA1, CA2, CA3, CB1, CB2, CB3, CC1, CC2, CC3 > > But, on other mo-bos: > > CA1, CB1, CC1, CA2, CB2, CC2, CA3, CB3, CC3. > > I know it looks crazy. If you were stacking the data as it comes (ie. > into a FIFO), you'd need to sort it before storing it. I used an array > of 8 FIFOs to hold the data temporarily until all pieces of a completion > were received. > Another approach would be to store the data by their packet address, > so it orders it as it is received. This way is how I perceive they > intended the interface to be used, ie. mapped into memory. > > HTH, > -P@ > > Each request gets a Tag value, and the completions have matching Tag values. You need to match up the tags to see which completions are connected to which requests. If you had a real-time PCI Express Analyzer, admittedly a lot of money, you would see this. RBArticle: 135998
My PCIE SATA host controller , PCIE NIC controller ,pcie-pci bridge for ML555 have worked sucessfully. It is full RTL design,except for PCIE/GMAC GTP SerDes . It can be retargeted ASIC.any need plz email: arcdoos@yahoo.comArticle: 135999
Hi,
I'm trying to write a driver for my LCD, the Sitronix ST7066U on
my Spartan 3E starter kit and i'm having a bit of trouble
understanding something. The user guide tells you
that there is 4-bit data bus and the lower 4-bits are unused. But a
page or 2 down the user guide it tells you that you need to use these
lower 4-bits to access characters. That's very confusing.
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