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fl wrote: > I do use Nios IDE. The above message is from the IDE. I want to know > what is wrong with the IDE. Thanks. I think you need to re-install. It should work out-of-the-box. IIRC it asks you somewhere whether or not you want to set the environment variables... You haven't installed a later version of Quartus on the same machine? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136151
On Mon, 3 Nov 2008 13:00:03 -0800 (PST), fl <rxjwg98@gmail.com> wrote: >Hi, >I want to learn Nios with its examples: hello. Although the >environment is correct, see below: > >SOPC_KIT_NIOS2=C:\altera\72\quartus\nios2eds > >I have check it both on control panel and cmd window. > >The following error message apperes. I can see both app_rules.mk and >gnu_rules.mk exist at the build directory. What is wrong with that? >Thanks in advance. > > > >--------------------------------------------------------------------------------------------- >**** Build of configuration Debug for project hello_world_2 **** > >make -s all includes >make: /bin/sh.exe: Command not found >make: /bin/sh.exe: Command not found >make: /bin/sh.exe: Command not found >make: /bin/sh.exe: Command not found >make: /bin/sh.exe: Command not found >C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: >153: /components/altera_hal/build/gnu_rules.mk: No such file or >directory >C:/altera/72/quartus/nios2eds/components/altera_hal/build/app_rules.mk: >157: /components/altera_hal/build/gtf_rules.mk: No such file or >directory >make: *** No rule to make target `/components/altera_hal/build/ >gtf_rules.mk'. Stop. >Build completed in 2.637 seconds Under windows you need to add %SOPC_KIT_NIOS2%\sdk2\bin to path. If make doesn't work on commandline you must be missing that line in your path. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 136152
> You mean that the file and/or format in which the ip manager certainly > stores this information into one of the component's files is unknown? no, in my understanding the information (for synthesis) is stored in the mif/coe files you already found. out of this, coregen creates a (in your case huge ;) ) vhdl/verilog simulation file with many small RAMB16 components with their INIT generics. ciaoArticle: 136153
On Nov 4, 6:48=A0am, y.tachw...@gmail.com wrote: > On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > > > On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote: > > > > Hello Guys, > > > > I am trying to move a current project files that contain PCI Xilinx I= P > > > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the > > > project. The ISE 7.x does not have "export source" function. Also, I > > > have tried to move the following files: (.v , .xco and .ucf) and have > > > created a new project with the same target and same name in ISE 10.1 > > > and started adding the source files (.v , .xco and .ucf). That allowe= d > > > me to synthesize the project successully but did not allow me to > > > implement the design. It fails from the first step "translate" ! and > > > lists the following log: > > > Why are you making it so hard? =A0Just make a copy of the -entire- > > ISE-7.1 project (sub-directories and all) and open the project with > > ISE-10.1 > > > ISE will convert is for you. > > > Alex > > Hello Alex, > > Thanks for your reply... I have tried that also and ISE asked me to > convert it and make automatically a backupfile of the old one > but ..... unfortunately I end up with the same errors... I have to > emphasis that there is an IP core used in the project. so maybe I have > to set up the ISE 10.1 to recognize the IPcores available in the other > station were ISE7.1 resides. So probably there is a procedure I need > to follow or so? Any clues :(- Hide quoted text - > > - Show quoted text - Did you try option "Regenerate all cores" before performing synthesis. I one of my experiences, I was unable to synthesize an ISE-7.1 design in ISE-8.2 till I regenerated all cores. Hope this Helps Regards /MHArticle: 136154
Dear all, In the course of my research on static timing analysis, I need to simulate the timing behaviour of Gaisler Research FPU (GRFPU). Xilinx and Altera netlists are available on the website, but they require the commercial versions of these 2 tools. It would be so kind if someone sends me the SDF and VHDL simulation files (from Xilinx, these can be obtained using the tools: NGDBUILD and NDG2VHDL). Thanks in advance! Regards! Mohamed Compiler Research Group Universit=E4t des Saarlandes PS Actually it would be a good idea for the Gaisler Research guys to put the SDF and VHDL simulation code on the website, along with netlists!Article: 136155
On Mon, 3 Nov 2008 18:47:47 -0800 (PST), Brian Davis <brimdavis@aol.com> wrote: >Brian Drummond wrote: >> >> ... and I have seen *some* evidence that there *may* be a problem with >> pipeline delays implemented as variables (actually a variable array, to >> easily control the length); or the transition between signals and such >> delays. About a year ago, on XST 7.1. > I saw a similar bug in XST 9.1 (fixed in 9.2), that would >drop (add?) a pipeline stage on inferred memories under certain >conditions. > XST attempts to push extra register stages into the BRAM by >enabling the output pipeline register; under certain conditions, >XST would lose track of what it was doing, and wire up the BRAM >incorrectly. Interesting... possibly related, but not the exact same bug. BRAMS are far too precious in this app for this purpose. But it may make a related mistake with SRL16s. - BrianArticle: 136156
Hi there everyone, I hope I could find my answer here. I am looking for RS-232 bus controller design in VHDL. To be precise, I need the Receiver and Transmitter coding in VHDL. I will only be using 3 pins out of 9 pins of the DB9. There are RXD , TXD and ground signals. My DTE is PC while my DCE is Xilinx Spartan 3. Im planning to send data using hyperterminal from PC to RS-232 receiver and this receiver will display the date at a 7-segment display. On the other hand, There will be a 8 bits switch to send data back to PC to be displayed at the hyper terminal. help is appreciated ... thanksArticle: 136157
On Mon, 3 Nov 2008 15:58:13 -0800 (PST), y.tachwali@gmail.com wrote: >Hello Guys, > >I am trying to move a current project files that contain PCI Xilinx IP >Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the >project. It sounds liek the process you have followed is reasonable... perhaps it's worth focussing on the actual error? >ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>" LOC = >"T8" |> > [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. >..... and alot of similar error messages (ERROR:ConstraintSystem:59 ) I would suggest generating a post-synthesis simulation netlist, opening it in a text editor, and searching for "AD_IO". (I find this easier to use than the RTL view for this sort of purpose!) You may find nets called "PCI_CORE_AD_IO<0>" (where the hierarchy separator is "_" not"/") or "MY_MODULE/PCI_CORE/AD_IO<0>" (where the hierarchical name has been extended) or simply "ADIO<0>" where it has been shortened, or some similar change. The first can be fixed by setting the hierarchy separator character (on the "Synthesis Properties" dialog); others may be fixable by editing the relevant UCF constraints to reflect the actual signal names. - BrianArticle: 136158
In comp.arch.fpga, ikki <jasperng10@gmail.com> wrote: > Hi there everyone, I hope I could find my answer here. > > I am looking for RS-232 bus controller design in VHDL. To be precise, I > need the Receiver and Transmitter coding in VHDL. These controllers are commonly known as UART. Google the words UART and VHDL and you will find a lot of examples. Add the word Treseler to the search if you want to find an example by someone who reads this group frequently. A UART is not very hard to code and often used as an example. If you know how a UART works (get a datasheet of one), it is not that hard to write your own. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) No man would listen to you talk if he didn't know it was his turn next. -- E.W. HoweArticle: 136159
On Nov 3, 11:53=A0pm, Mark McDougall <ma...@vl.com.au> wrote: > fl wrote: > > I do use Nios IDE. The above message is from the IDE. I want to know > > what is wrong with the IDE. Thanks. > > I think you need to re-install. It should work out-of-the-box. IIRC it > asks you somewhere whether or not you want to set the environment variabl= es... > > You haven't installed a later version of Quartus on the same machine? > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Yes. I did install a Quartus 8.0sp1. I previously installed Quartus 8.0 without Nios II. Because I can access Quartus 7.2 subscription. I installed Quartus 7.2 subscription. Then it failed when I installed Nios II 8.0. I cannot uninstall Quartus 8.0 or Quartus 7.2 when I want to reinstall them. I have tried to uninstall Sentinel first, I still cannot uninstall 8.0 or 7.2. How to uninstall them? Thanks.Article: 136160
>In comp.arch.fpga, >ikki <jasperng10@gmail.com> wrote: >> Hi there everyone, I hope I could find my answer here. >> >> I am looking for RS-232 bus controller design in VHDL. To be precise, I >> need the Receiver and Transmitter coding in VHDL. > >These controllers are commonly known as UART. Google the words UART and >VHDL and you will find a lot of examples. Add the word Treseler to the >search if you want to find an example by someone who reads this group >frequently. > >A UART is not very hard to code and often used as an example. If you >know how a UART works (get a datasheet of one), it is not that hard >to write your own. > > >-- >Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) > >No man would listen to you talk if he didn't know it was his turn next. > -- E.W. Howe > Thanks for you reply, I know there are plenty of UART. However most of them incorporate handshaking signals which i do not need it for my design. THus, Im just looking for a simple rs232 UART design. Also, Im also wondering anyone has the block diagram (architecture) of the RS232 UART ? ...Article: 136161
In comp.arch.fpga, ikki <jasperng10@gmail.com> wrote: >>In comp.arch.fpga, >>ikki <jasperng10@gmail.com> wrote: >>> Hi there everyone, I hope I could find my answer here. >>> >>> I am looking for RS-232 bus controller design in VHDL. To be precise, > I >>> need the Receiver and Transmitter coding in VHDL. >> >>These controllers are commonly known as UART. Google the words UART and >>VHDL and you will find a lot of examples. Add the word Treseler to the >>search if you want to find an example by someone who reads this group >>frequently. >> >>A UART is not very hard to code and often used as an example. If you >>know how a UART works (get a datasheet of one), it is not that hard >>to write your own. >> >> >>-- >>Stef (remove caps, dashes and .invalid from e-mail address to reply by > mail) >> >>No man would listen to you talk if he didn't know it was his turn next. >> -- E.W. Howe >> > > Thanks for you reply, > > I know there are plenty of UART. However most of them incorporate > handshaking signals which i do not need it for my design. THus, Im just > looking for a simple rs232 UART design. > > Also, Im also wondering anyone has the block diagram (architecture) of the > RS232 UART ? ... > Have you actually entered "UART VHDL" (without the quotes) in the google search field and followed any of the result links? Doesn't sound like it, if I do that there are at least 4 simplified uarts (tx/rx only) on the first result page. There's even a code downloadable example in those first results. And what if you only found more complicated examples? Cutting them down to what you need shouldn't be that hard. And try following a few links on that search page, you might even find block diagrams and stuff. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) I'm using my X-RAY VISION to obtain a rare glimpse of the INNER WORKINGS of this POTATO!!Article: 136162
In comp.arch.fpga, ikki <jasperng10@gmail.com> wrote: > > I know there are plenty of UART. However most of them incorporate > handshaking signals which i do not need it for my design. THus, Im just > looking for a simple rs232 UART design. Furthermore... You say 'most' of them include handshaking. This implies that you also found at least one which didn't, or else you would have written 'all'. What was wrong with the one(s) without handshake? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Never make anything simple and efficient when a way can be found to make it complex and wonderful.Article: 136163
Michael Dreschmann wrote: ... > Does anyone know of such a module or knows what's wrong with the > example from the xapp610? Have a look at this page: http://www3.elphel.com/ The source of those cameras is available as open source and one of the first camera models using M-JPEG has an encoder based on the XAPP610. I assume the author did get it to work. If not, there are several examples of JPEG encoders on opencores. Cheers, GuenterArticle: 136164
Hi I have just sythesized 3 different design of an IP core and to my surprise the clock frequency of the 3 design are quite different (between 55 and 85 MHz). I assumed that all 3 designs should have almost the same critical path delay. Has Xilinx a tool included in their ISE 10.1 that allows me to easily track down the critical path of each design? One of the designs uses almost all the logic of the FPGA so I assume that here less duplication of logic could lead to a lower frequency? Thanks in advance, KlausArticle: 136165
I had just another quick look at the timing summary and it seems that
as I expected: The combinatinal path delay is basically the same for all
3 designs. However, I am wondering why I get now such a significant
difference in the minimum period? Anyone an idea what I have to track
down here to get clarification?
Design 1:
Minimum period: 17.040ns (Maximum Frequency: 58.687MHz)
Minimum input arrival time before clock: 1.681ns
Maximum output required time after clock: 6.731ns
Maximum combinational path delay: 2.318ns
Design 2:
Minimum period: 23.811ns (Maximum Frequency: 41.997MHz)
Minimum input arrival time before clock: 1.681ns
Maximum output required time after clock: 6.733ns
Maximum combinational path delay: 2.318ns
Article: 136166What do "real" engineers do when they want to preserve the ability to connect a JTAG pod to a device, but board layout/space concerns prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG header that's common on all the JTAG Products? I'm somewhat envisioning a tiny small-pin-count press-to-fit connector, but I have no idea. Are there any standards in this area? Thanks! ...EricArticle: 136167
Klaus wrote: > I had just another quick look at the timing summary and it seems that > as I expected: The combinatinal path delay is basically the same for all > 3 designs. However, I am wondering why I get now such a significant > difference in the minimum period? Anyone an idea what I have to track > down here to get clarification? > > > Design 1: > Minimum period: 17.040ns (Maximum Frequency: 58.687MHz) > Minimum input arrival time before clock: 1.681ns > Maximum output required time after clock: 6.731ns > Maximum combinational path delay: 2.318ns > > Design 2: > > Minimum period: 23.811ns (Maximum Frequency: 41.997MHz) > Minimum input arrival time before clock: 1.681ns > Maximum output required time after clock: 6.733ns > Maximum combinational path delay: 2.318ns The first tool to condult is the Xilinx Timing Analyzer to get a detailed breakdown of all the componenets that make up your delay. Technology viewers can help you visually see the logic cones. I use SynplifyPro for synthesis so the HDL Analyst is part of my everyday synthesis; it's a tool which allows very clean visual representation of the synthesized results.Article: 136168
> The first tool to condult is the Xilinx Timing Analyzer to get a > detailed breakdown of all the componenets that make up your delay. Yes thanks, I will have a look at this. However, my understanding was always that basically the longest combinational path determines the critical path of the design. So I am surprised that two designs with the same combinational delay path can have such different minimum periods they are operating. I guess this difference could also be a direct result of longer routing delays? So basically effects that I wouldnt encounter with an ASIC implementation?Article: 136169
Hi, Another tool you may want to try is PlanAhead. The lite version is included with 10.1i. Regards, Stephan "Klaus" <Klaus@gmx.at> wrote in message news:geptsl$qom$1@aioe.org... > >> The first tool to condult is the Xilinx Timing Analyzer to get a >> detailed breakdown of all the componenets that make up your delay. > > Yes thanks, I will have a look at this. However, my understanding was > always that basically the longest combinational path determines the > critical path of the design. So I am surprised that two designs with the > same combinational delay path can have such different minimum periods they > are operating. I guess this difference could also be a direct result of > longer routing delays? So basically effects that I wouldnt encounter with > an ASIC implementation?Article: 136170
Hi. I'm trying to get the SDI Megacore Function with Triple Standard to work. It requires the DPRIO Block and the ALT2GXB Reconfig Block. When simulating with Modelsim, 'channel_reconfig_done' goes low immediately after power up . If I assert 'write_all' nothing happens.Article: 136171
Eric <jonas@mit.edu> wrote: >What do "real" engineers do when they want to preserve the ability to >connect a JTAG pod to a device, but board layout/space concerns >prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG >header that's common on all the JTAG Products? > >I'm somewhat envisioning a tiny small-pin-count press-to-fit >connector, but I have no idea. Are there any >standards in this area? Not really. I used a 1.27mm pitch dual row (2x5) header on a product. But it is intended to be used with a parallel port JTAG wiggler so speed (signal integrity) wasn't one of my concerns. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 136172
On Tue, 4 Nov 2008 08:31:39 -0800 (PST), Eric <jonas@mit.edu> wrote: >What do "real" engineers do when they want to preserve the ability to >connect a JTAG pod to a device, but board layout/space concerns >prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG >header that's common on all the JTAG Products? > >I'm somewhat envisioning a tiny small-pin-count press-to-fit >connector, but I have no idea. Are there any >standards in this area? > >Thanks! > ...Eric The Xilinx/Digilent boards use a 6-pin, single row, 0.1" pitch connector. That's probably too big for your board, though. -Dave PollumArticle: 136173
On Tue, 04 Nov 2008 16:39:49 +0000, Klaus <Klaus@gmx.at> wrote: > >> The first tool to condult is the Xilinx Timing Analyzer to get a >> detailed breakdown of all the componenets that make up your delay. > >Yes thanks, I will have a look at this. However, my understanding was >always that basically the longest combinational path determines the >critical path of the design. So I am surprised that two designs with the >same combinational delay path can have such different minimum periods >they are operating. I guess this difference could also be a direct >result of longer routing delays? So basically effects that I wouldnt >encounter with an ASIC implementation? How do you find out the "longest combinational path" for both designs? Your best option is to look at the timing report and find the longest path in actual gates and compare them. Find the register to register path which has the largest delay from the timing report and compare it with your expectations. Routing delays can be one explanation for timing difference and in an ASIC the routing overhead would not be as pronounced as FPGAs but still there. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 136174
ikki wrote:
> I know there are plenty of UART. However most of them incorporate
> handshaking signals which i do not need it for my design. THus, Im just
> looking for a simple rs232 UART design.
Like this?
port (
clock : in std_ulogic;
reset : in std_ulogic;
address : in std_ulogic;
writeData : in std_logic_vector(char_len_g-1 downto 0);
write_stb : in std_ulogic;
readData : out std_logic_vector(char_len_g-1 downto 0);
read_stb : in std_ulogic;
serialIn : in std_ulogic;
serialOut : out std_ulogic
);
http://mysite.verizon.net/miketreseler/uart.vhd
> Also, Im also wondering anyone has the block diagram (architecture) of the
> RS232 UART ? ...
http://mysite.verizon.net/miketreseler/uart.pdf
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