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> How do you find out the "longest combinational path" for both
> designs?
As I posted earlier, it says in the timing summary the following:
Design 1:
Minimum period: 17.040ns (Maximum Frequency: 58.687MHz)
Minimum input arrival time before clock: 1.681ns
Maximum output required time after clock: 6.731ns
Maximum combinational path delay: 2.318ns
Design 2:
Minimum period: 23.811ns (Maximum Frequency: 41.997MHz)
Minimum input arrival time before clock: 1.681ns
Maximum output required time after clock: 6.733ns
Maximum combinational path delay: 2.318ns
So for 2 designs exactly the same combinational path delay (2.318ns),
however, the have a complete minimum period!
Article: 136176On Tue, 04 Nov 2008 17:27:45 +0000, Klaus <Klaus@gmx.at> wrote: > >> How do you find out the "longest combinational path" for both >> designs? > >As I posted earlier, it says in the timing summary the following: > > >Design 1: > Minimum period: 17.040ns (Maximum Frequency: 58.687MHz) > Minimum input arrival time before clock: 1.681ns > Maximum output required time after clock: 6.731ns > Maximum combinational path delay: 2.318ns > >Design 2: > > Minimum period: 23.811ns (Maximum Frequency: 41.997MHz) > Minimum input arrival time before clock: 1.681ns > Maximum output required time after clock: 6.733ns > Maximum combinational path delay: 2.318ns > >So for 2 designs exactly the same combinational path delay (2.318ns), >however, the have a complete minimum period! I think you're misinterpreting that line. That statement is for reporting of delays from input pins to output pins without any intervenning registers. You need to look at the timing report to actually see what the max register to register delay is to decide what's limiting your maximum period. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 136177
"Nico Coesel" <nico@puntnl.niks> wrote in message news:49107e8c.511125379@news.planet.nl... > Eric <jonas@mit.edu> wrote: > >>What do "real" engineers do when they want to preserve the ability to >>connect a JTAG pod to a device, but board layout/space concerns >>prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG >>header that's common on all the JTAG Products? >> >>I'm somewhat envisioning a tiny small-pin-count press-to-fit >>connector, but I have no idea. Are there any >>standards in this area? > > Not really. I used a 1.27mm pitch dual row (2x5) header on a product. > But it is intended to be used with a parallel port JTAG wiggler so > speed (signal integrity) wasn't one of my concerns. > Signal integrity is still important on TCK. If not treated properly it can, and will, bite your butt. Bob -- == All google group posts are automatically deleted due to spam ==Article: 136178
Thanks for the help. I did have to switch to WinZip to decompress the files. After two weeks of BS, finally had someone from Xilinx call. Sound like they have some problem with our account not being setup for the correct licensing. Anyone else having problems since they dropped the DVDs? It's like a mad house over there now. I was able to get ISIM working to some degree. It seems to crash a lot (exits program). Must say it looks better than I expected. I can't seem to find a manual for it on the Xilinx site or in the on- line manuals. Has one been wrote that I can download from somewhere? I also seem to be having a problem getting the DCMs to do anything when using the behavioral simulation. Just now trying post route to see if this will work.Article: 136179
> I also seem to be having a problem getting the DCMs to do anything > when using the behavioral simulation. =A0Just now trying post route to > see if this will work. That was a bust. The tool gives some wacked out C code errors and stops. The project I am using for my evaluation will build correctly and I have been running various versions of it on hardware for a few years. Parts of it, including the DCMs were simulated in Aldec. So I'm guessing ISIM is just a little too new to use it yet. If they plan to continue to develop it like XST, I think it could be a useable tool down the road.Article: 136180
Eric wrote: > What do "real" engineers do when they want to preserve the ability to > connect a JTAG pod to a device, but board layout/space concerns > prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG > header that's common on all the JTAG Products? You only need 6 pins. I actually use 8, 3 grounds, VCC, and TMS, TCLK, DIN and DOUT. JonArticle: 136181
On Nov 4, 4:48=A0am, "ikki" <jaspern...@gmail.com> wrote: > Hi there everyone, I hope I could find my answer here. > > I am looking for RS-232 bus controller design in VHDL. To be precise, I > need the Receiver and Transmitter coding in VHDL. > > I will only be using 3 pins out of 9 pins of the DB9. There are RXD , TXD > and ground signals. > > My DTE is PC while my DCE is Xilinx Spartan 3. Im planning to send data > using hyperterminal from PC to RS-232 receiver and this receiver will > display the date at a 7-segment display. On the other hand, There will be= a > 8 bits switch to send data back to PC to be displayed at the hyper > terminal. > > help is appreciated ... thanks Picoblaze comes with serial comms stuff. At least, I think that's what I used some time ago.Article: 136182
Hi I would like to get a bit more aquantaited with using FPGAs and I thought of learning from courses and tutorials on http://www.techonline.com There seems to be interesting material, especially one like this here http://www.techonline.com/learning/course/210600272 but it costs 20 Dollars... So I am wondering if there are any other sites out there where I can learn this kind of stuff? Many thanks, ClaireArticle: 136183
On Nov 4, 6:31=A0pm, Claire <Cla...@hotmail.com> wrote: > Hi > > I would like to get a bit more aquantaited with using FPGAs and > I thought of learning from courses and tutorials on > > http://www.techonline.com > > There seems to be interesting material, especially one like this here > > http://www.techonline.com/learning/course/210600272 > > but it costs 20 Dollars... So I am wondering if there are any other > sites out there where I can learn this kind of stuff? > > Many thanks, > Claire Look here: http://www.xilinx.com/support/training/free-courses.htm for a list of free online classes from Xilinx. You have to register for some of them, but the classes are free. Regards, John McCaskill www.FasterTechnology.comArticle: 136184
Hi
Im using EDK9.1 and Trying to implement a standalone TCP/IP stack in a
microblaze processor core.
I tried to implement Lwip version 2.00.a coming free with EDK 9.1.
I have checked lwip stack in Software platform settings and
When i tried to do "Generate Libraries and BSPs".
Im getting this error.
ERROR:MDT - lwip () - error copying
"./src/contrib/ports/v2pro/netif/xemacliteif_polled.c" to
"./src/contrib/ports/v2pro/netif/xemacliteif.c": permission denied
while executing
"file copy -force "./src/contrib/ports/v2pro/netif/
xemacliteif_polled.c"
"./src/contrib/ports/v2pro/netif/xemacliteif.c""
(procedure "::sw_lwip_v2_00_a::generate" line 120)
invoked from within
"::sw_lwip_v2_00_a::generate 41183348"
ERROR:MDT - Error while running "generate" for processor
microblaze_0...
I tried to understand the error and tried to copy manually the file
netif/xemacliteif_polled.c to netif/xemacliteif.c
and i found that it is made readonly.
Well how can i do with it..?
Why the software makes it readonly and try to write to that file..?
Obviously it will give the error if anyone tries that
How can i get past this error...?
Any kind of help is highly appreciated
Article: 136185
I have 3 questions to ask regarding ML505 configurations.
1) How to configure Linear Flash on ML505 board? I generated .bin
files and in XILINX impact there is no option to configure linear
flash.
please tell me how to configure linear flash and suggest me any
tools to configure linear flash. Thank You.
2) and my 2nd questions is how to store bitstreams (data or programs )
into Flashes of ML505 and how to execute them?
i already loaded them via JTAG cable and i debugged them but
i want them to store in flashes and debug them. Thank You.
3) What is the need of 2 platform flashes on ML505 board? why they are
seperated?
Article: 136186On Nov 4, 1:59=A0am, Moazzam <moazzamhuss...@gmail.com> wrote: > On Nov 4, 6:48=A0am, y.tachw...@gmail.com wrote: > > > > > > > On Nov 3, 5:11=A0pm, LittleAlex <alex.lo...@email.com> wrote: > > > > On Nov 3, 3:58 pm, y.tachw...@gmail.com wrote: > > > > > Hello Guys, > > > > > I am trying to move a current project files that contain PCI Xilinx= IP > > > > Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the > > > > project. The ISE 7.x does not have "export source" function. Also, = I > > > > have tried to move the following files: (.v , .xco and .ucf) and ha= ve > > > > created a new project with the same target and same name in ISE 10.= 1 > > > > and started adding the source files (.v , .xco and .ucf). That allo= wed > > > > me to synthesize the project successully but did not allow me to > > > > implement the design. It fails from the first step "translate" ! an= d > > > > lists the following log: > > > > Why are you making it so hard? =A0Just make a copy of the -entire- > > > ISE-7.1 project (sub-directories and all) and open the project with > > > ISE-10.1 > > > > ISE will convert is for you. > > > > Alex > > > Hello Alex, > > > Thanks for your reply... I have tried that also and ISE asked me to > > convert it and make automatically a backupfile of the old one > > but ..... unfortunately I end up with the same errors... I have to > > emphasis that there is an IP core used in the project. so maybe I have > > to set up the ISE 10.1 to recognize the IPcores available in the other > > station were ISE7.1 resides. So probably there is a procedure I need > > to follow or so? Any clues :(- Hide quoted text - > > > - Show quoted text - > > Did you try option "Regenerate all cores" before performing synthesis. > I one of my experiences, I was unable to synthesize an ISE-7.1 design > in ISE-8.2 till I regenerated all cores. > > Hope this Helps > > Regards > /MH- Hide quoted text - > > - Show quoted text - Thank you for your reply... this attempt did not work... I am still having the same errors :(Article: 136187
On Nov 4, 4:53=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 3 Nov 2008 15:58:13 -0800 (PST), y.tachw...@gmail.com wrote: > >Hello Guys, > > >I am trying to move a current project files that contain PCI Xilinx IP > >Cores from ISE 7.1 to ISE 10.1. What it is the best way to move the > >project. > > It sounds liek the process you have followed is reasonable... > > perhaps it's worth focussing on the actual error? > > >ERROR:ConstraintSystem:59 - Constraint <NET "PCI_CORE/AD_IO<0>" =A0LOC = =3D > >"T8" |> > > =A0 [SigC6415.ucf(68)]: NET "PCI_CORE/AD_IO<0>" not found. =A0 > >..... and alot of similar error messages (ERROR:ConstraintSystem:59 ) > > I would suggest generating a post-synthesis simulation netlist, opening > it in a text editor, and searching for "AD_IO". (I find this easier to > use than the RTL view for this sort of purpose!) > > You may find nets called > "PCI_CORE_AD_IO<0>" (where the hierarchy separator is "_" not"/") > or > "MY_MODULE/PCI_CORE/AD_IO<0>" (where the hierarchical name has been > extended) or simply "ADIO<0>" where it has been shortened, > or some similar change. > > The first can be fixed by setting the hierarchy separator character (on > the "Synthesis Properties" dialog); others may be fixable by editing the > relevant UCF constraints to reflect the actual signal names. > > - Brian Thank you for your good advice... Sounds like I could reduce the number of errors by fixing the naming in the ucf file and reimplement. However, there is over 300+ name that need to be fixed and I am not sure if all of them can be this way... My thinking is that I need to move the PCI core over to the new ISE10.1 installation (only webpack with all web updates) from ISE7.1 but I do not know how to do that! I have read in Xilinx documentation that once you obtain the IP zip file, you need to expand it in C: \Xilinx\10.1\ISE\coregen\ip\xilinx so I thought instead I can move the PCI folder from the ISE 7.1 installation folder to C:\Xilinx\10.1\ISE \coregen\ip\xilinx and run the coregen hoping to detect a new core but it did not! Do you think that these error messages are because I have not install the PCI core in the 10.1 installation although it was able to synthesis? Thank you all for your great helpArticle: 136188
On Oct 9, 5:30=A0am, morphiend <morphi...@gmail.com> wrote: > On Oct 9, 6:45=A0am, lomtiks...@gmail.com wrote: > > > > > On Oct 6, 5:40 am, jason.hy...@gmail.com wrote: > > > > On Oct 6, 4:21 pm, lomtiks...@gmail.com wrote: > > > > > Hi everyone, > > > > > I would like to read a file from a CF card on xupv2p board using PL= B > > > > and Microblaze 7.10d. There are a few questions that I am trying to > > > > answer. > > > > > There is an xps_sysace interface controller v1.00a which seats betw= een > > > > the PLB and the system ace CF peripheral and has sysace v1_11_a dri= ver > > > > with functions like XSysAce_SectorRead and XSysAce_SectorWrite. > > > > However, I have not found any file system management soft like > > > > sysace_fopen and sysace_fread provided with XilFatfs FATFile System > > > > access library (xilfatfs_v1_00_a) that, from its doc, requires OPB > > > > SYSACE Interface Controller - Logicore module. How else would you r= ead > > > > files from the a CF via PLB? > > > > Would it require modifying xilfatfs to support PLB? > > > > > Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6 > > > > with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace. > > > > I am using MB 7.10a + plb + xps_sysace 1.00a with xilfatfs 1.00.a. I > > > also use > > > sysace_fopen, sysace_fread, sysace_fwrite for my sysace operations. S= o > > > I don't > > > think you need to redesign your system again.XSysAce_SectorRead and > > > XSysAce_SectorWrite are the raw operations as I remember. > > > Thanks Goran, Jason. It was great to hear the confirmation that > > xilfatfs worked for you with with the xps_sysace 1.00a. I came back to > > the original setup with PLB and xps_sysace and fixed all the > > compilation errors that I had. I also added the ddr ram plb controller > > and able to debug the code now. > > > I have another issue now that am trying to figure out. For some > > reason, when reading the first file, the program is hitting a > > _vector_sw_exception which I get after exiting > > int update_bufcache(int sector, unsigned char *sector_buf, int dirty) > > function. This function is called multiple times before the exception > > is made. > > > update_bufcache() is called by read_sector(), which in turn is read > > from read_from_file() > > > Why could this exception happen? > > I've checked my address ranges and they don't seem to overlap. > > I formatted my CF card as suggested by the xupv2p's user guide for > > 128mb with mkdosfs and placed a few images there, and the exception > > happens on the first. > > As example, I am using the slideshow code available from xilinx/ > > digilent:http://www.digilentinc.com/Products/Detail.cfm?Prod=3DXUPV2P > > I disabled //XCache_EnableDCache(0xF000000F) and // > > XCache_EnableICache(0xF000000F) lines. Could it relate to the problem? > > My DDR ram has these disabled in Assembly System View too. > > SW exception could be occuring because you compiled your software for > the wrong microblaze. In other words, you used instructions that were > not selected when the system was built. Hi, After debugging the problem further, I am sure I can open, read and close files from the CF card now. Everything is good while I am reading files with <=3D 12KBytes. The previously mentioned exception occurs when I read the next byte of the open file. The file is a bitmap with 54 Byte header, and body larger than ( 640pixels/line * 24bit/pixel * 6lines) / 8 ) + 714 Bytes. Total is 12288 Bytes =3D 12KB. The xilfatfs' PARAMETER CONFIG_BUFCACHE_SIZE =3D 16778, if that matters. PARAMETER CONFIG_MAXFILES =3D 8. I don't have XCache_EnableDCache(), XCache_EnableICache() enabled either. The allocated address to sysace is 128MB and I have under 8 files. I also reformatted the card to make sure it's not the problem. Any ideas? ThanksArticle: 136189
Hi, I am connecting xps_tft controller v1.00a to Microblaze 7.10.c. The TFT document suggests that uB should be connected to TFT controller via DCR bridge (TFT is DCR slave) and TFT itself to PLB such that TFT is a PLB Master. My uB is a master on PLB. Does it make sense to have two masters or should uB become slave? I haven't tried, but it looks like TFT controller can only be completely connected to PLB without DCR for Power PC. Also, I am connecting the following ports to FPGA's pins or internal signals. However, I have doubts: DCR_Clk is connected to the main system clock DCR_Rst is connected to sys_bus_reset, same as PLB's Sys_Rst (PLB works) TFT_DPS (display scan, out) to VGA_COMP_SYNCH pin TFT_DE (data enable, out) to VGA_OUT_BLANK_Z pin SYS_TFT_CLK (input) to the main system clock Thanks for the suggestions in advanceArticle: 136190
On Nov 4, 4:24=A0pm, mng <michael.jh...@gmail.com> wrote: > On Nov 4, 4:48=A0am, "ikki" <jaspern...@gmail.com> wrote: > > > Hi there everyone, I hope I could find my answer here. > > > I am looking for RS-232 bus controller design in VHDL. To be precise, I > > need the Receiver and Transmitter coding in VHDL. > > > I will only be using 3 pins out of 9 pins of the DB9. There are RXD , T= XD > > and ground signals. > > > My DTE is PC while my DCE is Xilinx Spartan 3. Im planning to send data > > using hyperterminal from PC to RS-232 receiver and this receiver will > > display the date at a 7-segment display. On the other hand, There will = be a > > 8 bits switch to send data back to PC to be displayed at the hyper > > terminal. > > > help is appreciated ... thanks > > Picoblaze comes with serial comms stuff. At least, I think that's what > I used some time ago. On that note, UartLite core is a simple UART controller. I used it with Microblaze without the flow control. However, it looks as you want to avoid EDK altogether.Article: 136191
Hi all, Is TFT Controller v1.00a for Microblaze 7 the easiest way to output video buffer to VGA screen? I was thinking of writing my own VGA controller, reading a line buffer stored in BRAM and having two copies of it to update one while the other one is read by the VGA controller. However, it seems as it is readily available as a pcore for smaller resolutions of 640x480, 18-bit bitmaps. Any comments? I would have to cut down on the originally planned resolution of 24- bits if I go with this option. ThanksArticle: 136192
On Nov 4, 9:20=A0am, "ikki" <jaspern...@gmail.com> wrote: > >In comp.arch.fpga, > >ikki <jaspern...@gmail.com> wrote: > >> Hi there everyone, I hope I could find my answer here. > > >> I am looking for RS-232 bus controller design in VHDL. To be precise, > I > >> need the Receiver and Transmitter coding in VHDL. > > >These controllers are commonly known as UART. Google the words UART and > >VHDL and you will find a lot of examples. Add the word Treseler to the > >search if you want to find an example by someone who reads this group > >frequently. > > >A UART is not very hard to code and often used as an example. If you > >know how a UART works (get a datasheet of one), it is not that hard > >to write your own. > > >-- > >Stef =A0 =A0(remove caps, dashes and .invalid from e-mail address to rep= ly by > mail) > > >No man would listen to you talk if he didn't know it was his turn next. > > =A0 =A0 =A0 =A0 =A0 =A0-- E.W. Howe > > Thanks for you reply, > > I know there are plenty of UART. However most of them incorporate > handshaking signals which i do not need it for my design. THus, Im just > looking for a simple rs232 UART design. > > Also, Im also wondering anyone has the block diagram (architecture) of th= e > RS232 UART ? ... It is a common misconception that RS232 is a communication protocol specification. In fact it only specifies the voltages used over the cables. RS232 signalling runs nominally at +/- 10 volts. However there are some implementations that use a positive threshold on the receiver and then drive only 0 to 5 volts on the interface. An example would be old Apple computers. No FPGA actually drives or receives RS232 signals directly. You need at a minimum an RS232 to logic-level transceiver.Article: 136193
FATAL_ERROR:Simulator:Fuse.cpp:424:$Id: Fuse.cpp,v 1.35.4.7 2008/05/28 00:03:05 droth Exp $ - Failed to compile generated C code isim/_tmp/simprim/a_3586507481_2973208550.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. FATAL_ERROR:Simulator:Fuse.cpp:424:$Id: Fuse.cpp,v 1.35.4.7 2008/05/28 00:03:05 droth Exp $ - Failed to compile generated C code isim/_tmp/ simprim/a_3586507481_2973208550.c Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Do a search on the errors and all Xilinx has is it being a problem in Linux. I was running it on plain jane XP Pro 32-bit.Article: 136194
On Nov 4, 6:22=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > Eric wrote: > > What do "real" engineers do when they want to preserve the ability to > > connect a JTAG pod to a device, but board layout/space concerns > > prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG > > header that's common on all the JTAG Products? > > You only need 6 pins. =A0I actually use 8, 3 grounds, VCC, and TMS, TCLK, > DIN and DOUT. > > Jon Real-world products usually already have some connectors on them. One approach is to use spare pins of an I/O connector or set up a dual-use for some pins. I have done this with Cardbus and Express- Card products, since the board will be in a sealed can when complete. Another approach is to just leave a few pads with no connector and build a fixture with pogo pins for production programming. Not very useful in the field, however. I have also used 1.27mm (.050") headers from Samtec on some products, but you will have limited access to wiring these unless you want to also design a mating card. For production this might not be a pad idea. Tiny wires in tiny sockets tend to break when used regularly. Regards, GaborArticle: 136195
Hi! You could also try the vga controller contained in the Genode FX project (fpga-graphics.org). It supports double buffering, vertical blank interrupts and fast clearing of memory. Timing and resolution are programmable. It requires an MPMC core for fetching the pixel data from external RAM. But it currently uses a color depth of 16 bits (RGB=565) as well. Matthias > Is TFT Controller v1.00a for Microblaze 7 the easiest way to output > video buffer to VGA screen? I was thinking of writing my own VGA > controller, reading a line buffer stored in BRAM and having two copies > of it to update one while the other one is read by the VGA controller. > However, it seems as it is readily available as a pcore for smaller > resolutions of 640x480, 18-bit bitmaps. > > Any comments? > I would have to cut down on the originally planned resolution of 24- > bits if I go with this option. > > ThanksArticle: 136196
Hi all,
I had now a look at the timing report from the Xilinx Timing Analyzer
for the 2 designs (Left out some things obviously :) )
Design 1:
Data Path Delay: 19.517ns (Levels of Logic = 13)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising
Destination Clock: clk_BUFGP rising
Clock Uncertainty: 0.000ns
Data Path: ARC_FF to ARC_NFF2
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.419
blabla (fanout=3) 1.091
....
....
---------------------------- ---------------------------
Total 19.517ns (6.639ns logic, 12.878ns route)
(34.0% logic, 66.0% route)
Design 2:
Data Path Delay: 36.101ns (Levels of Logic = 17)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising
Destination Clock: clk_BUFGP rising
Clock Uncertainty: 0.000ns
Data Path: ARC_FF to ARC_NFF2
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.419
blabla (fanout=3) 1.091
....
....
---------------------------- ---------------------------
Total 36.090ns (6.828ns logic, 29.262ns route)
(18.9% logic, 81.1% route)
So basically I could say that the logic between two registers is the
same but the routing complexity is so high that I have the long delays.
Is this right? What is confusing me is the timing summary output
Minimum period: 17.040ns (Maximum Frequency: 58.687MHz)
Minimum input arrival time before clock: 1.681ns
Maximum output required time after clock: 6.731ns
Maximum combinational path delay: 2.318ns
Here is says that the minimum period for design one is 17ns although the
timing analyzer shows me a critical path of length 19ns?
Thanks
Klaus
Article: 136197On Nov 5, 6:24 am, Gabor <ga...@alacron.com> wrote: > On Nov 4, 9:20 am, "ikki" <jaspern...@gmail.com> wrote: > > > > > >In comp.arch.fpga, > > >ikki <jaspern...@gmail.com> wrote: > > >> Hi there everyone, I hope I could find my answer here. > > > >> I am looking for RS-232 bus controller design in VHDL. To be precise, > > I > > >> need the Receiver and Transmitter coding in VHDL. > > > >These controllers are commonly known as UART. Google the words UART and > > >VHDL and you will find a lot of examples. Add the word Treseler to the > > >search if you want to find an example by someone who reads this group > > >frequently. > > > >A UART is not very hard to code and often used as an example. If you > > >know how a UART works (get a datasheet of one), it is not that hard > > >to write your own. > > > >-- > > >Stef (remove caps, dashes and .invalid from e-mail address to reply by > > mail) > > > >No man would listen to you talk if he didn't know it was his turn next. > > > -- E.W. Howe > > > Thanks for you reply, > > > I know there are plenty of UART. However most of them incorporate > > handshaking signals which i do not need it for my design. THus, Im just > > looking for a simple rs232 UART design. > > > Also, Im also wondering anyone has the block diagram (architecture) of the > > RS232 UART ? ... > > It is a common misconception that RS232 is a communication protocol > specification. In fact it only specifies the voltages used over the > cables. > > RS232 signalling runs nominally at +/- 10 volts. However there are > some > implementations that use a positive threshold on the receiver and then > drive only 0 to 5 volts on the interface. An example would be old > Apple > computers. > > No FPGA actually drives or receives RS232 signals directly. You need > at > a minimum an RS232 to logic-level transceiver. Just to pick a nit.... RS-232 does have a protocol. RTS-CTS, DSR-DTR, etc. V.24 describes the signal levels without mentioning the signal assertion/response. So the OP is really saying "I want RS-232 protocol WITHOUT the protocol". Still a miss-formed question. Cheers.Article: 136198
Hi, I need to configure Rocket IO GTP for 32 bit interface, but,GTP_DUAL is supporting only 16 bit as transceiver 0 and 1. Could you please help me out Rgds, BhaskarArticle: 136199
On Nov 5, 10:37=A0am, Klaus <Kl...@gmx.at> wrote: > So basically I could say that the logic between two registers is the > same but the routing complexity is so high that I have the long delays. > Is this right? Design 1: Data Path Delay: 19.517ns (Levels of Logic =3D 13) ... Design 2: Data Path Delay: 36.101ns (Levels of Logic =3D 17) I'm not sure why you would think that the logic between two registers is the same when the report shows that design 2 has four more levels of logic. That's not 'routing complexity'. KJ
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