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Saul Bernstein wrote:
> I just got an XC5VFX70T-FF1136 here on my desk, planning to put it on my
> self-designed board. I am just wondering what max. speed I can expect for my
> internal logic. The speed grade is -1 and I need to design logic running up
> to 582 MHz. Should I rather buy a speed grade -2 to be on the safe side or
> isn't that an issue?
Enter the critical logic and run static timing.
That will give you Fmax.
Can't afford many lut delays
between flops at that speed.
May have to trade latency for Fmax.
-- Mike Treseler
Article: 136376
lecroy7200@chek.com wrote:
> I wish I could post some sort of test case to replicate the problem,
> but it all appears random at this point.
Consider modelsim.
-- Mike Treseler
From rgaddi@technologyhighland.com Thu Nov 13 10:40:39 2008
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Date: Thu, 13 Nov 2008 10:40:39 -0800
From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: Efficient clock dividers
Message-Id: <20081113104039.5e7a87bd.rgaddi@technologyhighland.com>
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As I write yet another clock divider process yet another time, the same
question comes to mind once again. Given DIV (known at compile time),
is the more efficient implementation on a Xilinx FPGA (Spartan 3, but I
think the answer should be the same across the board):
A) Up-counter, 0 to DIV, compare to DIV and reset?
B) Down-counter, DIV to 0, watch for the carry out and reload?
C) Up-counter, -DIV to 0, watch for the carry out and reload?
My gut instinct is that B and C are equivalant (though C's less
readable), and are more efficient on both speed and area than A, but I
was hoping someone knew a little more certainly.
Yes, I realize that I'm fighting for both LUTs and picoseconds that I
almost never actually care about, but it just feels like something
that I do so many times I ought to do correctly.
Also, if B really is the right answer, is XST smart enough to figure
out how to do a carry-out from an 'integer'? Yes, I know how to have a
combinational process cast to a 'signed' with one more bit than
necessary, then do the subtraction, then use the MSB as the carry
signal and check that carry back in your clocked process, but talk about
your ugly ways to write something simple.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 136377
Uwe Bonnes wrote:
> What kind of constraints should be applied? This neither crosses
> uncorrelated time domains nor is a clear multi-cycle path.
the only place for clk in a synchronous design is (posedge clk)
(clk)? is considered harmful.
(we) is not synchronized to clk*2
> Pseudocode would look like:
>
> always @ (posedge clk)
> x_clk <= x;
> assign y = func(x_clk);
> assign we = (clk)? z:y;
>
> always @(posedge clk*2)
> if (we)
> out <= din;
>
> and the failing path is posedge clk -> x_clk -> y -> we @(posedge clk*2)
>
> Any help/examples welcome!
I would use one fast clock
and clock enables for the slower rates.
-- Mike Treseler
Article: 136378On Nov 13, 10:40=A0am, fl <rxjw...@gmail.com> wrote: > Hi, > I am trying to use Nios II with one Stratix II (2S60) DSP board, not > the Nios board. Even to use Nios /f in the simplest hello example, the > following error message is still there. What is the problem? Thanks > all. BTW, Using Quartus 7.2 subscription. > > **** Build of configuration Debug for project hello_world_1 **** > > make -s all includes > Linking hello_world_1.elf... > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region > onchip_mem is full (hello_world_1.elf section .text). Region needs to > be 41976 bytes larger. > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region > onchip_mem is full (hello_world_1.elf section .rwdata). Region needs > to be 3884 bytes larger. > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: > section .rodata [00002020 -> 000024ff] overlaps section .exceptions > [00002020 -> 000021c7] > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: > section .rwdata [00002500 -> 00003f2b] overlaps section .text > [000021c8 -> 0000d3f7] > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: > section .bss [00002020 -> 00002233] overlaps section .exceptions > [00002020 -> 000021c7] > /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ > bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/lib/mhw-mulx/ > mcustom-fpu-cfg=3D60-1//libc.a(sbrkr.o)(.text+0x14): In function > `_sbrk_r': > /build/nios2eds-gnutools-win32-7.2/bin/nios2-gnutools/src/newlib/ > newlib/libc/reent/sbrkr.c:59: Unable to reach errno (at 0x00002020) > from the global pointer (at 0x0000bec0) because the offset (-40608) is > out of the allowed range, -32678 to 32767. > > collect2: ld returned 1 exit status > make: *** [hello_world_1.elf] Error 1 > Build completed in 6.519 seconds I have increased instruction and data on chip memory to 64K. It is larger than the claimed 40K. Could you help me? Thanks.Article: 136379
fl wrote:
> Hi,
> I am trying to use Nios II with one Stratix II (2S60) DSP board, not
> the Nios board. Even to use Nios /f in the simplest hello example, the
> following error message is still there. What is the problem? Thanks
> all. BTW, Using Quartus 7.2 subscription.
>
>
>
>
>
>
> **** Build of configuration Debug for project hello_world_1 ****
Try release mode. You can switch this somewhere in the project settings in
Eclipse ("Properties" right-click menu item on the project).
--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Article: 136380"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message news:20081113104039.5e7a87bd.rgaddi@technologyhighland.com... > As I write yet another clock divider process yet another time, the same > question comes to mind once again. Given DIV (known at compile time), > is the more efficient implementation on a Xilinx FPGA (Spartan 3, but I > think the answer should be the same across the board): > > A) Up-counter, 0 to DIV, compare to DIV and reset? > B) Down-counter, DIV to 0, watch for the carry out and reload? > C) Up-counter, -DIV to 0, watch for the carry out and reload? > > My gut instinct is that B and C are equivalant (though C's less > readable), and are more efficient on both speed and area than A, but I > was hoping someone knew a little more certainly. IME, B and C should be equivalant (bugs notwithstanding), and A is less space efficient and runs slower. However, for maximum speed with a large number of bits, at the cost of area and simplicity, you can run a split counter - 3 bits (fits in well with LUT4's) running at the full speed, and n-3 bits running at 1/8th the speed. It requires a little bit of fancy footwork to link the two together, but it's not too difficult. It's easy to get it to work at 300 MHz or more on a S3 or similar, since you only have one level of logic and P&R usually does a good job. [...] -- Michael Brown Add michael@ to emboss.co.nz ---+--- My inbox is always openArticle: 136381
On Nov 13, 2:01=A0pm, Frank Buss <f...@frank-buss.de> wrote:
> fl wrote:
> > Hi,
> > I am trying to use Nios II with one Stratix II (2S60) DSP board, not
> > the Nios board. Even to use Nios /f in the simplest hello example, the
> > following error message is still there. What is the problem? Thanks
> > all. BTW, Using Quartus 7.2 subscription.
>
> > **** Build of configuration Debug for project hello_world_1 ****
>
> Try release mode. You can switch this somewhere in the project settings i=
n
> Eclipse ("Properties" right-click menu item on the project).
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys=
tems.de
Thanks. I change mode from Debug to Release. Although the memory
requirement is smaller (from 40K to 14K), it still has the same error
message.
The program is only a simple Hello_world. It should not be so memory
hungry.
Thanks,
**** Build of configuration Release for project hello_world_1 ****
make -s all includes
Compiling hello_world.c...
Linking hello_world_1.elf...
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region
onchip_mem is full (hello_world_1.elf section .text). Region needs to
be 14136 bytes larger.
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region
onchip_mem is full (hello_world_1.elf section .rwdata). Region needs
to be 2676 bytes larger.
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
section .rodata [00002020 -> 00002067] overlaps section .exceptions
[00002020 -> 000021c7]
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
section .rwdata [00002068 -> 00003a73] overlaps section .exceptions
[00002020 -> 000021c7]
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
section .bss [00002020 -> 00002233] overlaps section .exceptions
[00002020 -> 000021c7]
/cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/lib/mhw-mulx/
mcustom-fpu-cfg=3D60-1//libc.a(sbrkr.o)(.text+0x14): In function
`_sbrk_r':
/build/nios2eds-gnutools-win32-7.2/bin/nios2-gnutools/src/newlib/
newlib/libc/reent/sbrkr.c:59: Unable to reach errno (at 0x00002020)
from the global pointer (at 0x0000ba1c) because the offset (-39420) is
out of the allowed range, -32678 to 32767.
collect2: ld returned 1 exit status
make: *** [hello_world_1.elf] Error 1
Build completed in 8.297 seconds
Article: 136382fl wrote: > Thanks. I change mode from Debug to Release. Although the memory > requirement is smaller (from 40K to 14K), it still has the same error > message. The error sounds strange, maybe something with 16/32 bit CPU setting? Nios itself is sometimes strange, too. Do you have changed and recompiled the setting for the library project, too? > The program is only a simple Hello_world. It should not be so memory > hungry. If there is a printf, much of the library will be linked. If you have some LEDs for a hello world test, it could be much smaller. If it doesn't work, Altera has a very good support. Once I needed help with creating some special programming files and scripts for programming a flash behind a FPGA and they helped to solve the problem. Maybe this is one of the advantages of paying such high prices for the subscription (but there is good support for the web edition, too). -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 136383
Hi Bish, bish wrote: > Well now when we connected it with the target board the led keeps on > glowing with amber color but no green color. And while trying to > download bitstream, error occurs like cable not detected. > > ii) Further is there any way of checking whether the board is ok > downloading any bitstream to the fpga. And can we use anything other > than this platform cable usb to configure the fpga in Spartan 3a 1800a > dsp board. There is a default configuration file on that board, which will run some counting sequences on the green leds, drive the VGA with a rainbow pattern, and you can even talk to the RS232 to do a full suite of tests. Does the default configuration still exist and load/run? Do all the 3 power-supply LEDS (next to the 3 small power converter PCB modules) light? Btw., on my board only 2 of the three red LEDS light up because someone forgot to place resistor R152 on my board. :-( I've experienced several difficulties when programming my 3A-1800-DSP board as well (using a parallel cable from Digilent in my case). It would work great at home, but at other locations, I couldn't programm it - never really worked out why. Also, when loading a bitfile succeeds only partially, make sure that you check the temperature of your FPGA - mine got rather hot a couple of times after getting CRC errors on a configuration. Regards, Paul Boven.Article: 136384
Whilst trying to find out why my borrow out from a subtractor is
behaving incorrectly I noticed that some of my subtractors are signed
subtractors. This was shown by the ISE RTL schematic view. There are no
signed types in the verilog. So how could I have managed to do this?
{COm, Rd_contents}=Rn_contents - shifter_operand - BI;
The synthesis report records the subtractors as 33 bits wide.
shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
So is there a template for a subtractor using borrow in and borrow out
in verilog? e.g. I coded it wrongly.
Can I change one the data types into unsigned to force XST to make it
into an unsigned subtractor?
Synthesis is verilog 2001. I can use verilog 95 if it would help.
All suggestions gratefully listened to.
I am still learning verilog so please be gentle. Thanks in advance Andy.
Article: 136385> I would use one fast clock > and clock enables for the slower rates. In general, I agree this is the best design rule. But in this case that would mean a 200 MHz clock in a spartan 3e. Meeting timing at that high rate puts a burden on the rest of the design that is probably worse than dealing with the complexities of crossing clock domains in one small, limited part of the design. For example, I have a filter bank in a spartan 3e running at 206 MHz, but it required instantiating and handplacing primitives(flops and luts), and strictly only 1 lut level between flops. Regards AndrewArticle: 136386
>> I would use one fast clock
>> and clock enables for the slower rates.
Andrew FPGA wrote:
> In general, I agree this is the best design rule. But in this case
> that would mean a 200 MHz clock in a spartan 3e. Meeting timing at
> that high rate puts a burden on the rest of the design that is
> probably worse than dealing with the complexities of crossing clock
> domains in one small, limited part of the design.
I thought Uwe might like to try it the easy way first.
Synthesis is pretty smart when there is only one clock.
-- Mike Treseler
Article: 136387
On Nov 13, 4:32=A0pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote:
> Whilst trying to find out why my borrow out from a subtractor is
> behaving incorrectly I noticed that some of my subtractors are signed
> subtractors. This was shown by the ISE RTL schematic view. There are no
> signed types in the verilog. So how could I have managed to do this?
>
> {COm, Rd_contents}=3DRn_contents - shifter_operand - BI;
>
> The synthesis report records the subtractors as 33 bits wide.
> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>
> So is there a template for a subtractor using borrow in and borrow out
> in verilog? e.g. I coded it wrongly.
>
> Can I change one the data types into unsigned to force XST to make it
> into an unsigned subtractor?
>
> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>
> All suggestions gratefully listened to.
>
> I am still learning verilog so please be gentle. Thanks in advance Andy.
Just to understand this better, you're saying that the carry (or
borrow)
out is being messed up in the implementation? i.e. it looks like your
inputs are being sign-extended before the subtraction?
Another thing that bothers me is the lack of parentheses in the
equation.
Subtraction is one of those operators where a- (b - c) is not the
same as (a - b) - c, and if you guess the operator order incorrectly
you can have errors in the output as well.
Verilog 2001 does in fact have signed data types. How did you
define your 32-bit numbers? reg [31:0] foo? integer foo?
You can always force the correct behavior by zero-extending the
inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI
You may want to post this on comp.lang.verilog to get the guru's
view.
Regards,
Gabor
Article: 136388
Andy Botterill wrote:
> Can I change one the data types into unsigned to force XST to make it
> into an unsigned subtractor?
> All suggestions gratefully listened to.
http://groups.google.com/group/comp.lang.verilog/search?group=comp.lang.verilog&q=rules+sharp+unsigned+width-extended
From rgaddi@technologyhighland.com Thu Nov 13 15:05:00 2008
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Date: Thu, 13 Nov 2008 15:05:00 -0800
From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: Re: Efficient clock dividers
Message-Id: <20081113150500.01327165.rgaddi@technologyhighland.com>
References: <20081113104039.5e7a87bd.rgaddi@technologyhighland.com>
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On Thu, 13 Nov 2008 10:40:39 -0800
Rob Gaddi <rgaddi@technologyhighland.com> wrote:
> [snip]
> Also, if B really is the right answer, is XST smart enough to figure
> out how to do a carry-out from an 'integer'? Yes, I know how to have
> a combinational process cast to a 'signed' with one more bit than
> necessary, then do the subtraction, then use the MSB as the carry
> signal and check that carry back in your clocked process, but talk
> about your ugly ways to write something simple.
>
Yep, seems that there is:
rate_timer: integer range 0 to CLK_DIVISOR-1;
...
GO_TIMER: process(clk)
begin
if rising_edge(clk) then
if (rate_timer - 1 < 0) then
rate_timer <= CLK_DIVISOR - 1;
go <= '1';
else
rate_timer <= rate_timer - 1;
go <= '0';
end if;
end if;
end process GO_TIMER;
Is not recognized by XST as a modulo counter, but properly synthesizes
into a subtractor chain that runs the carry-out to the S or R inputs of
the registering flops accordingly.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 136389On Nov 12, 11:57=A0am, lomtiks...@gmail.com wrote: > On Nov 11, 4:34=A0am, lomtiks...@gmail.com wrote: > > > > > On Nov 11, 1:16=A0am, sundar <sundar....@gmail.com> wrote: > > > > On Nov 10, 3:45=A0pm, lomtiks...@gmail.com wrote: > > > > > Hi, > > > > > I am facing an issue of accessing the registers of a peripheral > > > > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBl= aze > > > > is on the PLB bus. The bridge is a slave on PLB and a master on DCR= . > > > > Please see below for a snippet of the .mhs file. > > > > > Since my peripheral has the C_DCR_BASEADDR =3D 0b0000000000, I assu= me it > > > > is register 0 on the PLB2DCR bridge and I can simply access it by > > > > looking at the base address of the PLB2DCR. For example, > > > > write_adress (0x87000000, value1) > > > > write_adress (0x87000004, value2) > > > > Does it make sense? > > > > > BEGIN plbv46_dcr_bridge > > > > =A0PARAMETER INSTANCE =3D plbv46_dcr_bridge_0 > > > > =A0PARAMETER HW_VER =3D 1.00.a > > > > =A0PARAMETER C_BASEADDR =3D 0x87000000 > > > > =A0PARAMETER C_HIGHADDR =3D 0x8700ffff > > > > =A0BUS_INTERFACE SPLB =3D mb_plb > > > > =A0BUS_INTERFACE MDCR =3D dcr_v29_0 > > > > END > > > > > BEGIN xps_tft > > > > =A0PARAMETER INSTANCE =3D xps_tft_0 > > > > =A0PARAMETER HW_VER =3D 1.00.a > > > > =A0PARAMETER C_DCR_SPLB_SLAVE_IF =3D 0 > > > > =A0PARAMETER C_TFT_INTERFACE =3D 0 > > > > =A0PARAMETER C_DEFAULT_TFT_BASE_ADDR =3D 0x10800000 > > > > =A0PARAMETER C_DCR_BASEADDR =3D 0b0000000000 > > > > =A0PARAMETER C_DCR_HIGHADDR =3D 0b0000000011 > > > > =A0BUS_INTERFACE MPLB =3D mb_plb > > > > =A0BUS_INTERFACE SDCR =3D dcr_v29_0 > > > > =A0PORT TFT_VSYNC =3D VGA_VSYNCH > > > > =A0PORT TFT_HSYNC =3D VGA_HSYNCH > > > > =A0PORT TFT_VGA_CLK =3D VGA_OUT_PIXEL_CLOCK > > > > =A0PORT SYS_TFT_Clk =3D tft_clk > > > > =A0PORT TFT_DE =3D VGA_OUT_BLANK_Z > > > > =A0PORT DCR_Rst =3D sys_bus_reset > > > > =A0PORT DCR_Clk =3D sys_clk_s > > > > =A0PORT TFT_VGA_R =3D VGA_OUT_RED > > > > =A0PORT TFT_VGA_G =3D VGA_OUT_GREEN > > > > =A0PORT TFT_VGA_B =3D VGA_OUT_BLUE > > > > END > > > > > Thank you in advance > > > > Hi, > > > > I am not sure how your other EDK setup files looks like but still tho= t > > > of sharing some info. > > > Note: PLB can be configured as 32,63 or 128 dwidth and address access > > > is by default 32. > > > DCR address access is 10 width so please study address translation > > > section of the Product spec. > > > Now coming to direct query ....the bridge core has registers > > > classified as slave access registers,interrupt registers. > > > I think slave access register may not start from 0. In this case DCR > > > is slave so make sure you are setting proper reg address space. > > > > Hope this helps. > > > > Sundar > > > Thanks for your comments, Sundar. > > > Following your advice, I've searched for slave access registers in > > plb2dcr bridge and tft controller and have not found the restrictions. > > There is a restriction for tft connected as slave on the plb bus, but > > from the eng doc it looks like it is an option for PPC only. I am > > using microblaze. In any case, I changed C_DCR_BASEADDR of tft > > controller peripheral to from 0b0010000000 to 0b0010000011 as one of > > the "ml401_emb_ref_71\projects\ml401_emb_ref" examples I found for > > ml401 board (it also uses microblaze, but opb2dcr bridge and tft on > > the dcr as a slave). Still I cannot change the register setting which > > is supposed to change the frame buffer pointer of the tft. Note that > > TFT is working fine for the default address that gets programmed with > > the bitstream (I can see the picture, but I cannot change to another > > memory location). > > > 2. So, to debug it further, I realized that I might have misconnected > > the ports on my peripheral. Previously, the xps_tft's DCR_Rst and > > DCR_Clk were connected to my 100MHz sys_bus_reset and sys_clk_s > > respectively and plb2dcr_bridge's PLB_dcrRst and PLB_dcrClk-- > > unconnected. So now, I connected these together because from the eng > > doc it looks like the PLB's clock has to clock the DCR via BUS2IP_Clk > > of the =A0bridge. So my mhs file is as below now, but still I cannot > > access the registers. > > BEGIN xps_tft > > =A0PARAMETER INSTANCE =3D xps_tft_0 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_DCR_SPLB_SLAVE_IF =3D 0 > > =A0PARAMETER C_TFT_INTERFACE =3D 0 > > =A0PARAMETER C_DEFAULT_TFT_BASE_ADDR =3D 0x10800000 > > =A0PARAMETER C_DCR_BASEADDR =3D 0b0010000000 <----------changed from > > 0b0000000000 > > =A0PARAMETER C_DCR_HIGHADDR =3D 0b0010000011 <----------changed from > > 0b0000000011 > > =A0BUS_INTERFACE MPLB =3D mb_plb > > =A0BUS_INTERFACE SDCR =3D dcr_v29_0 > > =A0PORT TFT_VSYNC =3D VGA_VSYNCH > > =A0PORT TFT_HSYNC =3D VGA_HSYNCH > > =A0PORT TFT_VGA_CLK =3D VGA_OUT_PIXEL_CLOCK > > =A0PORT SYS_TFT_Clk =3D tft_clk > > =A0PORT TFT_DE =3D VGA_OUT_BLANK_Z > > =A0PORT DCR_Rst =3D PLB_TO_DCR_RST > > =A0PORT DCR_Clk =3D PLB_TO_DCR_CLK > > =A0PORT TFT_VGA_R =3D VGA_OUT_RED > > =A0PORT TFT_VGA_G =3D VGA_OUT_GREEN > > =A0PORT TFT_VGA_B =3D VGA_OUT_BLUE > > END > > > BEGIN plbv46_dcr_bridge > > =A0PARAMETER INSTANCE =3D plbv46_dcr_bridge_0 > > =A0PARAMETER HW_VER =3D 1.00.a > > =A0PARAMETER C_BASEADDR =3D 0x87000000 > > =A0PARAMETER C_HIGHADDR =3D 0x8700ffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0BUS_INTERFACE MDCR =3D dcr_v29_0 > > =A0PORT PLB_dcrClk =3D PLB_TO_DCR_CLK <------------- new connection > > =A0PORT PLB_dcrRst =3D PLB_TO_DCR_RST <------------- new connection > > END > > > 3. I tried reading the memory directly from XMD and got "Debug memory > > access check failed. Section, 0x87000200-0x8700203 not accessible from > > processor debug interface. > > I used 0x87000200 because DCR's offset is 128 (C_DCR_BASEADDR =3D > > 0b0010000000) and to translate to PLB format, I multiplied by 4 as > > suggested. However, I also tried other values including 0x87000080, > > 0x87000100, 0x87000400, 0x87000800, 0x87001000, etc). Same result. > > > It looks like the address is either not decodable or not accessible > > due to misconnected ports. What do you think? > > Hello, > > I don't know where else I find find the answer to it, but I still > cannot access the registers of a device sitting on DCR bus over plb to > dcr bridge. How can I check whether the bridge is alive? (I don't have > chipscope) None of the peripheral's dcr registers are accessible. My > main suspicion is that the Rst and Clk pins are improperly connected. > Someone must have used this before. > I connected PORT PLB_dcrClk and PLB_dcrRst of the bridge to DCR_Clk > and DCR_Rst of the peripheral. > > I am sure that I am doing the proper register translation (tried both, > direct and multiplication by 4 as specified by the dcr spec). > > Thanks considering all your inputs i think your are almost close to the problem. i dont have any sample mhs of tft ctrl so i cant help on that. any thing related to dcr will fail if the address offsets are improper on the both the bus master and slave interfaces. this i knew becoz i was in the team who tested these cores. i suggest you contact xilinx customer support.Article: 136390
Gabor wrote:
> On Nov 13, 4:32 pm, Andy Botterill <a...@plymouth2.demon.co.uk> wrote:
>> Whilst trying to find out why my borrow out from a subtractor is
>> behaving incorrectly I noticed that some of my subtractors are signed
>> subtractors. This was shown by the ISE RTL schematic view. There are no
>> signed types in the verilog. So how could I have managed to do this?
>>
>> {COm, Rd_contents}=Rn_contents - shifter_operand - BI;
>>
>> The synthesis report records the subtractors as 33 bits wide.
>> shifter_operand, Rn_contents and Rd_contents are all 32 bits wide.
>>
>> So is there a template for a subtractor using borrow in and borrow out
>> in verilog? e.g. I coded it wrongly.
>>
>> Can I change one the data types into unsigned to force XST to make it
>> into an unsigned subtractor?
>>
>> Synthesis is verilog 2001. I can use verilog 95 if it would help.
>>
>> All suggestions gratefully listened to.
>>
>> I am still learning verilog so please be gentle. Thanks in advance Andy.
>
> Just to understand this better, you're saying that the carry (or
> borrow)
> out is being messed up in the implementation? i.e. it looks like your
> inputs are being sign-extended before the subtraction?
I'm not sure where the problem is yet. In my testbench I use this opcode
18 times. 2 times the borrow out (that would be a more obvious name than
COm sorry) is wrong. The borrow out is in the wrong state compared to my
pencil and paper calculations. The result (Rd_contents) is correct based
on the input data.
>
> Another thing that bothers me is the lack of parentheses in the
> equation.
> Subtraction is one of those operators where a- (b - c) is not the
> same as (a - b) - c, and if you guess the operator order incorrectly
> you can have errors in the output as well.
The output side is correct it's the borrow out side that I can't understand.
>
> Verilog 2001 does in fact have signed data types. How did you
> define your 32-bit numbers? reg [31:0] foo? integer foo?
reg [31:0] Rn_contents;
reg [31:0] Rd_contents;
reg [31:0] shifter_operand;
reg CO, COm, CI;
(* KEEP="TRUE" *) wire BI;
I only put the keep in there so that I can monitor the signal.
>
> You can always force the correct behavior by zero-extending the
> inputs yourself as in ({1'b0,a} - {1'b0,b}) - BI
Rn_contents and shifter_operand_out are already the correct size. Do you
really mean sign extend BI?
>
> You may want to post this on comp.lang.verilog to get the guru's
> view.
Let me do some checking before that. Thanks for the help.
>
> Regards,
> Gabor
Article: 136391I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :)Article: 136392
fl wrote:
> On Nov 13, 2:01 pm, Frank Buss <f...@frank-buss.de> wrote:
>> fl wrote:
>>> Hi,
>>> I am trying to use Nios II with one Stratix II (2S60) DSP board, not
>>> the Nios board. Even to use Nios /f in the simplest hello example, the
>>> following error message is still there. What is the problem? Thanks
>>> all. BTW, Using Quartus 7.2 subscription.
>>> **** Build of configuration Debug for project hello_world_1 ****
>> Try release mode. You can switch this somewhere in the project settings in
>> Eclipse ("Properties" right-click menu item on the project).
>>
>> --
>> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de
> Thanks. I change mode from Debug to Release. Although the memory
> requirement is smaller (from 40K to 14K), it still has the same error
> message.
> The program is only a simple Hello_world. It should not be so memory
> hungry.
> Thanks,
>
>
>
>
> **** Build of configuration Release for project hello_world_1 ****
>
> make -s all includes
> Compiling hello_world.c...
> Linking hello_world_1.elf...
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region
> onchip_mem is full (hello_world_1.elf section .text). Region needs to
> be 14136 bytes larger.
This message indicates that the linker thinks you've got no memory _at
all_ for the text section! So memory is not to small, but probably badly
mapped. I suggest you look at (and compare) the linker configuration and
SOPC/NIOS configuration.
-- Bas
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region
> onchip_mem is full (hello_world_1.elf section .rwdata). Region needs
> to be 2676 bytes larger.
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
> section .rodata [00002020 -> 00002067] overlaps section .exceptions
> [00002020 -> 000021c7]
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
> section .rwdata [00002068 -> 00003a73] overlaps section .exceptions
> [00002020 -> 000021c7]
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld:
> section .bss [00002020 -> 00002233] overlaps section .exceptions
> [00002020 -> 000021c7]
> /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/
> bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/lib/mhw-mulx/
> mcustom-fpu-cfg=60-1//libc.a(sbrkr.o)(.text+0x14): In function
> `_sbrk_r':
> /build/nios2eds-gnutools-win32-7.2/bin/nios2-gnutools/src/newlib/
> newlib/libc/reent/sbrkr.c:59: Unable to reach errno (at 0x00002020)
> from the global pointer (at 0x0000ba1c) because the offset (-39420) is
> out of the allowed range, -32678 to 32767.
>
> collect2: ld returned 1 exit status
> make: *** [hello_world_1.elf] Error 1
> Build completed in 8.297 seconds
Article: 136393Hi I have been using an emac core to be implemented as standalone in an FPGA. I was successful in implementing the core, but failed in PHY layer. Im using an SMSC MII 83C185 chip and i have been trying to configure it through an MDIO interface which i seperately implemented (not the one comes with the core). I have clocked the MDC at 1Mhz(specifications tell it to be no greater then 2.5Mhz). And i have been trying to write the registers for PHY configuration. In this regard i failed even though i have not found any timing mismatch between signals. So i tried to crack down the problem. I tried a working processor core implementation for ethernet in a starter kit and i tried to read the MDC clock and MDIO data. To my surprise i have not found a single state change in the MDC pin (no clock) and MDIO data itself is held at low all the time.I have seen the specs and found that the operating mode configuration pins brought outside the chip are left floating(the chip is not hardware configured) Doesn't the PHY require to be configured through MDIO interface before data transfer..? How can this be possible..? Is there any other way to configure the PHY other than fixed hardware and MDIO software configuration..? regards knightArticle: 136394
Hi all , I am a newbie of FPGA. So in the development chain I miss the following step: Suppose I have developed and tested my VHDL code, example an FFT. How can set a parameter (i.e FFT dimension) inside the VHDL code from the HOST PC? I need a driver. In which way this dirver have to be developed ? Thanks in advanceArticle: 136395
On Nov 14, 2:16=A0am, Paul Boven <p.bo...@xs4all.nl> wrote: > Hi Bish, > > bish wrote: > > Well now when we connected it with the target board the led keeps on > > glowing with amber color but no green color. And while trying to > > download bitstream, error occurs likecablenot detected. > > >ii) Further is there any way of checking whether the board is ok > > downloading any bitstream to the fpga. And can we use anything other > > than thisplatformcableusbto configure the fpga in Spartan 3a 1800a > > dsp board. > > There is a default configuration file on that board, which will run some > counting sequences on the green leds, drive the VGA with a rainbow > pattern, and you can even talk to the RS232 to do a full suite of tests. > Does the default configuration still exist and load/run? We had tested the board before our vacation and it had worked fine. We have configured the board with other examples too. So I don't think at present we have the default configuration file on the board. > Do all the 3 power-supply LEDS (next to the 3 small power converter PCB > modules) light? Yes all of them light. > > Btw., on my board only 2 of the three red LEDS light up because someone > forgot to place resistor R152 on my board. :-( > > I've experienced several difficulties when programming my 3A-1800-DSP > board as well (using a parallelcablefrom Digilent in my case). It > would work great at home, but at other locations, I couldn't programm it > - never really worked out why. Also, when loading a bitfile succeeds > only partially, make sure that you check the temperature of your FPGA - > mine got rather hot a couple of times after getting CRC errors on a > configuration. > We didn't get any difficulty earlier when we had used it for may be 3 - 4 times. But then now when we tried to use it the usb cable's indicator led does not glow green even when we connect the board and power it up. > Regards, Paul Boven. I cannot figure out how this can happen because if the platform usb cable had a problem it shouldn't have worked for first few times. The Vref pin in the cable from target board has required voltage (>1.5v, when it is powered on) and the PC has detected the cable, isn't these conditions sufficient for the cable to light the green led?Article: 136396
On 2008-11-14, Jan Bruns <testzugang_janbruns@arcor.de> wrote: > I've read somewhere about the MULTAND allowing to build an adder with > an additional enable input for one of the summands. I haven't looked into the MULTAND usage for multipliers much, but I have seen some other nice usage examples of it: It allows you to implement (a&b) + (c&d) using only one lut / bit. This can be good if you want to implement an adder with two possible inputs for each operand. (Assuming that you can arrange the unused input to be set to 1 using for example the set signal of the flip-flops in the previous pipeline stage.) I saw another neat use case on the fpga-cpu mailing list at http://www.embeddedrelated.com/groups/fpga-cpu/show/2801.php where Göran Bilski explains how the ALU in the microblaze works. By using MULTAND it is possible to get the following functionality using only one lut per bit: B+A, B-A, B and A Has anyone seen any other nice use case for MULTAND? /AndreasArticle: 136397
You also need to code the way the parameters are set in HDL, including the hardware interfaces Common choices to interface with a host PC are - JTAG - RS232 - Ethernet - USB - PCI Or there might even be no host PC. Maybe you are running Linux on a processor implemented in you FPGA and the user enters the parameters with EMACs. If you just want to test modules and have no whole system yet to implement in your FPGA you can use ChipScope that has an option to set Vitual IOs from a PC using Chipscope. Joysticks, Pushbuttons, PS2-Keyboards are very easy to interface to in hardware and can also be used to set parameters. Kolja Sulimma On 14 Nov., 10:12, "KingCharles" <as...@email.com> wrote: > Hi all , > > I am a newbie of FPGA. > So in the development chain I miss the following step: > > Suppose I have developed and tested my VHDL code, example an FFT. > > How can set a parameter (i.e FFT dimension) inside the VHDL code from the > HOST PC? > > I need a driver. In which way this dirver have to be developed ? > > Thanks in advanceArticle: 136398
On Nov 14, 2:14=A0am, axalay <axa...@gmail.com> wrote: > =A0I have this problem. Use ISE 9.2 SP4. This problem is solved in ISE > 10.1 SP1, but I whant solve this problem in 9.2. Help!!!! :) I'd suggest getting rid of at least one clock. KJArticle: 136399
Hallo. I don't remeber the purpose of the MULTAND (found in many xilinx fpgas), and I hate not understanding such simple things. I've read somewhere about the MULTAND allowing to build an adder with an additional enable input for one of the summands. But it seems to me this can still be done without the MULTAND using this setup: LUT(a,b,ben) := a xor (b and ben); CYMUX(sel,d1,d0) := (sel) ? d1 : d0; SUM(a,b,ben,cin) := LUT(a,b,ben) xor cin; COUT(a,b,ben,cin) := CYMUX(LUT(a,b,ben),cin,a); So the main purpose probably is to allow for an adder with enable bits for both summands, but I actually don't see how this would aid in building multipliers, except maybe for the outer, initial stage (am I missing something, or is this really the main purpose?). Gruss Jan Bruns
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