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Thanks for the comments. That was correct. Because it's a signed multiply in blocks of 18x18 it reduces the throughput of each input by one bit. I implemented a 35 x 35 multiplier and it only used 4 multipliers as I would expect. Thanks again, DaleArticle: 128626
On Jan 31, 4:46=A0pm, Kris Vorwerk <kris.vorw...@gmail.com> wrote:
> > I am working on Actel Fusion FPGA.
> > I am having problems with the ADC in my design.
>
> > Can someone please help me with this?
>
> More details please :)
>
> (I'm not overly-familiar with the ADC, but if you provide a few more
> details, either I or someone else may be able to help.)
>
> K.
Hey,
I am trying to configure the ADC for voltage monitoring part.
I have to use only three channels, So I am using AV0, AV1 and AV2.
I am using Flash running at 8MHz to initialize and 40MHz is the fast
clock after initialization which I am using as analog system clock.
In SMARTGEN in the analog system builder I am selecting "ADC Sample
and Sequence Control only".
And I am only outputting ADC Results from the analog system.
Te problem is that nothing comes out on the ADC Result.
In the post layout simulation, I see that Flash initialization is
done, but the ADC Channel and ADC Result is always zero along with
ASSC_Done, ASSC_Wait, ChLAT, ChSAT signals.
Out from the Analog system Block here is the code I use to read out
the ADC Results.
library ieee;
library fusion;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity strm_ebs is
port (
ebs_right,ebs_up,ebs_left,ebs_down : out std_logic;
rssi0,rssi1,rssi2,rssi3,rssi4,rfa0,rfa1,rfa2,rfa3,rfa4,
rfb0,rfb1,rfb2,rfb3,rfb4 : out std_logic_vector (11 downto
0);
adc_result : in std_logic_vector (11 downto 0);
adc_ch : in std_logic_vector (4 downto 0); --adc channel
adc_data_valid,clk_5k,reset : in std_logic
);
end strm_ebs;
architecture arch_strm_ebs of strm_ebs is
begin
---------Generating ebs signals -------------------
Process (clk_5k,reset)
variable ebs_sig : std_logic_vector (3 downto 0) :=3D "0000";
begin
if reset=3D'0' then
ebs_sig :=3D (others =3D> '0');
ebs_right <=3D '0';
ebs_up <=3D '0';
ebs_left <=3D '0';
ebs_down <=3D '0';
rssi0 <=3D (others =3D> '0');
rssi1 <=3D (others =3D> '0');
rssi2 <=3D (others =3D> '0');
rssi3 <=3D (others =3D> '0');
rssi4 <=3D (others =3D> '0');
rfa0 <=3D (others =3D> '0');
rfa1 <=3D (others =3D> '0');
rfa2 <=3D (others =3D> '0');
rfa3 <=3D (others =3D> '0');
rfa4 <=3D (others =3D> '0');
rfb0 <=3D (others =3D> '0');
rfb1 <=3D (others =3D> '0');
rfb2 <=3D (others =3D> '0');
rfb3 <=3D (others =3D> '0');
rfb4 <=3D (others =3D> '0');
elsif (clk_5k'event and clk_5k=3D'1') then
case ebs_sig is
when "0000" =3D>
ebs_sig :=3D "0001";
when "0001" =3D>
ebs_sig :=3D "0010";
when "0010" =3D>
ebs_sig :=3D "0100";
when "0100" =3D>
ebs_sig :=3D "1000";
when "1000" =3D>
ebs_sig :=3D "0000";
when others =3D>
null;
end case;
ebs_right <=3D ebs_sig(3);
ebs_up <=3D ebs_sig(2);
ebs_left <=3D ebs_sig(1);
ebs_down <=3D ebs_sig(0);
if (adc_data_valid =3D'1') then
case ebs_sig is
when "0000" =3D>
case adc_ch is
when "00001" =3D>
rfa0 <=3D adc_result;
when "00100" =3D>
rfb0 <=3D adc_result;
when "00111" =3D>
rssi0 <=3D adc_result;
when others =3D>
null;
end case;
when "0001" =3D>
case adc_ch is
when "00001" =3D>
rfa4 <=3D adc_result;
when "00100" =3D>
rfb4 <=3D adc_result;
when "00111" =3D>
rssi4 <=3D adc_result;
when others =3D>
end case;
when "0010" =3D>
case adc_ch is
when "00001" =3D>
rfa3 <=3D adc_result;
when "00100" =3D>
rfb3 <=3D adc_result;
when "00111" =3D>
rssi3 <=3D adc_result;
when others =3D>
end case;
when "0100" =3D>
case adc_ch is
when "00001" =3D>
rfa2 <=3D adc_result;
when "00100" =3D>
rfb2 <=3D adc_result;
when "00111" =3D>
rssi2 <=3D adc_result;
when others =3D>
end case;
when "1000" =3D>
case adc_ch is
when "00001" =3D>
rfa1 <=3D adc_result;
when "00100" =3D>
rfb1 <=3D adc_result;
when "00111" =3D>
rssi1 <=3D adc_result;
when others =3D>
end case;
when others =3D>
null;
end case; --end ebs signal cases
end if; --if (adc_data_valid)
end if; --if (reset)
end process;
----------------------------------------------------
----------------------------------------------------
end arch_strm_ebs;
Thanks,
Cheers!
Article: 128627OK, I upped the 3.1.4 source tarball to sourceforge, so unix people can have at it right away. http://sourceforge.net/project/showfiles.php?group_id=183606 Note that for windows there might be issues with crash reload in win32 as mk has indicated to me. This is being looked into. For those who hate the new user interface, you can revert to the old one by adding the following to your .gtkwaverc file: use_standard_clicking off use_toolbutton_interface off -TonyArticle: 128628
Hi everybody, It's been a while I'm struggling with ML310 board to have my design loaded from compact flash to the Virtex II-pro FPGA on the board. I'm generating system.ace file using iMPACT and program the compact flash using a card reader. In my design I have a Microblaze with an OPB timer, OPB SysAce controller and OPB uart-lite, I have some more controllers connected to OPB which I think should not matter in the flow of my design. In my software application I set the timer, write something to the STD-OUT which is RS232 and after executing some code I read the value of the timer again to know how many cycles it took for that piece of code. Anyway my problem is when I load the design to the compact flash, when I power on the device (or when I reset system_ace) sysAce Status LED on the board blinks several times and then all the LEDs including SysAce Status LED go green which to me means that it loaded the design to the FPGA. However the problem is the system seemingly goes to freeze mode. It doesn't write anything to hyperterminal so that I could know if it is working or not. As well no matter how much I keep SysAce button pressed it doesn't reset the sysace any more. As well I can't get connected to the board for debug using XMD through Parallel IV cable. So in fact I can't do anything except to shut down the board. I have no clue what the problem can be. I also tried using the bitstream already on the Xilinx ML310 Compact Flash card. I put my design in to folder cf7 but the same things happen when I want to load that design. Do you have any clue what the problem can be? I'd appreciate it if you could point me to the solution or can introduce a tutorial or article which in fact shows how exactly configuring through flash can be done. I already went through several articles but still haven't been able to get it work. I'd appreciate your comments and help beforehand, AmirArticle: 128629
In Xilinx application notes XAPP457 ( http://www.xilinx.com/support/documentation/application_notes/xapp457.pdf), the resistors used to adjust output voltage is only 22.6 and 38.3, shown in Figure 1 in the pdf file. According to LT1763 data sheet( http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1010,C1764,P1778,D3903), shown in Figure 2. Adjustable Operation, the R1 should not greater than 250K. My question is why in Xilinx application notes XAPP457 using such a small resistors? Is it better to use 22.6K and 38.3K resistors when the power consumed by resistors and the current bypass are much small?Article: 128630
jasonL wrote: > In Xilinx application notes XAPP457 ( > http://www.xilinx.com/support/documentation/application_notes/xapp457.pdf), > the resistors used to adjust output voltage is only 22.6 and 38.3, > shown in Figure 1 in the pdf file. > > According to LT1763 data sheet( > http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1010,C1764,P1778,D3903), > shown in Figure 2. Adjustable Operation, the R1 should not greater > than 250K. > > My question is why in Xilinx application notes XAPP457 using such a > small resistors? Is it better to use 22.6K and 38.3K resistors when > the power consumed by resistors and the current bypass are much small? How much current passes thru 22.6K ? How much current passes thru 250K ? What is the ADJ pin current ? Now, why does that difference bother you ? One other reason to lower the dividers, is to make the node less susceptable to noise pickup. If someone touches that PCB node, whilst it is on, do you want the FPGA to pop its lid ? -jgArticle: 128631
On 31 Jan., 13:56, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hello All, > > I am curious what are main applications of FPGA in > Telecommunications? Doing tasks. Sorry but its impossible to give better answers. I'm doing telecomunications and expect to have less in common with designs for othere companies. In fact I have several designs for one department that have nothing in common with designs for other departments in a rather small company. Imagine the widespread in companies covering a wide range of TC. Someone doing optical to electrical interface has complete different tasks like someone doing paket routing and both is complete different from a answering machine. bye ThomasArticle: 128632
"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:604fh2F1p55sjU1@mid.individual.net...
> I would get eval versions of both vendors to see
> how each worked on my machine with my code,
> and which vendor was easier to deal with on licensing.
Well, as an update to my rushed mini-review, here's what I've found so far:
a) The web-eval of Active-HDL 7.3 appears to run the "EE" product
configuration,
which is the most advanced edition of Active-HDL. Capacity is limited to
5MB
or less, and sim-runtime is limited to 10us.
b) Modelsim/PE's Systemverilog (Design) support is more robust than
ActiveHDL's.
Just about everything I tried worked properly. Active-HDL 7.3 has a
bunch
of rough-edges. String types don't work properly with some standard
system-tasks
($swrite, $sformat) -- there is no package/endpackage support (maybe
that's in
the full/commercial version?) And minor quirks in the Systemverilog
preprocessor
(string-concatenation doesn't trim whitespace:
`define( myword ) `" blah myword blah `"
c) SVA (Systemverilog Assertion) constructs compiled and simulated
successfully.
Modelsim/PE doesn't do SVA at all. Active/HDL is the least expensive
solution for
designers wanting to use SVA in design. ('least expensive' does not
mean cheap:
Active/HDL-EE's SVA-option costs extra, and EE's base-price is 2X the
price
of Modelsim/PE!)
d) I tried a Xilinx Smartmodel based simulation (TEMAC from Coregen
9.2i.04), and
with help from this usenet group, finally built the PLI and testbench
properly.
Unfortunately, I can't determine if its working properly, because the
simulator
terminates at 10us, long before that sim-testbench has a chance to
finish.)
e) I didn't like the terseness of the assertion-$error/$warning/$info
reports in the
logfile. Unlike Modelsim, ActiveHDL does not stamp each message with
filename/line#
info. On the other hand, Aldec's GUI-console window is 'hyperlinked' --
doubleclicking on virtually any message (user or simulator generated)
jumps the
RTL-browser to the triggering statement, brilliant!
f) I couldn't check performance -- I didn't have a useful testcase which
could
finish in under 10us of simtime. And I don't have access to Modelsim/PE
anymore.
g) ActiveHDL claims support for *some* Systemverilog testbench features --
but 'class/endclass' support isn't sufficient to do a heavy-duty TLM
testbench.
To be fair, Mentor restricts class/endclass (and assertions, coverage,
etc.)
to Modelsim/SE Questasim.
Overall, despite Modelsim/PE's advantages (more mature Systemverilog-Design
support, and Xilinx/Altera's official blessing for FPGA-device sims), I'm
leaning toward Active/HDL. The user-interface is much nicer (for me),
and the existing Systemverilog support is quite usable for a small/FPGA
project.
Article: 128633Hi Urban, If you want to connect the fsl module to MicroBlaze, then one port is usually enough since MicroBlaze can only write or read to one port at a time. You can't get more bandwidth by adding more ports. Göran <u_stadler@yahoo.de> wrote in message news:fc9851b7-5b44-4631-a108-5f3e1bbb369c@d21g2000prf.googlegroups.com... > hi > > i'm just working on a project where i need to create an fsl interface > for my custom ip core. i used the "create and import" peripheral > wizard from the edk. > the wizard gives me the following options to choose from : "number of > input/output 32 bit words" and two pages later "number of input > arguments". whats the difference between those two things? when i > look into the driver and vhdl code i still get 1 32 bit bus. the only > thing is that depending on the values i choose the driver template for > example creates one variable "input_0" (which in case of 8 32 bit > input words and 1 input argument" is an array of 8. > is there any speed advantage of creating a large array or is it better > to create more input arguments. when i look at the selftest source > code the macro is called for every entry of the array anyway..... > or did i misunderstand something here? > > > thanks > urbanArticle: 128634
> why for a dual port to SDRAM controller? i suppose it´s faster. Here is a Xilinx example. Your system contains : - CPU (microblaze) - a DMA controller, - the sdram controller - a peripheral, and you'd like to copy data from this peripheral to SDRAM using DMA. Case 1: You use opb_sdram, and everything is connected to the OPB bus. This bus can only have one transaction going on at the same time, of course. Say the CPU executes an instruction at address 0x1000. It makes a read request to the sdram controller to get the instruction. Until this request is finished, and the CPU gets the instruction it wanted, OPB bus can not be used for other things. Since SDRAM has latency, this means you lose cycles on the OPB bus. If, for instance, the DMA controller needs to transfer data from the peripheral to SDRAM, it will have to wait. Case 2: Yo use mch_opb_sdram. Everything is still connected to the opb bus, but the CPU has a cache and will use XCL to talk to the SDRAM controller. Therefore the CPU talks directly to the SDRAM controller when it needs to read/write SDRAM, and only uses OPB when it needs to talk to the peripheral or the DMA controller. Say the CPU executes an instruction at address 0x1000. It makes a read request to the sdram controller (via XCL) to get the instruction. The SDRAM controller makes a burst and transfers address 0x1000-0x100F to the CPU cache (even though the CPU didn't ask, once you talk to a SDRAM you might as well do a burst, it doesn't take much extra time). Therefore while the CPU executes the next 4 instructions it takes them from the cache and the OPB bus is free. If the CPU wants to talk to a peripheral or BRAM via OPB bus this does not conflict with instruction fetching. Also, the OPB bus was not used until now, so the DMA controller can talk to the peripheral without waiting, read a burst of data, and talk to the sdram controller via opb bus to write this data. Of course the SDRAM controller can only make one SDRAM transaction at the same time, but you save on transaction setup time. Since the SDRAM controller "sees" two incoming transactions (read instructions / DMA write to memory) it will be ready to switch from one to the other, so you save on arbitration time. So yeah, multichannel is faster, because OPB bus is not clogged by memory accesses from the CPU and can be used for faster peripheral access or DMA.Article: 128635
"jasonL" <junsong.liao@gmail.com> wrote in message news:17c5da4a-f6d9-4891-be9c-c7b8152e3fbd@s37g2000prg.googlegroups.com... > > My question is why in Xilinx application notes XAPP457 using such a > small resistors? Is it better to use 22.6K and 38.3K resistors when > the power consumed by resistors and the current bypass are much small? Hi Jason, It's because the app. note probably has a mistake. The values given will work, I guess, as they are less than 250k, but I would use 22.6k and 38.3k. You should email Eric, the XAPP author, and see what he says. You can find his email address in the C.A.F archive somewhere. Cheers, Syms.Article: 128636
On Jan 31, 9:24 pm, johnp <johnp3+nos...@probo.com> wrote:
> On Jan 31, 6:24 am, jo...@mit.edu wrote:
>
> > Has anyone managed to get the xilinx BSCAN primitives (for interfacing
> > with the USERx jtag registers/comands) working robustly? I've found a
> > depressing lack of information as to what the actual pins do -- aside
> > from a (now unavailable?) techXclusive article, "Reconfiguring Block
> > RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't
> > find much more info.
>
> > What's the best way to interface with this part? In particular, how do
> > you deal with the obvious synchronization/metastability issues when
> > crossing clock domains, esp. if you're hoping for a device that's
> > still small (i.e. no hardware async fifos or anything).
>
> > Thanks for any advice you can provide,
> > ...Eric
>
> I used it recently for the 1st time to check out a JTAG interface
> block I
> was developing. Here's the very simple code I used:
> //
> ----------------------------------------------------------------------
> // Xilinx BSCAN
> // This is temporary code that allows us to test out JTAG master block
> by
> // using the Xilinx JTAG block
> reg [31:0] bscan_data;
>
> BSCAN_SPARTAN3 u_bscan (
> .CAPTURE (BSCAN_CAPTURE),
> .DRCK1 (BSCAN_DRCK1),
> .DRCK2 (),
> .RESET (BSCAN_RESET),
> .SEL1 (BSCAN_SEL1),
> .SEL2 (),
> .SHIFT (BSCAN_SHIFT),
> .TDI (BSCAN_TDI),
> .UPDATE (BSCAN_UPDATE),
> .TDO1 (bscan_data[0]),
> .TDO2 (1'b0)
> );
>
> always @(posedge BSCAN_DRCK1 or posedge BSCAN_RESET)
> if (BSCAN_RESET)
> bscan_data <= 32'h87654321;
> else if (BSCAN_SHIFT)
> bscan_data <= {BSCAN_TDI, bscan_data[31:1]};
>
> The code provides access to a simple shift register. This would be
> simple
> to extend to a much more functional block, but as you point out,
> you'll
> need to take care of clock domain crossing, etc.
>
> John Providenza
Eric,
Have you seen Gnat tool ?
It is a powerful tool for communicating with FPGA through JTAG,
consisting of a VHDL core and TCL scripts to establish the
communication.
Hope this helps,
/MH
Article: 128637Hi, Does anyone run the Gemac on a Xilinx ML402 board ? I try to use the example design that comes with the core but it didn't work yet. For example, this example design doesn't have the phy_reset output pin which is necessary to make 88E1111 PHY work. Keeping phy_reset high the link and speed light stay on, anything I download to the board that doesn't set phy_reset high make the link down. Any hint in how make Gemac on ML402 are very welcome. Regards, Josue. -- UFSM - BR - Master StudentArticle: 128638
Sometimes low values are good to provide a minimum output load but these are so low that they would need to be probablly 1206 sized resistors, or bigger, to take the power dissapated. Higher values also react more with parasitic capacitance to form a filter that might slow down response of the regulator and sometimes this is a reason to use lower values. John Adair Enterpoint Ltd. On 1 Feb, 02:07, jasonL <junsong.l...@gmail.com> wrote: > In Xilinx application notes XAPP457 (http://www.xilinx.com/support/documen= tation/application_notes/xapp457...), > the resistors used to adjust output voltage is only 22.6 and 38.3, > shown in Figure 1 in the pdf file. > > According to LT1763 data sheet(http://www.linear.com/pc/downloadDocument.d= o?navId=3DH0,C1,C1010,C1764,...), > shown in Figure 2. Adjustable Operation, the R1 should not greater > than =A0250K. > > My question is why in Xilinx application notes XAPP457 using such a > small resistors? Is it better to use 22.6K and 38.3K resistors when > the power consumed by resistors and the current bypass =A0are much small?Article: 128639
Symon wrote: > "jasonL" <junsong.liao@gmail.com> wrote in message > news:17c5da4a-f6d9-4891-be9c-c7b8152e3fbd@s37g2000prg.googlegroups.com... >> My question is why in Xilinx application notes XAPP457 using such a >> small resistors? Is it better to use 22.6K and 38.3K resistors when >> the power consumed by resistors and the current bypass are much small? > > Hi Jason, > It's because the app. note probably has a mistake. The values given will > work, I guess, as they are less than 250k, but I would use 22.6k and 38.3k. > You should email Eric, the XAPP author, and see what he says. You can find > his email address in the C.A.F archive somewhere. > Cheers, Syms. > > From the appnote: "Careful inspection of the original design reveals that the impedance of the feedback network is atypically low. Even with zero load, approximately 50 mA is lost through the feedback network. At first, this loss seems undesirable, but it serves an important purpose." << Full explanation follows >> -- BasArticle: 128640
hi
well i understand that microblaze can only write to one port at a
time.
but my question was more about those two parameters:
"number of input/output 32 bit words" and "number of input arguments"
what i see in the driver template is that it writes every word at a
time
anyway. so i was wondering if there advantage is any advantage of
having more than on 32 bit word or more that one argument.
(well of coures if i want to write more than 1 32 bit word i have to
call the driver function more often but that i what the driver does
anyway)
for example the driver function (marco) looks like that for 1 32 bit
word and argument
for (i=3D0; i<1; i++)\
{\
write_into_fsl(input_0[i], input_slot_id);\
}\
adding more 32 bit words just increases the number of runs in the for
loop.
so any advantage of having more than 1 here?
thanks
urban
On 1 Feb., 08:35, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote:
> Hi Urban,
>
> If you want to connect the fsl module to MicroBlaze, then one port is
> usually enough since MicroBlaze can only write or read to one port at a
> time.
> You can't get more bandwidth by adding more ports.
>
> G=F6ran
>
> <u_stad...@yahoo.de> wrote in message
>
> news:fc9851b7-5b44-4631-a108-5f3e1bbb369c@d21g2000prf.googlegroups.com...
>
> > hi
>
> > i'm just working on a project where i need to create an fsl interface
> > for my custom ip core. i used the "create and import" peripheral
> > wizard from the edk.
> > the wizard gives me the following options to choose from : "number of
> > input/output 32 bit words" and two pages later "number of input
> > arguments". whats the difference between those two things? when i
> > look into the driver and vhdl code i still get 1 32 bit bus. the only
> > thing is that depending on the values i choose the driver template for
> > example creates one variable "input_0" (which in case of 8 32 bit
> > input words and 1 input argument" is an array of 8.
> > is there any speed advantage of creating a large array or is it better
> > to create more input arguments. when i look at the selftest source
> > code the macro is called for every entry of the array anyway.....
> > or did i misunderstand something here?
>
> > thanks
> > urban
Article: 128641"Bas Laarhoven" <sjml@xs4all.nl> wrote in message news:47a3102e$0$85786$e4fe514c@news.xs4all.nl... > > From the appnote: > > "Careful inspection of the original design reveals that the impedance of > the feedback network is atypically low. Even with zero load, approximately > 50 mA is lost through the feedback network. > At first, this loss seems undesirable, but it serves an important > purpose." << Full explanation follows >> > > -- Bas So now we know! I knew Eric wouldf have his reasons. Ta, Syms.Article: 128642
Hi,
All the code produce for the peripheral (both VHDL and C) will most likely
need modification for your specific needs.
The wizard just create example files (still functional) but you have to
change them to something more meaningful
The VHDL code just add together all input words and then send back the
result.
The "number of input/output 32 bit words" determines how many words the core
needs in order to produce the result and how many words the result consists
of
This will be used by the VHDL code that the wizard generates.
i.e. If you say 8 inputs words and 1 output words, the VHDL code will read 8
words on the FSL and then send back one word to the FSL.
The actual connection to MicroBlaze will always be one Master FSL port and
one Slave FSL port independent on the number of input/out words.
The "number of input arguments" determines how the driver for your core will
handle the data.
If you have 8 input words and 1 input argument, the driver code will assume
all 8 words to be in the one 8-word sized array.
You could change it to 8 input arguments and then the driver code would
assume 8 arguments each being 1-word sized array.
So how you set this depends on the function and how you stored the data in
your C code.
It might be more advantage to have fewer input/output arguments since you
can loop over the array index instead of reading from different arrays.
It should produce less code.
Göran
The difference between "number of input/output 32 bit words" and "number of
input arguments" is for
<u_stadler@yahoo.de> wrote in message
news:f735940e-3ea1-4018-96da-4d347acdc925@k39g2000hsf.googlegroups.com...
hi
well i understand that microblaze can only write to one port at a
time.
but my question was more about those two parameters:
"number of input/output 32 bit words" and "number of input arguments"
what i see in the driver template is that it writes every word at a
time
anyway. so i was wondering if there advantage is any advantage of
having more than on 32 bit word or more that one argument.
(well of coures if i want to write more than 1 32 bit word i have to
call the driver function more often but that i what the driver does
anyway)
for example the driver function (marco) looks like that for 1 32 bit
word and argument
for (i=0; i<1; i++)\
{\
write_into_fsl(input_0[i], input_slot_id);\
}\
adding more 32 bit words just increases the number of runs in the for
loop.
so any advantage of having more than 1 here?
thanks
urban
On 1 Feb., 08:35, "Göran Bilski" <goran.bil...@xilinx.com> wrote:
> Hi Urban,
>
> If you want to connect the fsl module to MicroBlaze, then one port is
> usually enough since MicroBlaze can only write or read to one port at a
> time.
> You can't get more bandwidth by adding more ports.
>
> Göran
>
> <u_stad...@yahoo.de> wrote in message
>
> news:fc9851b7-5b44-4631-a108-5f3e1bbb369c@d21g2000prf.googlegroups.com...
>
> > hi
>
> > i'm just working on a project where i need to create an fsl interface
> > for my custom ip core. i used the "create and import" peripheral
> > wizard from the edk.
> > the wizard gives me the following options to choose from : "number of
> > input/output 32 bit words" and two pages later "number of input
> > arguments". whats the difference between those two things? when i
> > look into the driver and vhdl code i still get 1 32 bit bus. the only
> > thing is that depending on the values i choose the driver template for
> > example creates one variable "input_0" (which in case of 8 32 bit
> > input words and 1 input argument" is an array of 8.
> > is there any speed advantage of creating a large array or is it better
> > to create more input arguments. when i look at the selftest source
> > code the macro is called for every entry of the array anyway.....
> > or did i misunderstand something here?
>
> > thanks
> > urban
Article: 128643On 31 Jan., 22:29, Dale <dale.prat...@gmail.com> wrote: > Thanks for the comments. That was correct. Because it's a signed > multiply in blocks of 18x18 it reduces the throughput of each input by > one bit. I implemented a 35 x 35 multiplier and it only used 4 > multipliers as I would expect. > > Thanks again, > Dale You only need two adders to extend a 35x35 to 36x36. Maybe you cann use the final adders in the DSP slice for that. Kolja SulimmaArticle: 128644
talkb wrote:
> Overall, despite Modelsim/PE's advantages (more mature Systemverilog-Design
> support, and Xilinx/Altera's official blessing for FPGA-device sims), I'm
> leaning toward Active/HDL. The user-interface is much nicer (for me),
> and the existing Systemverilog support is quite usable for a small/FPGA
> project.
Thanks for the report.
-- Mike Treseler
Article: 128645Hello, Somebody can explain me what is the "Tdcmino" signal in a DCM ? The "Tdcmino" delay is very high (more than 5 ns) and I don't what is it ! please Help. Laurent. have fun.Article: 128646
On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote: > > Eric, > Have you seen Gnat tool ? > It is a powerful tool for communicating with FPGA through JTAG, > consisting of a VHDL core and TCL scripts to establish the > communication. > > Hope this helps, > /MH Gnat looks like a very useful suite of tools. Unfortunately, the article (http://www.xilinx.com/publications/xcellonline/xcell_53/ xc_jtag53.htm) was written in 2005, and the URLs to the actual applications & libraries are all dead (the company that was hosting them has deleted them - searching the website turns up nothing). Nice idea though. Anyone know if the project has been moved somewhere else? EBArticle: 128647
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/dev/dev0121_17.html Explains it, in part. and, http://www.xilinx.com/support/documentation/white_papers/wp257.pdf AustinArticle: 128648
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:5f7af460-4a3c-4ac2-972c-6d6c9d6b4585@s8g2000prg.googlegroups.com... > Hello, > > Somebody can explain me what is the "Tdcmino" signal in a DCM ? > The "Tdcmino" delay is very high (more than 5 ns) and I don't what is > it ! > > please Help. > Laurent. > > have fun. STFW. http://www.google.com/search?q=TdcminoArticle: 128649
On Fri, 1 Feb 2008 09:13:38 -0800 (PST), emeb <ebrombaugh@gmail.com> wrote: >On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote: >> >> Eric, >> Have you seen Gnat tool ? >> It is a powerful tool for communicating with FPGA through JTAG, >> consisting of a VHDL core and TCL scripts to establish the >> communication. >> >> Hope this helps, >> /MH > >Gnat looks like a very useful suite of tools. Unfortunately, the >article (http://www.xilinx.com/publications/xcellonline/xcell_53/ >xc_jtag53.htm) was written in 2005, and the URLs to the actual >applications & libraries are all dead (the company that was hosting >them has deleted them - searching the website turns up nothing). > >Nice idea though. Anyone know if the project has been moved somewhere >else? > >EB There seems to be a copy here: http://www.xess.com/appnotes/gnat_xsa_3s1000.html
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