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On 11 Feb., 14:52, michel.ta...@gmail.com wrote: > Hi all, > > I've a problem.. :) > I have to divide a 48MHz clock to obtain a clock with differents > frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. > First I used flips flops to make a frequency divider, I obtained the > good frequencies, but I had skew between my master clock (48MHz) and > my divided clock. > So, I tried to use a DCM to divide frequency and to deskew divided > clock using the CLKFB input. But, the problem is the lower limit of > the DCM output frequency (1MHz) .. > > So, if anyone have an idea ? > > Thanks by advance, > > Best regards, Michel. try using higher clock and clock-enable "tick pulses" then you have now scew :) Antti Lukats My First Flash FPGA: http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdfArticle: 128951
Hello all, I'm evaluating ModelSim versus Active-HDL to determine which one is better in today's marketplace (for VHDL). I found some older threads that seemed to lean towards Active-HDL so I wanted to see if that was still the case. I currently use ModelSim Xilinx Edition but my designs often-times hit XE's limits and get throttled. Also, does know off-hand the approximate price of the different versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key features that make the more expensive ones worth the cost? Thanks, JohnArticle: 128952
On Mon, 11 Feb 2008 05:48:16 -0800 (PST), LilacSkin <lpaulo07@iseb.fr> wrote: >so, I return to my first message, that is correct : No, it's not; you're being unacceptably careless. >if ( unsigned_data = "00000000" ) then This test will never be true, because unsigned_data is 10 bits wide and can never be equal to an 8-bit vector. > signed_data <= "10000001"; >else > signed_data <= (not unsigned_data(9)) & > unsigned_data(8 downto 0); And now you're trying to copy a 10-bit expression into an 8-bit result. But yes, you're on the right track. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 128953
On Feb 11, 11:29 am, paragon.j...@gmail.com wrote: > Hello all, > > I'm evaluating ModelSim versus Active-HDL to determine which one is > better in today's marketplace (for VHDL). I found some older threads > that seemed to lean towards Active-HDL so I wanted to see if that was > still the case. > > I currently use ModelSim Xilinx Edition but my designs often-times hit > XE's limits and get throttled. > > Also, does know off-hand the approximate price of the different > versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key > features that make the more expensive ones worth the cost? > > Thanks, > John I use ActiveHDL , It was the first program I learned to use and I am not changing it for nothing , though I tried ModelSim. AlfredoArticle: 128954
Hi,
disabling optimisations still do not work. the hardware peripherals
attached to microblaze is only
1) UART
2) a simple timer
so the issue does not seem to be about optimisations. Also realised
that, it only works in debug mode with the breakpoint set just before
the algorithm commences. If the breakpoint is set in the middle of the
function start_algo(), the same thing happens; no data is sent back to
UART.
Can it be an issue of hardware catching up? the UART data is read
via blocking statements!!
In any case, the UART is the free opb_uartlite provided by xilinx,
which i hacked to allow hardware handshaking. I did this, so that I
could use the default drivers for opb_uartlite with the same UART with
additional functionality of hardware handshaking. No further register
manipulation in software is necessary in this case to do hardware
handshaking like for the case of the UART16550.
This is what I did to enable hardware handshaking without any
additional software needed.
1) rts on PC side will drive FPGA cts pin. If rts on PC side = 1, then
transmission from FPGA to PC will be possible. otherwise, the FPGA
cannot transmit anything back to PC.
2) cts on PC side is driven by FPGA rts pin. FPGA rts pin = 1 once the
receiver buffer in UART peripheral attached to microblaze is full.
this will disable PC from sending any more data to microblaze on the
FPGA.
this method of UART handshaking seems to be working all this while on
the previous FPGA board with PC. I have also tested and ensured that
it works fine with this current board and PC (using both telnet and
simple matlab routines, as described in my original post).
Any other ideas? Something that i might have failed overlooked? thank
you all in advance.
Chris
GMM50 wrote:
> On Feb 10, 5:20 pm, chrisde...@gmail.com wrote:
> > Hi,
> > I am currently working on a microblaze v6.00 core on FPGA and am
> > developing an algorithm. This is what I am doing
> >
> > 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232
> > hardware handshaking is deployed here.
> > 2) the algorithm runs on microblaze to process the input data
> > 3) microblaze sends the data back to matlab on PC.
> >
> > the setup I am working on works perfectly on a previous FPGA board.
> > I have just migrated the setup to another FPGA board for FPGA resource
> > expansion reasons. However, microblaze no longer sends the data back
> > to PC. Here are some other details
> >
> > 1) I have ensured that the board is able to send data back and forth
> > from PC to microblaze via UART in both directions in matlab. thus code
> > like this works:
> > int main() {
> > get_params(); //get data from UART using blocking statements
> > return_result(); //return results back to PC via UART.
> >
> > }
> >
> > 2) the C code which doesnt work however looks like this in normal
> > operation unless I am in debug mode. :(
> >
> > int main(){
> > get_params(); //get data from UART using blocking statements
> > start_algo(); //to start algo
> > return_result(); //return results back to PC via UART.
> >
> > }
> >
> > void start_algo(){
> > // I inserted a breakpoint around here.
> > ...the rest of the algo....
> >
> > }
> >
> > when I use a debugger to debug, by inserting a breakpoint somewhere up
> > in the start_algo() function. Whenever I do that, the return_result()
> > function works just fine and returns the expected data correctly.
> >
> > However, normal operation (without use of a debugger) just fails to
> > work. I have been working on this for quite a while and am clueless
> > how else further to debug.
> >
> > any suggestions would really help.
> >
> > thanks in advance!
> > Chris
>
> Well I would first look at compiler optimizations. Some time debug
> operation has NO optimizations while 'release' has some.
> Look at the code produces with and with out. If it's not IDENTICAL
> then that a good place to look.
>
> Then break points might give hardware a chance to ketch up. Try debug
> with no breakpoints. That should also yield clues.
>
> Switch to Altera and NIOS. (Just kiddine).
>
> keep us posted.
>
> george
Article: 128955On Feb 11, 3:06 am, "Symon" <symon_bre...@hotmail.com> wrote: > Saw this on Slashdot.http://csg.csail.mit.edu.nyud.net/oshd/index.html > > Quote:- > > Projects > > H.264: HD quality H.264 baseline profile decoder. > > OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to > cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for > 802.15 (WUSB) is currently being worked on. > > 802.11a: 802.11a WiFi transmitter And it might even be useful, if you've got a copy of Bluespec System Verilog to compile it with. EBArticle: 128956
Can anyone assist is supplying 50 pieces of a Xilinx XC5VLX85-2FFG1153C? I also need 100 pieces of a EP2S130F1508C3N? I can not wait the factory lead time. Please call Jon E. Hansen (949)864-7745 directArticle: 128957
michel.talon@gmail.com wrote:
> I have to divide a 48MHz clock to obtain a clock with different
> frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz.
Here's a related vhdl example using clock enables:
A counts every clock,
B counts when A rolls,
C counts when B rolls
http://home.comcast.net/~mike_treseler/count_enable.vhd
-- Mike Treseler
Article: 128958Is it possible to install the last version of the free ISE on XP home edition?let me know,please Thanks to you all DiegoArticle: 128959
paragon.john@gmail.com wrote: > Hello all, > > I'm evaluating ModelSim versus Active-HDL to determine which one is > better in today's marketplace (for VHDL). I found some older threads > that seemed to lean towards Active-HDL so I wanted to see if that was > still the case. > > I currently use ModelSim Xilinx Edition but my designs often-times hit > XE's limits and get throttled. > > Also, does know off-hand the approximate price of the different > versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key > features that make the more expensive ones worth the cost? There is a big difference between Modelsim PE and SE, including a price difference of something like $12K (the last time I looked, which was awhile ago). Also, another thing to consider is Aldec Riviera, rather than ActiveHDL. This is just a high performance simulator, without all the whole "design environment" that ActiveHDL includes. Also, while you only mention VHDL, keep in mind that you are likely to want to be able to do mixed language simulations. For example, a lot of good memory models seem to only come in Verilog.Article: 128960
Hi lets assume I have two signals, each carrying 8 bits of information. One signal is a so called configuration signal and has exactly 4 bits that are HIGH and 4 bits that are LOW. Now depending on on the values of the configuration signal I wanna reorder the bits in the other signal in the following way: If a bit is set in the configuration signal, then the corresponding bit in the source register will be part of the most significant 4 bits of the result signal. If a bit in the configuration signal is not set then the corresponding bit in the source register will be part of the least significant 4 bits. Difficult to describe, so here an example Source: A B C D E F G H Configuration: 1 0 1 0 1 0 1 0 Result = ACEG BDFH So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 LSB bits. Is there maybe a better approach to do implement this on an FPGA?Article: 128961
On Feb 11, 8:55 am, chrisde...@gmail.com wrote:
> Hi,
> disabling optimisations still do not work. the hardware peripherals
> attached to microblaze is only
> 1) UART
> 2) a simple timer
>
> so the issue does not seem to be about optimisations. Also realised
> that, it only works in debug mode with the breakpoint set just before
> the algorithm commences. If the breakpoint is set in the middle of the
> function start_algo(), the same thing happens; no data is sent back to
> UART.
>
> Can it be an issue of hardware catching up? the UART data is read
> via blocking statements!!
>
> In any case, the UART is the free opb_uartlite provided by xilinx,
> which i hacked to allow hardware handshaking. I did this, so that I
> could use the default drivers for opb_uartlite with the same UART with
> additional functionality of hardware handshaking. No further register
> manipulation in software is necessary in this case to do hardware
> handshaking like for the case of the UART16550.
> This is what I did to enable hardware handshaking without any
> additional software needed.
>
> 1) rts on PC side will drive FPGA cts pin. If rts on PC side = 1, then
> transmission from FPGA to PC will be possible. otherwise, the FPGA
> cannot transmit anything back to PC.
> 2) cts on PC side is driven by FPGA rts pin. FPGA rts pin = 1 once the
> receiver buffer in UART peripheral attached to microblaze is full.
> this will disable PC from sending any more data to microblaze on the
> FPGA.
>
> this method of UART handshaking seems to be working all this while on
> the previous FPGA board with PC. I have also tested and ensured that
> it works fine with this current board and PC (using both telnet and
> simple matlab routines, as described in my original post).
>
> Any other ideas? Something that i might have failed overlooked? thank
> you all in advance.
>
> Chris
>
> GMM50 wrote:
> > On Feb 10, 5:20 pm, chrisde...@gmail.com wrote:
> > > Hi,
> > > I am currently working on a microblaze v6.00 core on FPGA and am
> > > developing an algorithm. This is what I am doing
>
> > > 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232
> > > hardware handshaking is deployed here.
> > > 2) the algorithm runs on microblaze to process the input data
> > > 3) microblaze sends the data back to matlab on PC.
>
> > > the setup I am working on works perfectly on a previous FPGA board.
> > > I have just migrated the setup to another FPGA board for FPGA resource
> > > expansion reasons. However, microblaze no longer sends the data back
> > > to PC. Here are some other details
>
> > > 1) I have ensured that the board is able to send data back and forth
> > > from PC to microblaze via UART in both directions in matlab. thus code
> > > like this works:
> > > int main() {
> > > get_params(); //get data from UART using blocking statements
> > > return_result(); //return results back to PC via UART.
>
> > > }
>
> > > 2) the C code which doesnt work however looks like this in normal
> > > operation unless I am in debug mode. :(
>
> > > int main(){
> > > get_params(); //get data from UART using blocking statements
> > > start_algo(); //to start algo
> > > return_result(); //return results back to PC via UART.
>
> > > }
>
> > > void start_algo(){
> > > // I inserted a breakpoint around here.
> > > ...the rest of the algo....
>
> > > }
>
> > > when I use a debugger to debug, by inserting a breakpoint somewhere up
> > > in the start_algo() function. Whenever I do that, the return_result()
> > > function works just fine and returns the expected data correctly.
>
> > > However, normal operation (without use of a debugger) just fails to
> > > work. I have been working on this for quite a while and am clueless
> > > how else further to debug.
>
> > > any suggestions would really help.
>
> > > thanks in advance!
> > > Chris
>
> > Well I would first look at compiler optimizations. Some time debug
> > operation has NO optimizations while 'release' has some.
> > Look at the code produces with and with out. If it's not IDENTICAL
> > then that a good place to look.
>
> > Then break points might give hardware a chance to ketch up. Try debug
> > with no breakpoints. That should also yield clues.
>
> > Switch to Altera and NIOS. (Just kiddine).
>
> > keep us posted.
>
> > george
I would try to slow the UART down and run with out interrupts and with
out handshaking. There's not much else to get in the way.
You didn't mention a timer interrupt. If there are any other
interrupts enabled I would try to run without them. The thought is
debug is protecting you n some way from something missing in an
interrupt routine.
keep us posted
george
Article: 128962On Feb 11, 10:12=A0am, "blisca" <bliscachiocciolinatiscalipuntoit> wrote: > Is it possible to install the last version of the free ISE on XP home > edition?let me know,please > > Thanks to you all > > Diego I can see why the website list for supported platforms would give you pause. I have XP Home at home and recall installing ISE Webpack without worry though I've only stressed the product at work with XP Pro. Is the issue that you're looking at purchasing a full ISE copy or a new computer? If you have XP Home and are itching to install ISE Webpack, go for it! Don't bother with this forum to analyze the situation... execute! And have fun with Xilinx@home! - John_HArticle: 128963
"Dave" <Dave@yahoo.com> wrote in message news:foqmok$c7t$1@aioe.org... > Hi > > Difficult to describe, > For sure, but you did it well. > > So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 > LSB bits. Is there maybe a better approach to do implement this on an > FPGA? Dunno, but you're so good at describing, I'll guess you thought about this before posting. So, I'll bet on your solution. Is there a trick? Cheers, Syms.Article: 128964
Dave wrote: > Hi > > lets assume I have two signals, each carrying 8 bits of information. > One signal is a so called configuration signal and has exactly 4 bits > that are HIGH and 4 bits that are LOW. Now depending on on the values > of the configuration signal I wanna reorder the bits in the other signal > in the following way: If a bit is set in the configuration signal, then > the corresponding bit in the source register will be part of the most > significant 4 bits of the result signal. If a bit in the configuration > signal is not set then the corresponding bit in the source register will > be part of the least significant 4 bits. Difficult to describe, so here > an example > > Source: A B C D E F G H > Configuration: 1 0 1 0 1 0 1 0 > > Result = ACEG BDFH > > So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 > LSB bits. Is there maybe a better approach to do implement this on an FPGA? I'm thinking this eloquent description is from a textbook problem. Can you tell me if the order in the result has to be the same as the order in the source? Can you describe the inputs and outputs to an 8-4 mux? Chances are you haven't thought that through. If you had 8 8-1 muxes instead, how would you determine the control for each one? I'm guessing you can do this with a simple cascade of 2-1 muxes. Think about how you might use a simple 2-1 mux and some slight additional control generation to produce several stages of intermediate results before settling on a final result. The joy and the challenge of electronics includes wrapping your mind around the problem and figuring out how you can dice the problem up to get the desired result. Different engineers will produce different "right" results. Show me how you can use 2 8-4 muxes (specifically devices that can be found in Verilog or VHDL libraries) and I'll send you $20 toward next semester's books. - John_HArticle: 128965
Dave wrote: > Hi > > lets assume I have two signals, each carrying 8 bits of information. > One signal is a so called configuration signal and has exactly 4 bits > that are HIGH and 4 bits that are LOW. Now depending on on the values > of the configuration signal I wanna reorder the bits in the other signal > in the following way: If a bit is set in the configuration signal, then > the corresponding bit in the source register will be part of the most > significant 4 bits of the result signal. If a bit in the configuration > signal is not set then the corresponding bit in the source register will > be part of the least significant 4 bits. Difficult to describe, so here > an example > > Source: A B C D E F G H > Configuration: 1 0 1 0 1 0 1 0 > > Result = ACEG BDFH > > So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 > LSB bits. Is there maybe a better approach to do implement this on an FPGA? The example does not really match the text...? If each output can be one of two sources, selected by each config bit, that is 8 x 2:1 MUX's, and you can have any mapping you like (including the one in the example) -jgArticle: 128966
Hi all, Looking at the Xilinx IP core documentation I found only 2 versions of reed solomon decoder implemented on Virtex-5 (RS decoder version 6.1) and Virtex-2pro (RS decoder version 5.1). I need to know how this IP core will consume (LUTs, slices, Block RAM/FIFO, Frequency) if it is implemented on virtex-4 (xc4vfx12-10ff668 or XC4vlx100-11ff668). Any documentation will be helpful. Thank you.Article: 128967
I didn't work with ActiveHDL, but I know that with ActiveHDL you cannot do post place and route simulation. This soft is only for behavioral simulation.Article: 128968
Have you tried getting an evaluation license from Xilinx? Once you have that, you could build it yourself in your technology of choice... Just remember, the evaluation product will not run for very long. (We accidentally build an FPGA with it, and wondered why the decoder stopped working after several hours....) JTW "nezhate" <mazouz.nezhate@gmail.com> wrote in message news:6b82f5a0-3d33-43b6-9fb1-3cf10550a8c7@1g2000hsl.googlegroups.com... > Hi all, > Looking at the Xilinx IP core documentation I found only 2 versions of > reed solomon decoder implemented on Virtex-5 (RS decoder version 6.1) > and Virtex-2pro (RS decoder version 5.1). I need to know how this IP > core will consume (LUTs, slices, Block RAM/FIFO, Frequency) if it is > implemented on virtex-4 (xc4vfx12-10ff668 or XC4vlx100-11ff668). Any > documentation will be helpful. > Thank you.Article: 128969
> I have to divide a 48MHz clock to obtain a clock with differents > frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. The first question might be: Why do you need these clocks and what are you trying to do with them? If you have data running at those rates, you can simply repeat data to make it update at the desired rate. To exagerate, with a 100MHz clock you would need to repeat each word 1000 times to get an output that changes at a 100KHz rate. Similar math for the other rates. A long time ago in school my APL professor (not a very common language today) insisted that the most important task before approaching a project was to really think about the representation of the problem. The same problem can either become very complex or very simple depending on the representation. -MartinArticle: 128970
Dave schrieb: > Hi > > lets assume I have two signals, each carrying 8 bits of information. > One signal is a so called configuration signal and has exactly 4 bits > that are HIGH and 4 bits that are LOW. Now depending on on the values > of the configuration signal I wanna reorder the bits in the other signal > in the following way: If a bit is set in the configuration signal, then > the corresponding bit in the source register will be part of the most > significant 4 bits of the result signal. If a bit in the configuration > signal is not set then the corresponding bit in the source register will > be part of the least significant 4 bits. Difficult to describe, so here > an example > > Source: A B C D E F G H > Configuration: 1 0 1 0 1 0 1 0 > > Result = ACEG BDFH > > So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 > LSB bits. Is there maybe a better approach to do implement this on an FPGA? Hi Dave, what if the two signals are just two wires, and the 8 Bits of information come in serially? (Let's just assume it for the moment.) Then you would just need two 4 bit shift regs with parallel outputs and an inverter on one of the shift regs Clock Enable. Depending on the Configuration bit the Source data would eiter be shifted into the MSB-SR or the LSB-SR. And if the signals actually do have 8 bits of parallel data, you can still use the above solution, if you can clock this circuit at 8 times the datarate (if possible). Of course you need another two 8 bit parallel to serial SRs. Have a nice Synthesis EilertArticle: 128971
Wrong. You can do all the types of simulation with the same probes that you can do with ModelSim. You probably shouldn't comment on software that you haven't used before. ---Matthew Hicks > I didn't work with ActiveHDL, but I know that with ActiveHDL you > cannot do post place and route simulation. This soft is only for > behavioral simulation. >Article: 128972
On 12 f=E9v, 07:46, m <martin.use...@gmail.com> wrote: > > I have to divide a 48MHz clock to obtain a clock with differents > > frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. > > The first question might be: Why do you need these clocks and what > are you trying to do with them? > > If you have data running at those rates, you can simply repeat data to > make it update at the desired rate. > > To exagerate, with a 100MHz clock you would need to repeat each word > 1000 times to get an output that changes at a 100KHz rate. Similar > math for the other rates. > > A long time ago in school my APL professor (not a very common language > today) insisted that the most important task before approaching a > project was to really think about the representation of the problem. > The same problem can either become very complex or very simple > depending on the representation. > > -Martin First, Thanks for all your anwers. In fact, I have to use the verilog core sources of a processor (originaly developped for silicium). The problem is the processor is made of latchs, internal tristate buses, and keepers which keep values on buses when there are not active drivers. More precisely, the core runs using two 180=B0 clocks with a nonoverlap time between the two, and during this time, the keepers assume that the last value is kept on the bus, that avoids hold violations. But in the FPGA, there are not any internal keepers, so I use my master clock (used to generate the two previous clocks) for reclocking critical tristate buses and to drive them during non overlap time.. The problem, I think, is like I create the two clocks using master clock, a counter, and a comparator, I create a delay between master clock edge and the others clocks edge, and like I reclock data generated on first two clocks with the master clock, I've a path between the two clock domains (which in fact are the same..) That's why I'm looking for generating the two 180=B0 clocks on an other way, for reducing delay between them and master clock. Thanks for your comments and idea.. Best regards, Michel.Article: 128973
On 12 Feb., 07:56, backhus <n...@nirgends.xyz> wrote: > And if the signals actually do have 8 bits of parallel data, you can > still use the above solution, if you can clock this circuit at 8 times > the datarate (if possible). Of course you need another two 8 bit > parallel to serial SRs. You can even use this thinking to model a parallel single clock solution. You write a for loop and just omit the registers. Essentially what you create is a chain, where bit N is either taken from the right neighbour or from the input depending selctor bit at that position. (i.e. one output skips all 0s, the other all 1s) Kolja SulimmaArticle: 128974
On Feb 12, 9:26 am, "jtw" <wrightjt @hotmail.invalid> wrote: > Have you tried getting an evaluation license from Xilinx? Once you have > that, you could build it yourself in your technology of choice... > > Just remember, the evaluation product will not run for very long. (We > accidentally build an FPGA with it, and wondered why the decoder stopped I didn't try to get an evaluation license from Xilinx. Thank you for your helpful information. Nezhate.
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