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michel.talon@gmail.com wrote:
> So, at the end of the last week, ( and thanks to Martin : "[...] the
> most important task before approaching a project was to really think
> about the representation of the problem [...]"), I decide to take two
> weeks to try something I thought since a long time : convert this
> strange design in full synchronous FPGA design..
You are on the right path.
Extract the requirements from the old design,
then make it your own with portable, synchronous hdl code.
Use an rtl viewer and simulation to check your work.
-- Mike Treseler
Article: 129201Guru wrote: > I had FX12 totally full, with only 2 point-to-point PLB busses > connected to MPMC2 and PPC. For access to peripherals I used > exclusively DCR (low logic resources and high responsiveness), for > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. > I recommend NPI for very high DMA bandwidth. > > Too bad that with EDK 9.2 the bus diversity is gone. You have to to > use PLB in all cases. Ales, I'm still on 9.1. What bus diversity is changed in 9.2? -JeffArticle: 129202
On 18 Feb., 01:35, Peter Alfke <al...@sbcglobal.net> wrote: > On Feb 17, 3:20 pm, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: > > > > > "Peter Alfke" <al...@sbcglobal.net> wrote in message > > >news:cc16e624-1612-49ba-bfc8-0a5da09a622f@h11g2000prf.googlegroups.com... > > > > Our friend Antti is out of a job. > > > Is there somebody in the Munich area who can offer a job, or some > > > consulting ? > > > I need not explain that Antti is a really sharp engineer with lots of > > > FPGA experience. > > > You all know that. > > > > You can reach him at > > > > antti.luk...@googlemail.com > > > > Peter Alfke, who posted this on his own, because he cannot stand a > > > friend be so unhappy. > > > Ask Antti if he wants to move to the northwest Los Angeles county area. I'm > > sure I could get him into a great company, AND, they're a very large user of > > Xilinx. > > > Bob > > Thanks, Bob, for the kind offer. I tend to discourage the idea of > immigrating to the U.S. (funny, coming from me as an immigrant!) > because of the horrible bureaucracy and visa delay. I had its easy in > 1968, but now it is a nightmare. U.S. competitiveness is bound to > suffer... > Peter Alfke Hi Bob and Peter, first of all, thanks - while I could move almost anywhere, I do have two small kids (boy 6, girl 4) and the boy needs special care because delayed speech development (he talks all the time, but its really hard to understand what). This limits the options for the re-location with the family. Moving away from German spoken region, or even moving away from Munich could have bad impact on the kids. So options left for my family are either Munich area or then back home to Estonia. I myself however could take project based jobs with up to 3 months abroad (almost anywhere where needed). Sure it would have to pay well paid jobs for me to consider be away from the family for any longer time. I have been to US west-coast i think 12 times, but not anymore recently. But I know the visa issue, so I agree with Peter that anyone should think very carefully when planning immigration to US. Hm.. for possible offers, I know 5 human languages equally bad English, German, Russian, Estonian, Finnish - I mean I speak them bad compared to my skills with formal languages be it programming languages or (hardware) description languages. I could as example be useful when outsourcing projects from the "ex-UdSSR" area. There are still talented people there, and if they are "found, identified and verified to be reliable" then it could be a goldmine for some company looking for reduction of development costs. For this to work out some one knowing the region and people is almost a must have. As example I have one really good PCB designed from Ukraine that I work with, he is really a pro. But he prefers to talk in russian so I write cyrillica to him (on german keyboard) as it is easier for him to communicate so. Antti Lukats P.S. To Peter, it's not that I am not happy, I live my live without regrets (also when failing the goals). But yes I have issues that stress me a lot, and those issues may - well the kids feel the stress. So it's about their happiness, not mine.Article: 129203
On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote: > Guru wrote: > > I had FX12 totally full, with only 2 point-to-point PLB busses > > connected to MPMC2 and PPC. For access to peripherals I used > > exclusively DCR (low logic resources and high responsiveness), for > > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. > > I recommend NPI for very high DMA bandwidth. > > > Too bad that with EDK 9.2 the bus diversity is gone. You have to to > > use PLB in all cases. > > Ales, > I'm still on 9.1. What bus diversity is changed in 9.2? > -Jeff Microblaze 7.0 doesnt have OPB bus anymore. was a real shock ! Old designs still can be used. But all new systems have all new IP-Cores! AnttiArticle: 129204
On 18 Feb., 16:47, morphiend <morphi...@gmail.com> wrote: > Anyone ever run into an issue where the PowerPC can write to entities > on its DPLB, but cannot read from them? > > I've added chipscope to the PLB and everything looks right from the > control lines. I singled-stepped the first read instruction on the > PowerPC and after stepping that instruction the PPC goes off into 'la- > la' land. > > My system consists of a PPC w/ Instruction side and Data side OCMs, a > PLB attached the DPLB0 port, a MPMC3, interrupt controller, uartlite, > and host I/F for the TEMAC attached to the PLB. some (maybe all) Xilinx memory cores for DDR2 will go la-la land on read accesses when the memory controller misses DQS strobe from the memory chip once. But in that case the PPC should go la-la also on instruction fetched from the MPMC3 So it is possible that there is some problem with the memory controller or timings or UCF file, etc AnttiArticle: 129205
On Feb 18, 12:15 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 18 Feb., 16:47, morphiend <morphi...@gmail.com> wrote: > > > Anyone ever run into an issue where the PowerPC can write to entities > > on its DPLB, but cannot read from them? > > > I've added chipscope to the PLB and everything looks right from the > > control lines. I singled-stepped the first read instruction on the > > PowerPC and after stepping that instruction the PPC goes off into 'la- > > la' land. > > > My system consists of a PPC w/ Instruction side and Data side OCMs, a > > PLB attached the DPLB0 port, a MPMC3, interrupt controller, uartlite, > > and host I/F for the TEMAC attached to the PLB. > > some (maybe all) Xilinx memory cores for DDR2 will go la-la land > on read accesses when the memory controller misses DQS strobe > from the memory chip once. But in that case the PPC should go > la-la also on instruction fetched from the MPMC3 > > So it is possible that there is some problem with the memory > controller > or timings or UCF file, etc > > Antti Right now, the problem occurs not only on a memory access, but the TEMAC attached to the PLB. Also, I'm only using the DDR, not DDR2, for the MPMC. From what I saw from via chipscope, the memory controller was properly behaving as I expected (the same as the TEMAC).Article: 129206
Julien Lochen wrote:
> How to specify with XST that an input of a VHDL entity is a clock ?
> I guess it is not automatic because after the XST logic synthesis,
> noone of my "process" have been synthetized ?
XST or quartus synthesis will find the clock in
vhdl code that matches a synchronous process template.
There are many ways to do this.
Here's one:
architecture synth of sync_template is
begin
sync_template : process(reset, clock) is
-- <declarations go here>
begin -- process template
if reset = '1' then
init_regs; -- init code here
elsif rising_edge(clock) then
update_regs; -- update code here
end if;
update_ports; -- port assignments here
end process sync_template;
end architecture synth;
details here:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 129207On Mon, 2008-02-18 at 09:05 -0800, Antti wrote: > On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote: > > Guru wrote: > > > I had FX12 totally full, with only 2 point-to-point PLB busses > > > connected to MPMC2 and PPC. For access to peripherals I used > > > exclusively DCR (low logic resources and high responsiveness), for > > > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. > > > I recommend NPI for very high DMA bandwidth. > > > > > Too bad that with EDK 9.2 the bus diversity is gone. You have to to > > > use PLB in all cases. > > > > Ales, > > I'm still on 9.1. What bus diversity is changed in 9.2? > > -Jeff > > Microblaze 7.0 doesnt have OPB bus anymore. > was a real shock ! > > Old designs still can be used. > But all new systems have all new IP-Cores! > > Antti > > > > Microblaze 7.0 still has OPB. But you have to switch it on. JanArticle: 129208
On 18 Feb., 20:06, Jan Pech <inva...@void.domain> wrote: > On Mon, 2008-02-18 at 09:05 -0800, Antti wrote: > > On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote: > > > Guru wrote: > > > > I had FX12 totally full, with only 2 point-to-point PLB busses > > > > connected to MPMC2 and PPC. For access to peripherals I used > > > > exclusively DCR (low logic resources and high responsiveness), for > > > > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. > > > > I recommend NPI for very high DMA bandwidth. > > > > > Too bad that with EDK 9.2 the bus diversity is gone. You have to to > > > > use PLB in all cases. > > > > Ales, > > > I'm still on 9.1. What bus diversity is changed in 9.2? > > > -Jeff > > > Microblaze 7.0 doesnt have OPB bus anymore. > > was a real shock ! > > > Old designs still can be used. > > But all new systems have all new IP-Cores! > > > Antti > > Microblaze 7.0 still has OPB. But you have to switch it on. > > Jan ups! by default BSB with 9.2 its only PLB configured so I used older version of MB for old systems AnttiArticle: 129209
Antti wrote: > On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote: > >>Guru wrote: >> >>>I had FX12 totally full, with only 2 point-to-point PLB busses >>>connected to MPMC2 and PPC. For access to peripherals I used >>>exclusively DCR (low logic resources and high responsiveness), for >>>high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. >>>I recommend NPI for very high DMA bandwidth. >> >>>Too bad that with EDK 9.2 the bus diversity is gone. You have to to >>>use PLB in all cases. >> >>Ales, >>I'm still on 9.1. What bus diversity is changed in 9.2? >>-Jeff > > > Microblaze 7.0 doesnt have OPB bus anymore. > was a real shock ! > > Old designs still can be used. > But all new systems have all new IP-Cores! So much for the often-vaunted claims of 'design longevity' when using SoftCPU cores then ! ;) Seems to have caught the Software Version Creep disease.... ? -jgArticle: 129210
Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write both testbench and testcase in VHDL. But I feel VHDL is not that nice to implement testcase. So I am thinking to implement my testbench in VHDL, and write the testcases in TCL for my next project. Of course the verification should be self-checking. Does it sounds feasible? How is the simulation speed? Can anyone give me some reference? Thanks in advance. -Best Regards JimArticle: 129211
bigyellow wrote:
> Does anybody have experience on writing TCL testcase in Modelsim? I
> only have VHDL simulation license of Modelsim, I used to write both
> testbench and testcase in VHDL. But I feel VHDL is not that nice to
> implement testcase.
I would consider a testcase to be a subset of a testbench.
I would also consider vhdl to be 'nicer' than TCL for this purpose.
See http://home.comcast.net/~mike_treseler/test_uart.vhd
-- Mike Treseler
Article: 129212
Andreas Ehliar wrote:
> On 2008-02-16, Bob Smith <usenet@linuxtoys.org> wrote:
>> Does anyone know of a way to program the Basys board over
>> the USB cable using Linux?
>
> http://rmdir.de/~michael/xilinx/ has a windrv replacement library
> which you can LD_PRELOAD before starting impact. Personally
> I have used it exclusively instead of windrvr for a while now and
> it works perfectly with the platform USB cable.
Thanks, Andreas and Michael.
I've tried the USB driver and have followed the directions
in the README to edit the udev rules, copy the *.hex files
and to be sure /sbin/fxload is available. It looks like the
firmware download is not taking place as the USB IDs do not
change as expected after the firmware download. I still get
root@pohl:usb-driver# lsusb
Bus 004 Device 012: ID 1443:0005
ISE/impact give the following error when I try to download
the BASYS bit file build in the demo project:
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/Xilinx92i/bin/lin/xusbdfwu.hex = 1030.
File version of /usr/share/xusbdfwu.hex = 1030.
libusb-driver.so version: 2008-01-20 04:17:11.
Cable connection failed.
I tried adding the 1443:0005 to ~/.libusb-driverrc but that did
not make any difference.
Any more idea?
thanks
Bob Smith
Article: 129213Yes, I also did the same thing. Wrote hundreds of procedures and then use them in different testcases. I think it is quite complicate. For example, I need logics, procedures etc to control the behavior of testbenchs, but in modelsim, I can do it by forcing the register's value directly, rather than use vhdl procedure to write the register. I am starter of tcl, and I just wonder to know if using TCL could simplify the verification process. -Jim On Feb 18, 10:46 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > bigyellow wrote: > > Does anybody have experience on writing TCL testcase in Modelsim? I > > only have VHDL simulation license of Modelsim, I used to write both > > testbench and testcase in VHDL. But I feel VHDL is not that nice to > > implement testcase. > > I would consider a testcase to be a subset of a testbench. > I would also consider vhdl to be 'nicer' than TCL for this purpose. > Seehttp://home.comcast.net/~mike_treseler/test_uart.vhd > > -- Mike TreselerArticle: 129214
bigyellow wrote:
> Yes, I also did the same thing. Wrote hundreds of procedures and then
> use them in different testcases.
> I think it is quite complicate. For example, I need logics, procedures
> etc to control the behavior of testbenchs, but in modelsim, I can do
> it by forcing the register's value directly, rather than use vhdl
> procedure to write the register.
Once I have virtualized a register load with a vhdl procedure,
calling this procedure is no more difficult than a tcl force command.
It also matches what the firmware has to do.
If vhdl can't cover a verification, neither can the system software.
> I am starter of tcl, and I just wonder to know if using TCL could
> simplify the verification process.
TCL is well suited to orchestrate multiple OS commands and vsim runs
if python or sh is not available. I would not use it directly
for bit level stimulus or verification, but some do.
-- Mike Treseler
Article: 129215I am trying to pick up the Lattice ispLEVER tool and am having a bit of trouble with it in regards to libraries. I have several files for the various libraries I have written for my VHDL. In order to use them, they have to be compiled in the correct order since some use definitions from the others. I can't seem to figure out how to tell ispLEVER what order to compile the files. It has a way to telling the tool that a given file *is* a library, but that seems to be where it stops. I can't order the files in the project and it doesn't seem to actually understand that the libraries exist in the VHDL. I get several error message all related to libraries not found or identifiers not declared that should have been in the library files. I have looked through every piece of documentation I can find and they all pretty much gloss over the idea of user defined libraries. Is this something so simple I have missed it?Article: 129216
I'm going to talk to a potential new client about using FPGAs to accelerate part of their system. As part of what needs done there could be a significant amount of division(s) done. Previously I've been able to multiply by a reciprocal then scale to make division a double clock operation so this can be easily pipelined. This is only achieveable if the divisor is pre-known and the reciprocal can be pre-calculated. With what's coming up I'm not sure that I can do this, I know that Are there any clever techniques for streamlining divisions that make them deterministic and don't use a big wodge of logic? Thanks for any pointers, NialArticle: 129217
> I absolutely agree that it's a smart move to keep the number > of processes reasonably small (and, of course, Mike Treseler > would be even more emphatic about that). But to suggest that > there should be only one per clock is truly nonsensical. > What rationale is given for that rule? The explanation was that it was to cut down the mistakes made with clock enables! > Does this truly mean "no unconstrained paths", or does it > mean "no path without its own explicit constraint"? No unconstrained paths. From memory in ISE there's an output at the end of the run which tells you how many paths are unconstrained. This had to read 0. This company is a big 'household' name and I have a lot of respect for the engineers there, they were good guys. I just didn't understand these two mad rules. > I suspect that oddities rather come with the territory when > you're working as a contractor. Like the design I had to > rework a few years back, which had started life as a schematic > and caused Quartus to report something like 130 different > clocks... I had one where the FPGA built with ripple clocks everywhere with a reported maximum speed of 28MHz odd. They were clocking it at 50 MHz. That too was a start from scratch re-design. :-( Nial.Article: 129218
Nial Stewart <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: > I'm going to talk to a potential new client about using FPGAs to > accelerate part of their system. > As part of what needs done there could be a significant amount of > division(s) done. > Previously I've been able to multiply by a reciprocal then scale to > make division a double clock operation so this can be easily pipelined. > This is only achieveable if the divisor is pre-known and the > reciprocal can be pre-calculated. > With what's coming up I'm not sure that I can do this, I know that > Are there any clever techniques for streamlining divisions that > make them deterministic and don't use a big wodge of logic? Do you need high throughput and short latency? If latency isn't that big issue, I have successfully used the serial devider from opencores.Otherwise there are more divider projects at opencores. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 129219
> This is a perfect cue for the embarrassing moment when > Nial points out that his client got their style guidance > from us..... nah, just kidding (I hope) :-) No, they had generated this themselves. It was generally very good, they had taken a good look at how best to structure design directories for clarity and re-use, used source control etc. It was just these two odd rules I didn't agree with. Nial.Article: 129220
Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would like to generate a core that controls 7 chips (x16), this results in 112 DQ pins. The chips would use a clock of 133MHz. Has anybody got experience with the MIG tool? Is it user-friendly or do you prefer to write your own DDR core? thanks and best regards, KarelArticle: 129221
Greetings , I am trying to implement a solution for an FPGA that needs to be configured with two different programs because the whole system will operate in two different modes. Basically what I need is a device that contains two programs and depending on the user will program one of each. The pinout will be the same because it is a digital filter. One thing that came to my mind is putting a PIC that would emulate a PROM and would retrieve the corresponding program from a FLASH memory. Do you know how can I optimize this? Is there any commercial solution around? Thanks in advance , and sorry for my bad english. AlfredoArticle: 129222
On Feb 19, 4:26 pm, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote: > Greetings , I am trying to implement a solution for an FPGA that needs > to be configured with two different programs because the whole system > will operate in two different modes. Basically what I need is a device > that contains two programs and depending on the user will program one > of each. The pinout will be the same because it is a digital filter. > One thing that came to my mind is putting a PIC that would emulate a > PROM and would retrieve the corresponding program from a FLASH > memory. > > Do you know how can I optimize this? > Is there any commercial solution around? > > Thanks in advance , and sorry for my bad english. > > Alfredo Alfredo, Two solutions in my knowledge, Try Dynamic Partial reconfiguration, If you are using Xilinx FPGA's, try MicroBlaze as configuration controller. It may require a bit of effort from your side. Use a Micro-controller as configuration controller, configuring the FPGA in Slave serial mode through Micro-Controller is far easier than emulating the functionality of PROM through Micro-controller. Hope this helps /MHArticle: 129223
> Microblaze 7.0 still has OPB. But you have to switch it on. Good to know!! GuruArticle: 129224
On Feb 18, 5:20=A0pm, Jeff Cunningham <j...@sover.net> wrote: > Guru wrote: > > I had FX12 totally full, with only 2 point-to-point PLB busses > > connected to MPMC2 and PPC. For access to peripherals I used > > exclusively DCR (low logic resources and high responsiveness), for > > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. > > I recommend NPI for very high DMA bandwidth. > > > Too bad that with EDK 9.2 the bus diversity is gone. You have to to > > use PLB in all cases. > > Ales, > I'm still on 9.1. What bus diversity is changed in 9.2? > -Jeff DCR and OPB is gone. Guru
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