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On Jan 8, 9:59=A0am, quark.flav...@gmail.com wrote: > On Jan 8, 12:53=A0pm, j...@capsec.org wrote: > > > Strange, I remember DCM_SP is the DCM variant one should use in > > Spartan3E... Can't remember for sure... > > DCM_SP should be correct, it is the Spartan3E DCM. > > Andrew Hello , I have been following your lm32 SOC thread on the fpgafaa for quiet some time.I am new to the field of softcore/SOCs. I am interested in an open core SOC to implement a Ethernet MAC controller for my Spartan3E FPGA on my Spartan3E starter kit. That is when I came across your work. I have to admit your spirit for open source, excellent job. Now, that I have seen how sucessfuly you have ported the core to Spartan3E FPGA i have a few questions. (1) How do I implement the core on the Spartan3E FPGA? I downloaded the SOC from "https://roulette.das-labor.org/~joerg/pkg/soc-lm32.zip, and tired to complie the design on ISE9.1i. I got this error as the compiler was missing a file. HDLCompilers:26 - "../../soc-lm32/soc- lm32/boards/xilinx-s3esk/system.v" line 6 Could not find verilog include file 'ddr_include.v'. I thought I can compile the design with the system.v and system.ucf and I should be able to generate the bit stream to load and prgram the FPGA with? Am I wrong in this assumption. What am I missing here?? Are there any other files that is supposed to go with this?? (2) Browsing your other folders, I find that there is one called firmware that has a bootloader,ddr-phaser and hw-test? What are these for?? Then, there is this whole bunch of folders that have the RTL . What am i supposed to do with those?? Sorry to bother you with these pesky questions. Thanks for your time and patients.Article: 129401
Clemens Blank <CBlank@hotmail.com> wrote: >Hi > >I just came across some interview questions for digital design, and >would like to discuss my solutions with you! > >#Design a circuit to divide input frequency by 2 >I could do this with a Toggle Flip flop where the inverted output >is connected to the input, then i also divide the clock frequency by two > ># Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle. >I was thinking of having here a statemachine that outputs for 3 cycles >0, and then it changes the state to output 3 times a 1 at each clock >transition. > ># Which one is superior: Asynchronous Reset or Synchronous Reset > >Well, until now I was always using asynchronous resets because u >find it in most textbooks ;) not so sure about the right answer here! The best answer to all these questions is a question. Starting with the architecture / type of logic. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129402
Jim Granville wrote: > Jon Elson wrote: > >> >> >> Alfreeeeed wrote: >> >>> >>> Looks like SPI Master Mode is the option. I am interested in Jon's >>> alternative of putting a memory twice the size a program need. Any >>> ideas how to implement this? BTW , I also need to program two FPGA >>> with the same program so I would need to do daisy chain with a >>> Spartan-3E. >> >> >> >> Well, I'm not going to reveal all my secrets for free, but a fairly >> simple scheme can be figured out for the SST chips. They need an >> "instruction" byte serially shifted in to program the memory to read >> from the beginning. > > > I've often wondered why these Serial FLASH vendors have missed the > REALLY OBVIOUS option, of alias of a 00 or FF opcode to read, > so you could simply connect their serial memory, and just clock to > stream out data. Would be 100% upward compatible with present > usage. Yup, that would have made it easier, and probably saved two chips to default to read out one FPGA config. For that case, using the SST chip, I had to generate a couple 1 bits in the first byte and then zeros from then on to get what I wanted. JonArticle: 129403
"austin" <austin@xilinx.com> wrote in message news:fpmq00$83b1@cnn.xsj.xilinx.com... > BobW, > > Hspice licenses do not cost 100K, in fact they are >10X less than that > amount... > > I apologize, but our foundries device models belong to them, and they > must remain encrypted, and secret. Hspice is the only vehicle today > that is available to support this (and is commonly used to do so). > > Are there other spice that support encryption? Sure. But they are not > as common as Hspice. We have to support this for all customers, so it > isn't for free. > > If you submit a webcase, you will get an answer from an IO specialist, > if you request a Hspice result for a simulation (or two). Just be > SPECIFIC. > > And, obviously, the IOB netlist belongs to Xilinx, and we are not > interested in disclosing it to the world, so everyone who isn't able to > make their 65nm process work, gets a chance to see how we did it. > > Austin Austin, I do understand about the need to protect your property. It is a frustrating time because edge rates are going beyond what the accuracy of the (low cost) IBIS simulators can provide, and the only other solution is the (high cost) HSPICE stuff. Here are the approximate HSPICE costs. This includes the license and the simulator front end: $50K plus $8K/yr (maintenance) or optionally, as a lease: $25K/yr BobArticle: 129404
Stef wrote:
> I have studied that page an came up with this:
> entity bufbidir is
...
> Any good?
I don't know your requirements.
Run a sim and check the RTL viewer.
This is how quartus sees your design:
http://home.comcast.net/~mike_treseler/bufbidir.pdf
> I did leave out the reset as it will only take a few clocks
> to get the final values on all signals.
I would add the reset input.
It costs nothing.
It makes simulation much easier.
It allows me to combine processes.
-- Mike Treseler
Article: 129405
On Feb 17, 7:18 am, Narendra Sisodiya <narendra.sisod...@gmail.com>
wrote:
> On Feb 17, 4:04 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > On Sun, 17 Feb 2008 02:04:54 -0800 (PST), Narendra Sisodiya wrote:
> > >Hi, My Project title is "Serial RF Core for Multimedia Stream
> > >Transfer"
> > >I am using Xilinx Video Starter Kit, and I supposed to transfer a
> > >video stream over RF, using Bluetooth,
> > >I am totally confused
Hello to all,
I have video stater kit (ML402). using EDK i want to setup up a
streaming server on board, (rtp - rstp), earlier i was trying to port
Linux on powerpc and then i wanted to install or setup a server. but
this approach is rejected.
1) -- may any body tell me the complexity and steps involved in
setting up this kind of thing. I need to transfer video on RF. later I
want to transfer streamed video over ip. essentially this will be
streaming over ip, and I have studied that ip-based streaming possible
on bluetooth stack via (LAP or BNEP profile).
2) -- How I can compress (mpeg4) on FPGA -- is there any core
present or can be used to convert raw video to compressed video
3) My Kit (Ericsson Bluetooth application toolkit ROK101007
module ) contain lower layers upto HCI. the layer above it (RFCOMM and
L2CAP ) are provide as software, I want to connect my bluetooth kit to
FPGA board through UART. is there any hardware implementation (on
FPGA ) present for upper layers so that my FPGA uart will be connected
to RFCOMM.
4) other possible case I studied in a research paper is --
streaming over HCI, in this case i need to transfer video packet over
HCI layer directly. and this case does not require L2CAP and RFCOMM on
FPGA,
5) what is the difference between transmitting mpeg4 compressed
video file and Live video being compressed by mpeg4.
6) can I compile OpenBT library for poerpc and use then in EDK
environment. blueZ is not having support for powerpc.
till now i have done any significant FPGA programming using EDK
Article: 129406Nico Coesel wrote: > > The best answer to all these questions is a question. Is it?Article: 129407
Hello, I just received the package and it has the fpga board, usb cable, and power supply. I am am trying to it with Suse 10.2. I have installed the WebPack+SP4 softwares. Of course the kernel modules don't quite work, missing kernel symbol from xpc mod. So I can't use the xpc module. Windrv module works. I found this site: http://gentoo-wiki.com/HOWTO_Xilinx#Method_1:_kernel_modules I am using method 3, with usb-driver as a wrapper on top of IMPACT. This package compiled fine and I use LD_PRELOAD=/usr/local/lib/libusb-driver.so ise to start ISE. I have the board powered up and usb attached (dmesg showed the usb connect is recoganized). Ok here comes my question: how do I interact with the board? I'd imagine I could use minicom with a null serial connection with the board. But in the case of usb connection, what softwares should I use to see the boot up and menu of the board? Any good book or website for a complete fpga newbie (with proficient computer architecture and software engineering background). Thanks, FeiArticle: 129408
Fei Liu wrote: > Ok here comes my question: how do I interact with the board? I'd imagine > I could use minicom with a null serial connection with the board. But in > the case of usb connection, what softwares should I use to see the boot > up and menu of the board? Maybe that's different with your Spartan 3A starter kit, but with my Spartan 3E starter kit, there was only one USB connector, which is connected to a CPLD, which just converts the USB data to JTAG for programming the FPGA and the flash. There is no boot up menu (but there is a FPGA configuration flashed for board demo), it's all hardware and you have to write your own. You write VHDL code, which then controls the board, same as if you would use lots of logic gates. The hardware configuration (synthezied VHDL programs) is programmed via the USB interface and then you can use minicom to connect to your hardware, if you have written some VHDL program for the serial port, like this one: http://www.frank-buss.de/vhdl/spartan3e.html (note: this is old code, the serial port program is a bit unsafe, at least it didn't work stable for a Cyclone, unless I added a latch for the RX input and today I would write it less complicated, Whishbone doesn't make sense for such simple and synchronous designs with one clock). I've seen some hacks for the CPLD to use the USB port on the board for other things, but Xilinx didn't described the internals, like many other informations are not published by FPGA vendors, maybe because of trade rivalry, which is really cumbersome for developers like me, who wants to understand and use it down to the lowest level, if necessary and maybe for other tasks than the vendors have thougt for which it can be used and with other tools than the vendor synthesize tools. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 129409
BobW, Hmmm, they have raised their prices since I last checked. Either that, or the people I talk to all fight for a discount. The cost of one license will still be less than one re-spin and re-manufacture of one pcb assembly lot from one screw-up that the license could prevent (ie it is cheap insurance to get something right the first time). As to "not understanding about protecting our property" that is something I can not hope to change, as if you do not respect my property rights (or Xilinx' property rights), I would rather not communicate with you any further. Fine with me. Have fun. Enjoy. AustinArticle: 129410
On Feb 20, 3:45 pm, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote: > jasonL schrieb: > > > I have a project to prototype an ASIC design on FPGA. What are the > > things I should do? Here is some of my concerns: > > Well .. good HDL code should be portable. ;-) > > > 1) I understand FPGAs usually have 4 look-up table. Should I rewrite > > the ASIC combinational logics to be four-inputs logics to improve the > > utilization of FPGA? > > No. Usually the FPGA is big enough. This is an advanced topic for > highly-optimized designs. > > > 2) Netting if and case statements over three layers might results a > > poor synthesis result in FPGA . Should I changes those netting codes > > in ASIC RTL? > > Flipflops are free in FPGAs. Therefore you can pipeline your design > easily. The only disadvantage are the additional clocks through the > pipeline. > > > 3) ASIC synthesis need to generate clock tree and power rails. In FPGA > > synthesis, Maybe I not need to care too much about it? > > Ususally you should place an instance of a component, that tells the > synthesis tool to use global clocks and global signals for reset. For > Xilinx this it a BUFG. > > > 4) Is there a to-do-list for this kind of job? > > Usually I replace memories with BlockRAM inside the FPGA and use > instances of clock buffers. Thats it. > > Fully synchronous designs are easily done on FPGAs, but even highly > clock-gated designs using a lot of latches run quite fine. > > Ralf Thank you all for the helps. It seems that a good synthesizer will do a lot of help.Article: 129411
Oops. I thought you did 'not' understand property rights. I apologize. My comment on the cost of the license is still valid: it is cheap insurance. Also, looks like they did raise their prices over what I have been told in years past. AustinArticle: 129412
BobW, Additionally, IBIS is not adequate for MGTs (gigabit transceivers) but perfectly valid for gigabit LVDS (for example). This has to do with IBIS inability to model the more complex drivers used for the MGTs, not the inability of IBIS and simulators to handle edge rates and t-line effects: they do that just fine. But, IBIS will not allow you to change the Vcc, as the model was "made" by a particular Vcc, and there is no way to dial in the Vcc you would prefer over the one built into the results (IBIS is just a look-up table, after all). AustinArticle: 129413
Frank Buss wrote: > Fei Liu wrote: > >> Ok here comes my question: how do I interact with the board? I'd imagine >> I could use minicom with a null serial connection with the board. But in >> the case of usb connection, what softwares should I use to see the boot >> up and menu of the board? > > Maybe that's different with your Spartan 3A starter kit, but with my > Spartan 3E starter kit, there was only one USB connector, which is > connected to a CPLD, which just converts the USB data to JTAG for > programming the FPGA and the flash. There is no boot up menu (but there is > a FPGA configuration flashed for board demo), it's all hardware and you > have to write your own. You write VHDL code, which then controls the board, > same as if you would use lots of logic gates. > I used the quick start tutorial and indeed I can now program the board. It's amazing! FeiArticle: 129414
In comp.arch.fpga, Mike Treseler <mike_treseler@comcast.net> wrote: > Stef wrote: >> I have studied that page an came up with this: >> entity bufbidir is > ... >> Any good? > > I don't know your requirements. I wanted an I/O buffer and that's what I got. I've read a lot here about retiming the input signal so I added that. Not sure about the output FF's though. > Run a sim and check the RTL viewer. I have run it on an actual device, will do the simulation later. Can't find an RTL viewer in my version of ISE (still on 8.2i). Spent a good amount of time look through the floor planner and saw things simular to what you show below, but not nearly as nice. > This is how quartus sees your design: > http://home.comcast.net/~mike_treseler/bufbidir.pdf That looks brilliant, exactly like I pictured it, thanks! But the question remains if this is a good way to handle I/O in an fpga. The signal is an asynchronous serial signal (uart like), so a little extra delay does not hurt at all. On the other side of the "UART" I will need a bus interface to a cpu. Adding all that delay there slows down the interface, so I might need another approach. >> I did leave out the reset as it will only take a few clocks >> to get the final values on all signals. > > I would add the reset input. > It costs nothing. > It makes simulation much easier. I will have a rethink on the reset. But can you explain how it easies simulation? The way i see it, all these FF's will have clocked in their values after 2 clocks, so any reset value is gone after that anyway. > It allows me to combine processes. Sorry, but I can't understand that one at all, must be my inexperience in this field. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Computers in the future may weigh no more than 1.5 tons." (Popular Mechanics, 1949)Article: 129415
Stef wrote:
> I wanted an I/O buffer and that's what I got. I've read a lot here
> about retiming the input signal so I added that. Not sure about the
> output FF's though.
They make it easier to meet timing in large processes.
However I would never use a separate entity just to infer a buffer.
> Can't find an RTL viewer in my version of ISE (still on 8.2i).
It might be worth your time to find it or upgrade.
This is a valuable tool for learning and debugging.
> On the other side of the "UART" I will need a bus interface to
> a cpu. Adding all that delay there slows down the interface, so
> I might need another approach.
A uart does not require tri-state pins at all.
-- Mike Treseler
Article: 129416Ah, it just Xilinx tools self terminates, not Xilinx. I was scared. ;-) I found that 9.1 is much more stable then 9.2. So I'm skiping 9.2 completely and wait for 10.1 which is comming , I guess, in March.Article: 129417
In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7
signal on board), but after browsing through ug300.pdf and s3a
schematics, I don't see anything that remotely makes sense. I understand
I need a input signal, but I have no idea which PIN would give me that
on S3A board.
Here is my vhdl source:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
Article: 129418leevv wrote: > I found that 9.1 is much more stable then 9.2. So I'm skiping 9.2 > completely and wait for 10.1 which is comming , I guess, in March. 9.2 P&R is sooooo much faster with big jobs.Article: 129419
Leverage.... The same way a 10% drop can cost you much more than 10%!!! JTW <jack.harvard@googlemail.com> wrote in message news:6e670d75-420b-470a-9411-3cbd6bec4961@o77g2000hsf.googlegroups.com... > On Feb 22, 6:52 pm, "jack.harv...@googlemail.com" > <jack.harv...@googlemail.com> wrote: >> On Feb 21, 10:33 pm, Clemens Blank <CBl...@hotmail.com> wrote: >> >> > Clemens Blank schrieb: >> >> > > Interview questions >> >> > and the best one I came across was to double the clock frequency. How >> > on >> > earth should this be possible, must be a trap! >> >> An easy answer is to use a DCM in Virtex FPGA ... :-) haha >> details, as said, PLL and DLL... > > Another interesting question I read from a newspaper yesterday, how to > get more than 10% gain if share prices increase by 10%?Article: 129420
On 22 Feb., 13:34, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2008-02-22, Antti <Antti.Luk...@googlemail.com> wrote: > > > whatever the supported features of Spartan3A-ICAP are, no other > > spartan family has anything related to self-reconfig at all, there is > > no ICAP. > > As a footnote I could add that I've seen a paper on a Spartan-3 based > system which reconfigured itself by using the external configuration > interface:http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2006/0... > > /Andreas LOL, yes I have seen that paper too of course. I forgot and did write incomplete I should have said no other spartan has self-reconfiguration WITHOUT special externak wiring, i.e. using on chip resources onlye (ICAP) AnttiArticle: 129421
I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
of 8 MHz but see only a constant 2 volts on the CLKFX output. The
google hits on this did not help.
It must be a simple mistake; any ideas what I'm doing wrong?
The "****" indicate the lines from the prototype that I've changed.
thanks
Bob Smith
==================================================================================
module clocks(clkin, clkout1, clkout2);
input clkin; // Digilent Spartan 3e starter kit 50 MHz clock
output clkout1; // Wanna be 8 MHz
output clkout2; // 50 MHz/32 for comparison
reg [7:0] count;
always @(posedge clkin)
begin
count <= count + 1;
end
assign clkout2 = count[4];
DCM #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(25), // Can be any integer from 1 to 32 **************
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 ************
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.0), // Specify period of input clock ***********
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X *********
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(clkout1), // DCM CLK synthesis out (M/D) ************
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(clkin), // Clock input (from IBUFG, BUFG or DCM) ************
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
Article: 129422On Feb 23, 11:29 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 22 Feb., 13:34, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > > > On 2008-02-22, Antti <Antti.Luk...@googlemail.com> wrote: > > > > whatever the supported features of Spartan3A-ICAP are, no other > > > spartan family has anything related to self-reconfig at all, there is > > > no ICAP. > > > As a footnote I could add that I've seen a paper on a Spartan-3 based > > system which reconfigured itself by using the external configuration > > interface:http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2006/0... > > > /Andreas > > LOL, yes I have seen that paper too of course. I forgot and did write > incomplete > I should have said no other spartan has self-reconfiguration WITHOUT > special > externak wiring, i.e. using on chip resources onlye (ICAP) > > Antti To Antti, Thank you so much for your responses. I also went through that paper seems like a very good solution to my problem, but i'm not able to understand it completely as i'm only a student without much (or u can say any) experience. How are they actually using that "Config Flash" block is not very clear. Can you help me on that? and ICAP?? You also talked about stopping the system clock in order to achieve reconfigurability in s3a. How can that be achieved? It is difficult for us to go for Virtex as of now. Are there any FPGAs from Altera that can help us?? To Peter Alfke, Thank you for ur replies I've of course considered the traditional method to run an updown counter by selecting manually the functionality. But i want to achieve the same thing through reconfiguration as a part of my college project. Can you explain me how to 'stop the clock to remove the glitches' as u mentioned?? Regards, Paru noyArticle: 129423
"Symon" <symon_brewer@hotmail.com> wrote: >Nico Coesel wrote: >> >> The best answer to all these questions is a question. > >Is it? Ofcourse. Interview questions are designed to start a technical debate in order to reveal the applicant's knowledge (or lack thereof). -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129424
>ISE/impact give the following error when I try to download >the BASYS bit file build in the demo project: > Connecting to cable (Usb Port - USB21). > Checking cable driver. > File version of /home/Xilinx92i/bin/lin/xusbdfwu.hex = 1030. > File version of /usr/share/xusbdfwu.hex = 1030. > libusb-driver.so version: 2008-01-20 04:17:11. > Cable connection failed. >I tried adding the 1443:0005 to ~/.libusb-driverrc but that did >not make any difference. >Any more idea? Isn't the linux usb-dl driver supposed to be used with it's own download application. Ie not with ISE/impact ..?
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