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On 2008-02-22, Antti <Antti.Lukats@googlemail.com> wrote: > whatever the supported features of Spartan3A-ICAP are, no other > spartan family has anything related to self-reconfig at all, there is > no ICAP. As a footnote I could add that I've seen a paper on a Spartan-3 based system which reconfigured itself by using the external configuration interface: http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2006/01/pdfgKQFmBlaJb.pdf /AndreasArticle: 129376
On Feb 21, 11:17 pm, austin <aus...@xilinx.com> wrote:
> Yes. For example, if you stopped the system clock, reconfigured, and
> started the clock again, that would probably work just fine.
>
> It was decided (long ago) that some features were more important to some
> customers, and since Spartan parts are concerned with: cost, cost, cost
> (in order of importance), things like reconfigurability are reserved for
> the Virtex line (where we are not so greatly constrained).
Austin,
Just for clarification - for all S3 devices partial reconfiguration is
either:
A) guaranteed to work by stopping clocks, so to avoid glitches
or
B) not supported at all, so everyone just forget it
Scenario "A" leaves for external reconfiguration, but rules out
internal one.
Article: 129377
In comp.arch.fpga,
Mike Treseler <mike_treseler@comcast.net> wrote:
> Stef wrote:
>> Placing all signals on an I/O pin is easy with the PACE tool for 'normal'
>> signals. But I can't figure out how to use a bi-directional differential
>> buffer.
>
> Your vhdl source and testbench is incomplete.
> Add code to infer and test the bidirectional buffer.
> related example:
> http://home.comcast.net/~mike_treseler/oe_demo.vhd
> Pin numbers and I/O selection is best done
> at the back end, not it the source code or simulation.
I have studied that page an came up with this:
entity bufbidir is
port (
din : out std_logic;
dout : in std_logic;
doe : in std_logic;
dpin : inout std_logic;
clock : in std_logic );
end entity bufbidir;
architecture rtl of bufbidir is
begin
bufbidir : process(clock)
variable retimein_v : std_logic;
begin
if rising_edge(clock) then
if doe = '1' then
dpin <= dout;
else
dpin <= 'Z';
end if;
din <= retimein_v;
retimein_v := dpin;
end if;
end process;
end architecture rtl;
Any good? I did leave out the reset as it will only take a few clocks
to get the final values on all signals.
This buffer has been added to my modelsim designer top-level block
diagram and I have synthesized and P&R'ed the design. This time
I opted for direct programming of the starter kit instead of
simulation. ;-)
My scope shows that this indeed created a tri-state buffer, but still
one problem left: the differential driver/receiver.
If I am correct, I should not specify anything about the differential
in my VHDL code, but just assign it differential in de Xilinx PACE
tool. But somehow, I can't select the differential option in PACE. There
are fields "Diff. Type" and "Pair Name", but those are set to "Unknown"
and "" respectively and cannot be changed.
>> Next problem is the clock input. There's a 50MHz oscillator connected to
>> a clock input and I want to use the DCM to create a 100MHz (or even a
>> 150MHz) global clock off of that.
>
> Consider leaving it at 50 Mhz for the first proto.
> PLLs and DCMs are fussy vendor-specific black boxes.
I will (and have already) do(ne) that for my first tests on the starter
kit. But on the actual proto, I will need a clock >= 100MHz inside the
fpga. So how to implement it? I was hoping for some 'magic' way to infer
it, but at the moment I see no other option than to instantiate the xilinx
primitive directly (after I figure out how to get te xilinx libs in
modelsim designer)
--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
"Computers in the future may weigh no more than 1.5 tons."
(Popular Mechanics, 1949)
Article: 129378puneetjamrani@gmail.com wrote: > Hi again, > > Actually what i currently want to do is: > 1. divide the fpga into 2 parts > a) one part will have picoblaze controller. > b) other will have an up counter. > 2. Save a partial file for down counter (generated from difference > based partial reconfiguration option) in one of the ROMs. > 3. Run the up counter initially and then using picoblaze call the > partial file from the ROM to reconfigure the UP counter to a DOWN one. > Now the BIG question:Is it possible using Spartan 3a? Can multiboot > option be used for it or any other way possible? > Or should i go for Virtex??] > > Regards, > Parunoy. Have you considered using both an up counter and a down counter and functionally selecting between the two of them?Article: 129379
Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be possible to write the GUI that doesnt self-terminate itself so often. I am trying to playback an SVF file, and it caused impact and ISE self- termination. there are possibilites to "CATCH" exceptions and recover the application, but no, Xilinx tools just terminate themself. AnttiArticle: 129380
I ran a series of posts on this: http://asicdigitaldesign.wordpress.com/2007/07/09/the-ultimate-interview-question-for-logic-design-a-mini-challenge/ http://asicdigitaldesign.wordpress.com/2008/01/24/ultimate-technical-interview-question-the-standard-solution/ http://asicdigitaldesign.wordpress.com/2008/01/31/ultimate-technical-interview-question-take-2/ hope this helps. I also have in my blog a full section on interview questions and puzzles: http://asicdigitaldesign.wordpress.com/category/interview-questions/ http://asicdigitaldesign.wordpress.com/category/puzzles/ hope this helps. NirArticle: 129381
> # Which one is superior: Asynchronous Reset or Synchronous Reset > > Well, until now I was always using asynchronous resets because u > find it in most textbooks ;) not so sure about the right answer here! Depends upon what your criteria of superior is. Cheers, JonArticle: 129382
BobW, Hspice licenses do not cost 100K, in fact they are >10X less than that amount... I apologize, but our foundries device models belong to them, and they must remain encrypted, and secret. Hspice is the only vehicle today that is available to support this (and is commonly used to do so). Are there other spice that support encryption? Sure. But they are not as common as Hspice. We have to support this for all customers, so it isn't for free. If you submit a webcase, you will get an answer from an IO specialist, if you request a Hspice result for a simulation (or two). Just be SPECIFIC. And, obviously, the IOB netlist belongs to Xilinx, and we are not interested in disclosing it to the world, so everyone who isn't able to make their 65nm process work, gets a chance to see how we did it. AustinArticle: 129383
I just reported on 3A, I would have to go ask about 3, 3E. AustinArticle: 129384
On 22 Feb., 16:35, austin <aus...@xilinx.com> wrote: > I just reported on 3A, > > I would have to go ask about 3, 3E. > > Austin no need go asking. S3A is first ever Spartan with ICAP. ditto. whatever the supported features of Spartan3A-ICAP are, no other spartan family has anything related to self-reconfig at all, there is no ICAP. AnttiArticle: 129385
On Feb 21, 2:12 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > rickman wrote: > > All I need to know is how the Lattice ispLever tool is told the order > > to compile the files. > > http://www.latticesemi.com/products/designsoftware/isplever/isplevers... > > Looks like you have the choice of Synplify or Precision. > Probably an ordered file list for these. > Check the docs. Thanks for your reply. I had already stated that I could separately invoke Synplify and get the files to compile. I can't get it to work using the Lattice IDE. I contacted the local FAE and found out that the new release from a couple of weeks ago fixes this so that user libraries work correctly. I just find it amazing that at this late date such a simple feature was not working. I wasn't told that it was broken, I think they never supported user libraries until the latest release.Article: 129386
Ok, you can ignore my question above. I did some more experimenting and it turns out I was somehow doing the post PAR simulation wrong. I think closing the project navigator software must have cleared something out because the next time I ran the simulation I got numerous timing failures that were obviously causing my problems.Article: 129387
http://www.xilinx.com/support/documentation/user_guides/ug332.pdf page 248: Tells you exactly what is supported by ICAP (and the list does not include partial reconfiguration). If you want to reconfigure to a new, or different bitstream, ICAP may be used to do that. AustinArticle: 129388
Chindgi, My translation of your original post was not off target, after all. So here is my original answer: It seems like you have the conversion of the analog sine wave to digital (AD), and conversion back again (DA) working in both VHDL, and hardware, yet you say you can not see anything on the oscilloscope? Just because you hear something in the headphones may be cross-talk (just a coincidence caused by a secondary path - parasitic coupling). First, did you simulate the design? Does the simulation test bench work? Second, are you able to input, and output static (unchanging) DC voltages? This would be my first test, before I tried AC (sine waves). If this is an issue with clocking (sampling), the DC will work, and then the AC will have issues with frequency response (just guessing). If the DC does not work, then I would use a logic analyzer (if it is Xilinx, Chipscope(tm) is soft IP that may be part of your design, and allows you to probe your digital signals inside the FPGA and see if they are what you expect in the DC case). http://www.xilinx.com/ise/optional_prod/cspro.htm Have fun, AustinArticle: 129389
On 22 Feb., 17:45, austin <aus...@xilinx.com> wrote: > http://www.xilinx.com/support/documentation/user_guides/ug332.pdf > > page 248: > > Tells you exactly what is supported by ICAP (and the list does not > include partial reconfiguration). > > If you want to reconfigure to a new, or different bitstream, ICAP may be > used to do that. > > Austin well, page 248 says "same as slave-map"... via slavemap writing bitstream on frame-by-frame basis should be possible. if the same is possible via ICAP, i would say it is partial reconfiguration ?? maybe there are reasons why it would not work properly or have side issues glitches? but it should be possible to reconfigure some cells in S3a in runtime using ICAP? AnttiArticle: 129390
On Feb 21, 3:14=A0am, puneetjamr...@gmail.com wrote: > Hi all, > > I want to know whether it is possible to program Spartan 3a for a run > time partial reconfiguration. > If yes are there any detailed demo programs available? > > Regards, > Parunoy Here is a radically different idea: Why (partial) reconfiguration? Anything you can do with reconfiguration, you can also achieve by logic duplication. Reconfiguration is just more efficient and might give higher performance. The OP seems to aim for small changes, like changing up-count to down- count. For that, reconfiguration is gross overkill. I suggest looking at the traditional solution to such designs, namely logic duplication. An up/down counter is hardly bigger than an up-counter... Peter Alfke, Xilinx ApplicationsArticle: 129391
On 22 Feb., 18:08, Peter Alfke <pe...@xilinx.com> wrote: > On Feb 21, 3:14 am, puneetjamr...@gmail.com wrote: > > > Hi all, > > > I want to know whether it is possible to program Spartan 3a for a run > > time partial reconfiguration. > > If yes are there any detailed demo programs available? > > > Regards, > > Parunoy > > Here is a radically different idea: > Why (partial) reconfiguration? > Anything you can do with reconfiguration, you can also achieve by > logic duplication. Reconfiguration is just more efficient and might > give higher performance. > The OP seems to aim for small changes, like changing up-count to down- > count. For that, reconfiguration is gross overkill. > I suggest looking at the traditional solution to such designs, namely > logic duplication. > An up/down counter is hardly bigger than an up-counter... > Peter Alfke, Xilinx Applications sure, the OP was maybe barking under wrong tree. the topic itself is still interesting, if I have some soft-core say in right half of the die and if i want to change the PULLUP to PULLDOWN on the left side of the die I would assume this could be done by S3A ICAP ??? most MCU's can have pullup control in software, FPGA's have that control only via configuration, I could see S3A adds at least partially this possibilty or is there some thing that prevents such runtime reconfig? AnttiArticle: 129392
rickman wrote:
> Thanks for your reply. I had already stated that I could separately
> invoke Synplify and get the files to compile.
Sorry, I missed that.
> I can't get it to work using the Lattice IDE.
The device vendors all try to package their
collections of front and back end tools with
with a gui wrapper for demos and examples.
None of these stand up to serious use.
I am always better off doing the front end
and simulation from my favorite editor,
and the pin numbers and timing
with the place and route tool.
-- Mike Treseler
Article: 129393Possible, Yes. Supported, No. 'Play' all you like, but it is unsupported. If it does something useful for you, great. But, as an unsupported feature, we have no obligation to provide it (it might go away, doubtful, but a possibility if we change something to fix something else, if something needs fixing -- or if we cost reduce something to reduce costs). The pdf lists the supported features. Reprogramming live is noticeably absent. AustinArticle: 129394
On Feb 22, 9:16=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On 22 Feb., 18:08, Peter Alfke <pe...@xilinx.com> wrote: > > > > > On Feb 21, 3:14 am, puneetjamr...@gmail.com wrote: > > > > Hi all, > > > > I want to know whether it is possible to program Spartan 3a for a run > > > time partial reconfiguration. > > > If yes are there any detailed demo programs available? > > > > Regards, > > > Parunoy > > > Here is a radically different idea: > > Why (partial) reconfiguration? > > Anything you can do with reconfiguration, you can also achieve by > > logic duplication. Reconfiguration is just more efficient and might > > give higher performance. > > The OP seems to aim for small changes, like changing up-count to down- > > count. For that, reconfiguration is gross =A0overkill. > > I suggest looking at the traditional solution to such designs, namely > > logic duplication. > > An up/down counter is hardly bigger than an up-counter... > > Peter Alfke, Xilinx Applications > > sure, the OP was maybe barking under wrong tree. > > the topic itself is still interesting, if I have some soft-core say in > right half of the die > and if i want to change the PULLUP to PULLDOWN on the left side of the > die > > I would assume this could be done by S3A ICAP ??? > > most MCU's can have pullup control in software, FPGA's have that > control > only via configuration, I could see S3A adds at least partially this > possibilty > or is there some thing that prevents such runtime reconfig? > > Antti Antti, in partial reconfiguration (as in many things) the devil is in the details. Partial reconfiguration can inherently change only one frame at a time. In Virtex, the change is guaranteed to be glitchless (no erroneous codes), but in Spartan there will be glitches =3D erroneous codes. If you stop the clock, these glitches will probably (?) not cause any harm... If Xilinx were to support such a feature in Spartan, there would be so many "ifs and buts" that we would would perhaps make some designers happy, but definitely alienate others. So we decided not to support this feature in Spartan. Use Virtex if you need partial reconfiguration... PeterArticle: 129395
Hi Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF files: For first testing i used Xilinx IMPACT as SVF playback engine, and I got scan data mismatch error on any actel SVF files then i used my own SVF player and got same result (JTAG port and Actel FPGA connections are ok, my own software can identify chain ok) when looking into the Actel tools generated SVF ==================================== FREQUENCY 4E6 HZ; STATE RESET; RUNTEST IDLE 5 TCK; ENDIR IRPAUSE; ENDDR DRPAUSE; SIR 8 TDI(0F); SDR 32 TDI(00000000); STATE IDLE; RUNTEST IDLE 1 TCK; SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); ==================================== that SVF set IR to IDCODE (0F) clocks out 32 bits without using return data then without shifting anything to IR will go again shiftDR and try read IDCODE strange, while impact NEVER sees correct IDCODE readback, my own SVF player sometimes see the IDCODE returned on the second DR shift (never on first) AnttiArticle: 129396
On 22 Feb., 19:10, Peter Alfke <pe...@xilinx.com> wrote: > On Feb 22, 9:16 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 22 Feb., 18:08, Peter Alfke <pe...@xilinx.com> wrote: > > > > On Feb 21, 3:14 am, puneetjamr...@gmail.com wrote: > > > > > Hi all, > > > > > I want to know whether it is possible to program Spartan 3a for a run > > > > time partial reconfiguration. > > > > If yes are there any detailed demo programs available? > > > > > Regards, > > > > Parunoy > > > > Here is a radically different idea: > > > Why (partial) reconfiguration? > > > Anything you can do with reconfiguration, you can also achieve by > > > logic duplication. Reconfiguration is just more efficient and might > > > give higher performance. > > > The OP seems to aim for small changes, like changing up-count to down- > > > count. For that, reconfiguration is gross overkill. > > > I suggest looking at the traditional solution to such designs, namely > > > logic duplication. > > > An up/down counter is hardly bigger than an up-counter... > > > Peter Alfke, Xilinx Applications > > > sure, the OP was maybe barking under wrong tree. > > > the topic itself is still interesting, if I have some soft-core say in > > right half of the die > > and if i want to change the PULLUP to PULLDOWN on the left side of the > > die > > > I would assume this could be done by S3A ICAP ??? > > > most MCU's can have pullup control in software, FPGA's have that > > control > > only via configuration, I could see S3A adds at least partially this > > possibilty > > or is there some thing that prevents such runtime reconfig? > > > Antti > > Antti, in partial reconfiguration (as in many things) the devil is in > the details. Partial reconfiguration can inherently change only one > frame at a time. In Virtex, the change is guaranteed to be glitchless > (no erroneous codes), but in Spartan there will be glitches = > erroneous codes. > If you stop the clock, these glitches will probably (?) not cause any > harm... > > If Xilinx were to support such a feature in Spartan, there would be so > many "ifs and buts" that we would would perhaps make some designers > happy, but definitely alienate others. So we decided not to support > this feature in Spartan. Use Virtex if you need partial > reconfiguration... > Peter LOL, i may wanna want to support features available in Xilinx silicon that useable in some given application. If I have such application I may also do some reconfig in S3A, not matter it is officially supported. But agreed, what is not officially supported is no on the recommended list of things to be done. right. Antti to Peter, I have an application where even glitchy reconfig could be VERY useable in S3, the project is on ice right now, but i may get it active some dayArticle: 129397
On 22 Feb., 19:20, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > Since version 8.1 Actel provides SVF programming file generation for > A3 FPGA's but I have problems using those SVF files: > > For first testing i used Xilinx IMPACT as SVF playback engine, and I > got scan data mismatch error on any actel SVF files > > then i used my own SVF player and got same result > > (JTAG port and Actel FPGA connections are ok, my own software can > identify chain ok) > > when looking into the Actel tools generated SVF > ==================================== > FREQUENCY 4E6 HZ; > STATE RESET; > RUNTEST IDLE 5 TCK; > ENDIR IRPAUSE; > ENDDR DRPAUSE; > SIR 8 TDI(0F); > SDR 32 TDI(00000000); > STATE IDLE; > RUNTEST IDLE 1 TCK; > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF); > ==================================== > > that SVF set IR to IDCODE (0F) > clocks out 32 bits without using return data > then without shifting anything to IR will go again shiftDR and try > read IDCODE > > strange, while impact NEVER sees correct IDCODE readback, my own SVF > player > sometimes see the IDCODE returned on the second DR shift (never on > first) > > Antti issue solved, my own SVF player does verify the A3 IDCODE correctly when playing back actel generated SVF AnttiArticle: 129398
On Feb 21, 10:33 pm, Clemens Blank <CBl...@hotmail.com> wrote: > Clemens Blank schrieb: > > > Interview questions > > and the best one I came across was to double the clock frequency. How on > earth should this be possible, must be a trap! An easy answer is to use a DCM in Virtex FPGA ... :-) haha details, as said, PLL and DLL...Article: 129399
On Feb 22, 6:52 pm, "jack.harv...@googlemail.com" <jack.harv...@googlemail.com> wrote: > On Feb 21, 10:33 pm, Clemens Blank <CBl...@hotmail.com> wrote: > > > Clemens Blank schrieb: > > > > Interview questions > > > and the best one I came across was to double the clock frequency. How on > > earth should this be possible, must be a trap! > > An easy answer is to use a DCM in Virtex FPGA ... :-) haha > details, as said, PLL and DLL... Another interesting question I read from a newspaper yesterday, how to get more than 10% gain if share prices increase by 10%?
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