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Hi, i am configurating the PLL of my FPGA board to achieve a higher frequency. The master clock frequency of it is at 100 MHz. I am trying to divide it to attain 800 MHz. May i know is this possible, since i am able to divide it in the PLL configuration? However, my output is distorted. May i know if this is due to the PLL configuration limit (unable to divide more than 4) or due to my oscilloscope? Please advise. Thank you.Article: 129451
Hi all. I have recently downloaded the driver files in order to do hardware cosim on a ML501 Evaluation kit but I do not know how to unzip n install it to Sysgen I have heard it is a certain command in Matlab command window to invoke the installation so that I can do hardware cosim on the ML501. But finding the command, I have no luck. I would appreciate any help. Thank you in advance. Regards.Article: 129452
<MikeShepherd564@btinternet.com> wrote in message news:ke4rr3dvhavb3jhsaquskh3a8ceedsgtok@4ax.com... > >The NiosII blurb says that it can implement a single instruction >>32 bit multiply or divide. >>I wonder what sort of architecture they're using? > What's unusual about a single instruction multiply or divide? Surely > it's just a question of writing the microcode to do it. > Mike Ah ha, that was me with my hardware head on (I don't have another one) reading single instruction as single clock! :-( NialArticle: 129453
On Feb 24, 8:53 pm, PatC <p...@patocarr.com> wrote: > Bob Smith wrote: > > JK wrote: > >> your DCM is missing reset, if I am not wrong. > >> I dont see any reset on your top level port list. > >> You are getting clkout2, because it is not depending on reset. > > > Thanks for the suggestion. I added a reset from a switch on the > > board. A reset does not seem to make any difference. > > > PatC wrote: > >> Have you checked the locked output? if it's not locked, FX would not > >> output anything iirc, as opposed to clk0 which does regardless of lock. > > > Thanks for the suggestion. I tied an LED on the board to the > > locked status output. The locked status never goes high (perhaps > > as you suspected). Any ideas why it won't lock? > > Since your code sample is snipped, I don't see the BUFG connecting clk0 > to clkfb. If you are using clock feedback 1x, this is how it should be > connected. Without this feedback, it won't lock. > > -P@ When using the DCM for frequency synthesis only you are correct in saying that you don't need to feedback a signal and setting CLK_FEEDBACK to NONE is the right thing to do. I've succesfully used this configuration myself. Strange that the output is at 2V, is this the IO voltage for that bank? If you haven't already done so, i suggest you try and simulate the design, as this may give some clue as to what is going on. Without a RST input you also need to be careful that the clock is running and stable before configuration. Any change in the input clock requires RST to be asserted. I'm also not sure that the LOCKED pin should go high, since the datasheet states that this is asserted when CLKIN and CLKFB are in phase, which of course will never happen in this configuration. Cheers RobArticle: 129454
In comp.arch.fpga,
Mike Treseler <mike_treseler@comcast.net> wrote:
>
> Yes. It might make sense to have
> one design entity that converts the processor tristate
> data bus to separate read and write data buses
> on the fpga.
Yes. This is the design I have in mind (simplified)
CPUwrite ==> Mem ==> Processing ==> Serializer
// \
<==> BusInt SerInt <-->
\\ /
CPUread <== Mem <== Processing <== Deserializer
> Good luck.
Thank you, and thank you for your help sofar.
--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)
"Computers in the future may weigh no more than 1.5 tons."
(Popular Mechanics, 1949)
Article: 129455auguste.chindji@googlemail.com <auguste.chindji@googlemail.com> wrote: > Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz) > I can hear something (signal) at the output (by the DA converter) > with the > Headphones. However, I cannot measure it with the oscilloscope. Why? If you don't have an oscilloscope, try the poor man logic analyzer: http://www.sump.org/projects/analyzer/ or (in german) http://de.sump.org/projects/analyzer/ It can also display "digital" waveforms. regards, BartArticle: 129456
Hello Guys, I found an interesting website at www.calculatoredge.com an online engineering calculator for formula and equations you can solve at click of a button, If you like this website send links to your friends and engineering group members. TomArticle: 129457
Hi all, it has been silent about JOP in this group for a while. However, development is still very active. I've now decided to put the project under GPL v3. For those who don't know the project: JOP is an implementation of the Java virtual machine in hardware - that means a Java processor. It's not the only Java processor in the world, but now the first one under GPL ;-) If you want to browse the project: the sources are at opencores [1], there are two web sites [2, 3], and a handbook [4] available. Cheers, Martin [1] http://www.opencores.org/projects.cgi/web/jop/overview [2] http://www.jopdesign.com/ [3] http://www.jopwiki.com/ [4] http://www.jopdesign.com/doc/handbook.pdfArticle: 129458
>Hello Guys, > >I found an interesting website at www.calculatoredge.com an online >engineering calculator for formula and equations you can solve at >click of a button, If you like this website send links to your >friends and engineering group members. > >Tom You "found" an interesting web site and your e-mail address just happens to be based on the the same name?Article: 129459
I would like to know how the initialisation of seed values would affect the output of the procedure of UNIFORM. I have looked at UNIFORM but I am not able to understand the significance of the seed values. I have written a process to generate random signed vectors. In my case, i specify that the random number be in range min and max. When I change the seed values, I still get the same sequence of random numbers. I am not sure if this is how it should behave. All I have done is converted the real to signed using rand <= toSigned((real(min) + (rand1 * (real(max)-real(min))); How do I simulate this process. I am getting random numbers, but I would like to write a test bench which would check for all possible scenarios and worst cases. Thanks in advanceArticle: 129460
Hi,
I wasn't very satisfied with the available assembler, so a few month
ago I wrote a new compiler for the Picobaze during my spare
weekends ...
I just though I'd share it if anyone is interested ....
It's available there :
http://www.246tnt.com/files/PBAsm_20080225.tar.bz2
Example usage:
python ./Codegen.py example.S out.mem
WARNING: The last file on the command line is the output ... so if you
forget it, it will overwrite your last source file ...
What are the pro and cons:
pros:
- Cross platform
- It supports local label, so for labels that don't really deserve a
name you can do things like
load s0, 15
1:
sub s0, 1
jump nz, 1b
And the '1b' reference says to find the first label named 1 when
going 'back' (1f would be forward...).
Local labels are just a single digit.
- It supports initialized data, and reference to the "data" sections.
Like
.data
var1: .byte 0xa5
.text
load s0, var1
fetch s0, (s0)
- It supports evaluating expression like "load s0, 15 / 5 * 8"
- It supports some advanced hw feature not in the original picoblaze
like offset during fetches / store / input / output :
fetch s0, (s1)8
equivalent to
add s1, 8
fetch s0, (s1)
sub s1, 8
but in 1 cycle and at no hw cost ... (just need to change a LUT3 to a
LUT4 and change it's INIT string)
cons:
- Incompatible syntax with the official one ...
- I haven't tested interrupt stuff
- The registers are now s0 -> s15 and not s0 -> sF ... (easier to
parse)
- To use all the features you need a hw modified picoblaze
- It has terrible error reporting ... basically just throws an
exception with a not always helpful message.
It could use cleanup, an optimizer, a C front-end, a macro
preprocessor .... but ... it works :)
About the hw mods to the hw :
- I removed the ScratchPad distributed RAM and used the second port
on the BRAM as scratch pad. The second port is configured as 8 bit
width and with upper address lines mapped to 1 so that the SP is
located at the end of the BRAM. (Be careful when playing with this and
interruptions, the last 2 bytes of the scratch pad is the interrupt
vector ...) And the bonus is a 256 byte scratch pad, just sacrificing
128 instruction words ... (adjust mapping for other tradeoffs)
This mod is not absolutely needed. But if you want to use the pre-
initialized memory without it, you'll have to change the main function
to output two independent .mem file instead of just 1 merged one ...
(pretty easy, juste look at the end of CodeGen.py )
- I changed a lut to allow for having an offset in fetch/store/input/
output ... I can post the exact patch if it's to interest to anyone.
(I don't have it handy right here ...) But it doesn't cost any
slice ... It might prolong the critical path a bit. But for me, the
critical path was somewhere else anyway so I didn't mind ...
Sylvain
Article: 129461Hi everybody, I have successfully integrated the ICAP driver to our Linux on the PPC on the ML310 board. But now I had a problem about the ICAP driver. My combinational circuits, such as the very simple adder design and the subtractor design, can successfully be partially reconfigured by the ICAP driver, but the sequential circuit cannot be. Are there any things that I have to consider, such the hardware design? Thanks! Best regards, HuangArticle: 129462
> - Cross platform I forgot to say you need Python and also the Ply (Python Lex Yacc) library ...Article: 129463
Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx parallel 3 cable not Parallel 4 cable. Is it possible to configure spartan3e with Parallel cable 3 through the parallel cable 4 header? Thanks. -AravindArticle: 129464
On Feb 24, 7:11 pm, Fei Liu <fei....@gmail.com> wrote: > jkljljklk wrote: > >> Hello Dan, my board is S3A described in ug330.pdf. In ug330.pdf Fig 2-1 > >> there is no SW7. Also I have no idea how to control it, do I have to > >> manually push it up and down? I have 4 push button switch T14,15,16 and > >> U15 in Fig 2-5. > > >> The quick start tutorial in qst.pdf uses a S3 board. > > >> Fei > > > Yes, you have to control the switches and pushbuttons on the board > > manually. > > I see, many thanks. I guess I can use either of the manual switch to > control DIRECTION. One thing I don't understand is that the clock is > 50MHz and my timing constraints is only a few macro seconds. I wonder > how I can control DIRECTION that fast by manually pushing the switch. > > Fei That constraint doesn't mean that you will be switching at that rate, it only defines the maximum rate.Article: 129465
FPGA WITH NO NAME (I prefer to talk to humans), > I would like to know how the initialisation of seed values would > affect the output of the procedure of UNIFORM. I have looked at > UNIFORM but I am not able to understand the significance of the seed > values. > I have written a process to generate random signed vectors. In my > case, i specify that the random number be in range min and max. > When I change the seed values, I still get the same sequence of random > numbers. I am not sure if this is how it should behave. You should be getting a different sequence. Did you do all of your process steps (save file, recompile, re-run simulation)? Is there a bug in your scaling process? Just for fun, write a test program that loops while generating random values. How many times does it need to loop before all values are generated? After going through your loop n times where n = range of values, how many values are not covered? I usually track this in an array. > All I have done is converted the real to signed using rand <= > toSigned((real(min) + (rand1 * (real(max)-real(min))); This looks ok other than toSigned. I use ieee.nummeric_std.to_signed I am not sure where toSigned comes from. > How do I simulate this process. I am getting random numbers, but I > would like to write a test bench which would check for all possible > scenarios and worst cases. There is the fun stuff. You will have to enumerate what these are and write code to track them. For help you will need to be more specific. Cheers, JimArticle: 129466
On Feb 25, 8:11=A0am, aravind <aramos...@gmail.com> wrote: > Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx > parallel 3 cable not Parallel 4 cable. Is it possible to configure > spartan3e with Parallel cable 3 through the parallel cable 4 header? > Thanks. > > -Aravind You have a direct correlation between the signals on the programming connector and the signals on the Parallel cable 3, except... The Parallel cable 3 hooks up to the PC's parallel port directly without any power beyond that supplied by the programming interface. Since the parallel port needs TTL levels, powering the Parallel cable 3 with the 2.5V on the Darnaw1 module won't provide a reliable interface. If you connect the Parallel cable 3's VCC to a 3.3V connection instead, you should get reliable programming without concern for damage. Personally, I've sincerely appreciated the ease of the Xilinx USB programming cable where the parallel port is powered through the USB (it's from an external supply or keyboard through-connector on the Parallel 4) and the VCC is actually a VREF of sorts, allowing a 2.5V powered programming interface as easily as a 1.8V or 5V interface. When I had my Parallel 3 hooked up to 2.5V, my results were poor. At 3.3V, my 2.5V programming interface worked fine. I purchased the USB programming cable the next week. - John_HArticle: 129467
On 25 Feb., 17:11, aravind <aramos...@gmail.com> wrote:
> Hi, I just purchased Enterpoint's Darnaw1 module. I have Xilinx
> parallel 3 cable not Parallel 4 cable. Is it possible to configure
> spartan3e with Parallel cable 3 through the parallel cable 4 header?
> Thanks.
>
> -Aravind
yes, it still should work. Xilinx has officially dropped Cable III
support
but so far the SW still can work with cable III too
Antti
From puiterl@notaimvalley.nl Mon Feb 25 09:07:31 2008
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Message-Id: <47c2f5d3$0$14346$e4fe514c@news.xs4all.nl>
From: Paul Uiterlinden <puiterl@notaimvalley.nl>
Subject: Re: Seed Values
Newsgroups: comp.arch.fpga,comp.lang.vhdl
Followup-To: comp.arch.fpga
Date: Mon, 25 Feb 2008 18:07:31 +0100
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FPGA wrote:
> I would like to know how the initialisation of seed values would
> affect the output of the procedure of UNIFORM. I have looked at
> UNIFORM but I am not able to understand the significance of the seed
> values.
You initialize the seed values once. After that, they are modified by the
calls to uniform. You should not change the seed values anymore. Unless you
want to repeat the generated random values. Because that is what the seed
value guarantees: initialize them with the same values as before, and
uniform will generate the exact same numbers as before.
> I have written a process to generate random signed vectors. In my
> case, i specify that the random number be in range min and max.
> When I change the seed values, I still get the same sequence of random
> numbers.
Are you sure?
> I am not sure if this is how it should behave.
> All I have done is converted the real to signed using rand <=
> toSigned((real(min) + (rand1 * (real(max)-real(min)));
> How do I simulate this process. I am getting random numbers, but I
> would like to write a test bench which would check for all possible
> scenarios and worst cases.
Something like:
use std.textio.all;
...
process is
variable l: line;
variable rand : integer; (or signed())
variable seed1, seed2: integer;
begin
seed1 := 123;
seed2 := 5678;
for i in 1 to 1000 loop
rand := your random function, calling uniform()
write(l, rand);
writeline(output, l);
end loop;
wait;
end process;
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Article: 129468Gents, Saw this thread go by on my alert list and wanted to check in. From the perspective of the synthesis and simulator, the Project Navigator's job is to supply an ordered file list, command line flags, and in some cases a script to automate a run. There is no user- defined file order 7.0. It will attempt to build an ordered file list automatically. I have seen some VHDL designs fail under 7.0 that requires Service Pack 2 to correct. If all else fails, manage HDL source from within Synplify or Precision and create an EDIF-based ispLEVER project. It's accurate to say Project Navigator has some non-standard conventions for HDL file management. I blame it partially because system has a long history of managing all sorts of non-HDL file formats like schematic, ABEL, and the native Lattice parameter constraints file (LPC) created by IPexpress. Under the hood 7.0 is a big improvement over 6.x, it has far better capacity, performance, and language compliance when dealing with long file lists. It also supports mixing VHDL and Verilog. We are working on this area to make it closer to the conventions you'd find in other EDA tools. Troy Scott Software Marketing Lattice Semiconductor CorporationArticle: 129469
On Feb 25, 11:41=A0am, Jim Lewis <j...@synthworks.com> wrote: > FPGA WITH NO NAME (I prefer to talk to humans),> I would like to know how = the initialisation of seed values would > > affect the output of the procedure of UNIFORM. I have looked at > > UNIFORM but I am not able to understand the significance of the seed > > values. > > I have written a process to generate random signed vectors. In my > > case, i specify that the random number be in range min and max. > > When I change the seed values, I still get the same sequence of random > > numbers. I am not sure if this is how it should behave. > > You should be getting a different sequence. =A0Did you do all of your > process steps (save file, recompile, re-run simulation)? > Is there a bug in your scaling process? I have saved, recompiled and rerun simulation. The strange thing is, I am getting the same sequence if I output uniform in real format even after I change the initialisation of Seed1 and Seed2. uniform(S1,S2,rand1); rand_real <=3D rand1; I am not sure why this is happening. SEED1 <=3D 10;--1 ; SEED2 <=3D 20;--2147483647 ; > > Just for fun, write a test program that loops while generating random valu= es. > How many times does it need to loop before all values are generated? > After going through your loop n times where n =3D range of values, > how many values are not covered? =A0I usually track this in an array. > > =A0> All I have done is converted the real to signed using rand <=3D > =A0> toSigned((real(min) + (rand1 * (real(max)-real(min))); > This looks ok other than toSigned. =A0I use ieee.nummeric_std.to_signed > I am not sure where toSigned comes from. toSigned converts real to signed of specified bw. I dont see any problem with toSigned. > > > How do I simulate this process. I am getting random numbers, but I > > would like to write a test bench which would check for all possible > > scenarios and worst cases. > > There is the fun stuff. =A0You will have to enumerate what these are and > write code to track them. =A0For help you will need to be more specific. I am dealing with someone who himself doesnt know what he wants. I would just like to write smthg to prove that it works correctly, nothing very particular. > > Cheers, > JimArticle: 129470
On Feb 25, 12:07=A0pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote: > FPGA wrote: > > I would like to know how the initialisation of seed values would > > affect the output of the procedure of UNIFORM. I have looked at > > UNIFORM but I am not able to understand the significance of the seed > > values. > > You initialize the seed values once. After that, they are modified by the > calls to uniform. You should not change the seed values anymore. Unless yo= u > want to repeat the generated random values. Because that is what the seed > value guarantees: initialize them with the same values as before, and > uniform will generate the exact same numbers as before. > > > I have written a process to generate random signed vectors. In my > > case, i specify that the random number be in range min and max. > > When I change the seed values, I still get the same sequence of random > > numbers. > > Are you sure? I am very sure. I my top level, I have defined SEED1 and SEED2 (of type positive) as signals and then assigned them to S1 , S2 of type positive. > > > I am not sure if this is how it should behave. > > All I have done is converted the real to signed using rand <=3D > > toSigned((real(min) + (rand1 * (real(max)-real(min))); > > How do I simulate this process. I am getting random numbers, but I > > would like to write a test bench which would check for all possible > > scenarios and worst cases. > > Something like: > > =A0 use std.textio.all; > =A0 ... > =A0 process is > =A0 =A0 variable l: line; > =A0 =A0 variable rand : integer; (or signed()) > =A0 =A0 variable seed1, seed2: integer; > =A0 begin > =A0 =A0 seed1 :=3D 123; > =A0 =A0 seed2 :=3D 5678; > =A0 =A0 for i in 1 to 1000 loop > =A0 =A0 =A0 rand :=3D your random function, calling uniform() > =A0 =A0 =A0 write(l, rand); > =A0 =A0 =A0 writeline(output, l); > =A0 =A0 end loop; > =A0 =A0 wait; > =A0 end process; > > -- > Paul Uiterlindenwww.aimvalley.nl > e-mail addres: remove the not.Article: 129471
On Feb 25, 12:07=A0pm, Paul Uiterlinden <puit...@notaimvalley.nl> wrote: > FPGA wrote: > > I would like to know how the initialisation of seed values would > > affect the output of the procedure of UNIFORM. I have looked at > > UNIFORM but I am not able to understand the significance of the seed > > values. > > You initialize the seed values once. After that, they are modified by the > calls to uniform. You should not change the seed values anymore. Unless yo= u > want to repeat the generated random values. Because that is what the seed > value guarantees: initialize them with the same values as before, and > uniform will generate the exact same numbers as before. > > > I have written a process to generate random signed vectors. In my > > case, i specify that the random number be in range min and max. > > When I change the seed values, I still get the same sequence of random > > numbers. > > Are you sure? > > > I am not sure if this is how it should behave. > > All I have done is converted the real to signed using rand <=3D > > toSigned((real(min) + (rand1 * (real(max)-real(min))); > > How do I simulate this process. I am getting random numbers, but I > > would like to write a test bench which would check for all possible > > scenarios and worst cases. > > Something like: > > =A0 use std.textio.all; > =A0 ... > =A0 process is > =A0 =A0 variable l: line; > =A0 =A0 variable rand : integer; (or signed()) > =A0 =A0 variable seed1, seed2: integer; > =A0 begin > =A0 =A0 seed1 :=3D 123; > =A0 =A0 seed2 :=3D 5678; > =A0 =A0 for i in 1 to 1000 loop > =A0 =A0 =A0 rand :=3D your random function, calling uniform() > =A0 =A0 =A0 write(l, rand); > =A0 =A0 =A0 writeline(output, l); > =A0 =A0 end loop; > =A0 =A0 wait; > =A0 end process; > > -- > Paul Uiterlindenwww.aimvalley.nl > e-mail addres: remove the not. I just commented my signals SEED1,SEED2 in the top level. I initialised the values of SEED1, SEED2 within the process (not taking as signal inputs as before). Now, I see that I am getting different sequence for different values of SEED1, SEED2. Why would this happen? Shouldnt it behave the same if I have SEED1, SEED2 as signals and then within process I have variable S1,S2 initialised to signal SEED1, SEED2 I dont understand why it behaves so.Article: 129472
troy.scott@latticesemi.com wrote:
> There is no user-
> defined file order 7.0. It will attempt to build an ordered file list
> automatically. I have seen some VHDL designs fail under 7.0 that
> requires Service Pack 2 to correct.
This is a hard problem for vhdl even with a single work library.
I would recommend letting the user edit the order you come up with.
Otherwise, the trial-and-error method (which always works) is ruled out.
> We are working on this area to make it closer to the conventions you'd
> find in other EDA tools.
Don't stop trying, but note that I wasn't picking on Lattice.
I don't think any device vendor has
a front end that can do it all for complex projects.
-- Mike Treseler
Article: 129473
FPGA wrote:
> I dont understand why it behaves so.
Variables update immediately.
Signals don't update until they see a wait.
-- Mike Treseler
Article: 129474Hello Pat, We have seen similar map issues in the past when sending large amounts of LOC constraints via a UCF file to ISE. We've made some improvements in both 10.1 ISE and PlanAhead to address them. Rather than just passing LOC constraints, we've seen a much better success rate when passing both LOC and BEL constraints. Therefore, in 10.1 release of PlanAhead, we've defaulted both the Export IP and Export Pblock commands to include both types of constraints in the UCF. The map group has also fixed quite a few of these types of logic packing scenarios that cause packing failures. I'm not sure what version of PlanAhead you are using, but the latest 9.2 versions will output BEL constraints. If you are using 9.2, we'd like to try it using 10.1 PlanAehad and ISE. It would be helpful if you could file a bug against PlanAhead with the design data. If we duplicate it here, it will be filed as a bug against the map tool. The other option is to strip out the 105 lines in question from the UCF file. We find that the mapper with usually just put them back in the same locations anyhow??? Please fell free to contact me directly to help resolve the issue. Brian Jackson Marketing Manager, Xilinx 720-652-3102 On Feb 23, 10:17=A0am, PatC <p...@patocarr.com> wrote: > Hi, > > I'm trying to insert an IP core generated by PlanAhead into our > script-based flow, but map fails with Pack:679 error on several slices. > > The IP in question is a wrapper around the PCIe block plus, that > contains our DMA engine. This component is pretty big and we decided to > lock it down when we deliver the sources to our customers. Using > PlanAhead, we intend to floorplan it tightly and lock its placement so > the customer won't have timing issues. > > The exported IP is in the edn/ucf form, and it's imported into our xst > flow without problems. I gutted the top level of the component and made > it a black box. Xst and ngdbuild run without problems. Both transform > the edn into an ngo. I also concatenated the system ucf to the component > ucf and fixed the relative paths. > > Map fails with 105 error 679, and over 3 thousand warnings (some > expected). Different runs give different results though. > > "Unable to obey design constraints (LOC=3DSLICE_X46Y115) which require the= > combination of the following symbols into a single SLICEL component" > ... (snip - see below) > "The clock enable signals don't agree. Please correct the design > constraints accordingly." > > Looking at the SLICEL in PlanAhead, I see six symbols (3 LUTs, 3 FLOPs) > and a seventh one that doesn't seem related to the others. Perhaps this > is the one "clock enable" referred to in the error message. > > Also, doubting of the import-into-my-flow procedure, I made another PA > project, where I import this same IP into the netlist, and it fails with > the same errors. > > Has anybody seen this error? The answer records show some similar > errors, but no explanation on how to work around it/fix it. > > Thanks in advance, > -Pat > > Error Message: > ------------------------------ > ERROR:Pack:679 - Unable to obey design constraints (LOC=3DSLICE_X46Y115) > which require the combination of the following symbols into a single > SLICEL component: > LUT symbol > "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00= 0=AD03 > 11" (Output Signal =3D > ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[8])= > LUT symbol > "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_60_mux00= 0=AD03 > 21" (Output Signal =3D > ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_mux0000[9])= > LUT symbol > "ii_pci_express_interface/application_reg_file/mmux_ctl_reg_o_sig_62_mux00= 0=AD03 > 11" (Output Signal =3D > ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_mux0000[8])= > FLOP symbol > "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_8" (Output= > Signal =3D ctl_reg<;60><;8>) > FLOP symbol > "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_60_9" (Output= > Signal =3D ctl_reg<;60><;9>) > FLOP symbol > "ii_pci_express_interface/application_reg_file/ctl_reg_o_sig_62_8" (Output= > Signal =3D ctl_reg<;62><;8>) > The clock enable signals don't agree. Please correct the design > constraints accordingly.
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