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Jonathan Bromley wrote: > On Fri, 25 Jan 2008 06:44:10 -0800 (PST), > Ann <thakkar.anuja@gmail.com> wrote: > > >>I just found out that I need random number generator just for >>simulation. I do not need to synthesize it. Some feedback on this >>would be helpful. I am having a look at some of the links posted here. > > > OK, that's easy. The math_real package contains an excellent > random number generator that you can adapt for your own purposes. > > use ieee.math_real.all; > ... > process > variable R: real; > variable S1, S2: positive := 42; > --- seed variables, change initialization to > --- get a different random number stream > begin > ... > uniform(S1, S2, R); > ... > That's great for testbenching, but it isn't helpful for implementation in an FPGA.Article: 129326
glen herrmannsfeldt wrote: > FPGA wrote: > >> I would like to know if VHDL already has functions defined to generate >> Random Numbers. > > >> If not, which would be the best algorithm for generating random >> numbers for implementation on an FPGA. > > > LFSR are pretty popular for random numbers, and very easy to > implement in an FPGA. > > -- glen > LFSRs are fine for a psuedo-random sequence. If it needs to be truely random however (such as with crypto), an LFSR is not suitable because the output is predictable given the history. If you do use an LFSR, take only one bit per clock of the LFSR, as the bits are highly correlated in the shift register. My former employee, Jennifer Brady (who did much of the algorithm work for my ultra-fast FFT core), recently finished her master's thesis on random number generation in FPGAs. I know she looked at distribution as well as randomness in her study. I don't have her conclusions or dissertation, but I have asked her to chime in here.Article: 129327
Mikhail, Only in terms of the number of paralleled output devices selected. If you wish 8 mA min drive at 2.5v Vcco, the number of drivers will be stronger than that at 3.0, or 3.3 v. Conversely, if 8mA is selected for 3.3v, it will be weaker at 3.0 or 2.5v. The hspice models on the website will predict actual results from real silicon, whereas the IBIS models do not allow for changing Vcco. Regardless, simulating 8 mA at 3.3v slow/weak corner in IBIS will give you some idea of what the typical will be with 3.0 volts. A 10% change in Vcco is roughly the same as the difference from slow/weak to typical, or typical to fast/strong(in IBIS). Austin AustinArticle: 129328
On Feb 20, 3:40=A0pm, Jan Pech <inva...@void.domain> wrote:
> On Wed, 2008-02-20 at 01:45 -0800, MAx wrote:
> > Hi,
> > =A0 =A0 =A0 How to read an integer from hyperterminal onto a microbaze u=
sing
> > EDK 9.1i.
> > Im trying it using scanf but its giving me errors.
>
> > =A0 =A0 =A0 here are the lines of code im trying to achieve the read.
>
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 scanf("%d",&var);
> > =A0 =A0xil_print("\r\n Entered %d \r\n",var);
>
> > =A0 =A0 =A0 I get the following errors,
>
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0At Local date and time: Wed Feb 20 15=
:08:33 2008
> > =A0xbash -q -c "cd /cygdrive/d/SCANF/; /usr/bin/make -f system.make
> > TestApp_Memory_program; exit;" started...
> > mb-gcc -O2 TestApp_Memory/src/TestApp_Memory.c =A0-o TestApp_Memory/
> > executable.elf \
> > =A0 =A0 -mno-xl-soft-mul -mxl-pattern-compare -mcpu=3Dv6.00.a =A0-Wl,-T =
-
> > Wl,TestApp_Memory/src/TestApp_Memory_LinkScr.ld =A0-g =A0 =A0-I./
> > microblaze_0/include/ =A0-L./microblaze_0/lib/ =A0\
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
> > is full (TestApp_Memory/executable.elf section .text)
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
> > is full (TestApp_Memory/executable.elf section .text)
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .init [00000050 ->
> > 00000077] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .fini [00000078 ->
> > 00000093] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000094 ->
> > 00000cdf] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .data [00000ce0 ->
> > 000013ff] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .ctors [00001400 ->
> > 00001407] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .dtors [00001408 ->
> > 0000140f] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> > 3.4.1/../../../../microblaze/bin/ld.real: section .jcr [00001410 ->
> > 00001413] overlaps section .text [00000050 -> 00010293]
>
> > /cygdrive/c/DOCUME~1/ADMINI~1/LOCALS~1/Temp/ccGEcfLD.o: In function
> > `main':
>
> > /cygdrive/d/SCANF/TestApp_Memory/src/TestApp_Memory.c:85: undefined
> > reference to `xil_print'
> > collect2: ld returned 1 exit status
>
> > make: *** [TestApp_Memory/executable.elf] Error 1
>
> > Done!
>
> > Expecting a quick response
>
> > Thanks in advance
>
> You do not have enough code space to use scanf()...
>
> Jan- Hide quoted text -
>
> - Show quoted text -
Hi ,
I have assigned 64k of local memory.
Is there an alternative to this problem im facing.
I want to be able to read intergers from the hyper terminal.
Thanks
Article: 129329Hi, For one of my projects, I am looking for ADPCM IP core. I found a previous thread and a Xilinx release note which says that the core is available from Xilinx. But I could not find it. http://www.allbusiness.com/media-telecommunications/6538619-1.html Could anyone give me any pointers? Thanks, -- GoliArticle: 129330
Hi Uncle Noah, I have just received one source zipped file. Do you missed to send others packages (compiler, benchmark, ...) ? best reguards "Uncle Noah" <nkavv@skiathos.physics.auth.gr> a écrit dans le message de news: 93bb4042-2820-4ec5-aaf4-a4a8fa469642@s8g2000prg.googlegroups.com... >> Hello Uncle Noah, > > Hi J-S > >> What a good news ! >> >> My needs are the source code (file 1), >> The toolchain as well (file 2), >> Benchmark would be appreciable (file 3), >> So btw all files :) > > I'll have to use a file-upload service for all these. I have some work > to do at the univ. office tomorrow (today's there is a panGreek > strike:). I believe i will finish the work around 4-5pm. So around > 19:00 Greenwich time, I will post here about the files. > > I'm sending you (right here now) a XiRisc VHDL distro by email, to see > what it is about. > >> Does somebody knows if Picoga source was downloadable ? >> Or if there is another reconfigurable datapath, or reconfigurable >> coarse-grain or fine-grain architecture available at download ? > > The only publicly available reconfigurable datapath i can think of now > is the CF_RCA which can be found at the Opencores site. It is written > in a functional language called Confluence from which you can generate > (ugly lookin') VHDL and/or Verilog. It is a NEWS network for 4-bit > data. > > > Kind regards > Nikolaos Kavvadias > PS: Are you involved on a Univ. or joint academia-industry project on > processor architecture? Or is it a hobby endeavour?Article: 129331
Hi ! You can have a see to CentOS distro. This is a recompiled RedHat without modifying sources (so not like Fedora). I am using it in a production environment. It is a very powerfull, fast distro and very stable and reliable. But this is jst a working environment, no compiz or something else .... :) All softwares and also all drivers are running just fine. http://www.centos.org/ Xilinx is uning it on its AN. Else you can use Ubuntu, wich have the best community support I've ever seen. You will find many websites describing how to install Xilinx tools and drivers. Best regards. <paragon.john@gmail.com> a écrit dans le message de news: 7b729098-8f05-4d90-bf81-8717d9b4a56d@o77g2000hsf.googlegroups.com... > On Feb 19, 8:25 am, Narendra Sisodiya <narendra.sisod...@gmail.com> > wrote: >> Hi, >> I Love Linux, but currently i have to boot in XP because of xilinx >> toolset (ISE, EDK, sysgen Matlab, chipscope etc) >> May any body tell me , Any Linux Distro (other then commercial , like >> redhat, i cann't buy) which will work perfectly with all >> components(ISE, EDK, sysgen Matlab, chipscope etc). >> I am using Fedora 7 and face problem with cable drivers and many such >> things, >> Is any body working perfectly with this any Linux Distro, ??? > > I believe Sysgen is Windows only. So, I don't think there is any way > to satisfy your requirement. > > If this is incorrect, that would be fantastic news to me, as Sysgen is > one of the few things still tying me to Windows.Article: 129332
Hi, All! Need more info about system generator hardware co-simulation interface. Using JTAG for custom board very simply but extremely slow. How to support hardware co-simulation on custom FPGA boards with high speed interfaces: Ethernet, PCI, USB. For example: ML506 board Ethernet co-simulation files, from system generator plugins folder: eth_cosim_bitgen.opt eth_cosim_core.lna eth_cosim_core_synopsis eth_cosim_impl.opt eth_cosim_top.bmm eth_cosim_top.ucf ML506_PPEth_NonMmPorts.m ML506_PPEth_PostGeneration.m ML506_PPEth_Target.m xltarget.m How to build such plugin for custom Virtex board?Article: 129333
> Nial, > Your reciprocal division is reasonably close to a low latency divider I've used many times in the > past. Instead of just one reciprocal, use the upper bits of the denominator to address a BRAM > containing reciprocals, then use the lower bits of the denominator to interpolate between the > stored reciprocals to obtain a corrected reciprocal for more precision. Use that to multiply the > numerator to obtain the quotient. It can be pipelined to run at the max clock for the multipliers, > and has a latency of a BRAM plus two multipliers plus an adder. > > For example a divider with 17 bit denominator and numerator and 16 bit quotient can use the upper > 10 bits of the denominator to address a 1Kx18 reciprocal ROM to get an approximate reciprocal. > Interpolate using a second 1Kx18 ROM (holds the slope at each stored reciprocal) and a multiplier > to get a correction equal to the product of the 6 LSBs of the denominator and the entry from the > interpolation rom. That gets added to the reciprocal ROM output to get a corrected reciprocal. > Multiply that corrected reciprocal by the numerator and round to get the quotient. The entire 17 > bit divide uses two multipliers, two BRAMs and two adders plus registers to match delays to give a > low latency divider. You can improve the accuracy further if you can normalize the denominator > and numerator before the divide and then denormalize by the difference of the normalizing shifts > afterwards (basically floating point). Thanks Ray, This is exactly the sort of technique I was talking about. This will defenitely be worth a look in I end up having to do multiple divisions (as I think I might have to). Nial.Article: 129334
Hi all, I want to know whether it is possible to program Spartan 3a for a run time partial reconfiguration. If yes are there any detailed demo programs available? Regards, ParunoyArticle: 129335
Hi, We are currently designing a Xilinx Spartan-3 FPGA based tool that needs to communicate with a daughter card. Multiple variations of daughtercard exist, each of which have a different IO voltage ( 1.5 to 3.3v) As we dont know what voltage the FPGA IO bank is going to operate, (as daughtercard will be hot-plugged, so we may remove a 1.5V daughtercard and replace it with 1.8v one) the daughtercards are going to power the VCCO of FPGA (1.5 to 3.3v). The daughtercards are connected using 2 ft ribbon cable. so we would like to be able to tinker with the slew rate and drive strengths too. (that narrows me down to LVCMOS and LVTTL) Only one daughtercard will be plugged in at a time, so i am not trying to use 2 IOSTANDARDs at the same time. My question is, 1) In the UCF file, what IOSTANDARD should i set for the pins ? will it be ok if i select LVCMOS15 and expect that the IOs will work fine even at applied VCCO of 3.3v ? (setting the pin to LVCMOS33 may not go down well for 1.5v daughtercard ... ?) 2) how are the VOH/VOL values of the (input section of) FPGA pins related to VCCO actually applied and IOSTANDARD selected in the UCF ? My assumption is that the VOH/VOL are a percentage of VCCO actually applied to the VCCO pin. IOSTANDARD is just used by place-n-route tool to ensure that user does not place incompatible IOs in same bank. any pointers that lead to answers are also fine. meanwhile, i have already gone through the following before posting here. 1) xilinx ug331.pdf, "using IO resources" chapter, page-352, contains a table. in the IOSTD vs VCCO table, for the entry LVCMOS25 vs VCCO of 1.8v there is a '-' (which means, undefined). for Spartan 3A/AN, VCCO of 1.8 acts as input for LVCMOS25. 2) This comes surprisingly close to my problem. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/90b7171e7e876f10/933fcd1de1b211b2?lnk=st&q=FPGA+LVCMOS#933fcd1de1b211b2 Thanks -mpArticle: 129336
Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio (SDR) implementieren. Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, etc..) ganz gut . Genauso kann ich auch VHDL und VERILOG. Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt einem SDR auf oben genanntem Board (oder anderen) zu implementieren zweck Erfahrungsaustauch. Im folgenden einem detaillierten =DCberblick =FCber was ich bis jetzt gemacht habe: Zun=E4chst strebe ich nur mal den Empfang von AM Signal an, damit man auch etwas zum Vorf=FChren hat. Hardwarem=E4=DFig ist auf dem Board einiges da: einer DA-Wandler (LM4550) von National und einer externen AD-Wandler (LTC2208) von Linear Technology. Ich habe bereit alle Software entwickelt (ADC.vhd,DAC.vhd, DDC.vhd,...). Nun muss ich meine Signale testen: und zwar mit einem Funktionsgenerator m=F6chte ich einem Sinus erzeugen, danach den Sinus mit der FPGA verarbeiten durch die AD und DA -Wandler . Allerding sollte ich die gleiche Signale wieder empfangen. Beispiel.: Sinus(1Khz)----> ADC-->FPGA--->DAC--->Sinus(1Khz) Ich kann schon etwas am Ausgang (nach der DA-Wandler) mit dem Kopfh=F6rer h=F6ren. Allerdings k=F6nnte ich das mit dem Oszilloskop nicht messen . Ich habe schon vieles ausprobiert ohne Erfolg und frage wo das Problem liegen kann? Ob es am Downsampling liegt oder eher an einer Clockst=F6rung? Hat Jemand vielleicht eine Idee oder einem Tipp f=FCr mich?? Ich freue mich auf alle Vorschl=E4ge und bedanke mich im Voraus.. ChindjiArticle: 129337
The NiosII blurb says that it can implement a single instruction 32 bit multiply or divide. I wonder what sort of architecture they're using? Nial.Article: 129338
>The NiosII blurb says that it can implement a single instruction >32 bit multiply or divide. > >I wonder what sort of architecture they're using? What's unusual about a single instruction multiply or divide? Surely it's just a question of writing the microcode to do it. MikeArticle: 129339
mp, An IO programmed for a specific Vcco as LVCMOS will function at any higher Vcco applied to the bank. The input threshold depends on the Vcco voltage to the bank (~ 1/2 Vcco), so that is not an issue. The only concern is that a 8 mA slow IO at 1.5 volts, may be a 24 mA fast IO at 3.3 volts (too many output drivers enabled at a lower voltage to meet current requirement). You would have to consider the signal integrity, and be sure this will meet your needs. Again, it will function as desired, but SI may not be what you want. I suggest setting the IO for something like 8 mA slow at 1.8, or 2.5 volts, and then seeing how they look at 1.5 and 3.3 volts. Split the difference (compromise). AustinArticle: 129340
On 21 Feb., 14:17, auguste.chin...@googlemail.com wrote: > Im folgenden einem detaillierten =DCberblick =FCber was ich bis jetzt > gemacht habe: > > Zun=E4chst strebe ich nur mal den Empfang von AM Signal an, damit man > auch etwas zum Vorf=FChren hat. > > Hardwarem=E4=DFig ist auf dem Board einiges da: einer DA-Wandler (LM4550) > von National und einer externen AD-Wandler (LTC2208) von Linear > Technology. Ich habe bereit alle Software entwickelt > (ADC.vhd,DAC.vhd, > DDC.vhd,...). Nun muss ich meine Signale testen: und zwar mit einem > Funktionsgenerator m=F6chte ich einem Sinus erzeugen, danach den Sinus > mit der FPGA verarbeiten durch die AD und DA -Wandler . Allerding > sollte > ich die gleiche Signale wieder empfangen. > > Beispiel.: > Sinus(1Khz)----> ADC-->FPGA--->DAC--->Sinus(1Khz) > Ich kann schon etwas am Ausgang (nach der DA-Wandler) mit dem > Kopfh=F6rer > h=F6ren. Allerdings k=F6nnte ich das mit dem Oszilloskop nicht messen . Ich k=F6nnte mir aus diesen Angaben auch keinen Reim machen. Sollte Anderen das Board und verwendete hdl-Funktionsger=FCste bekannt sein? > Ich > habe schon vieles ausprobiert ohne Erfolg und frage wo das Problem > liegen kann? Ob es am Downsampling liegt oder eher an einer > Clockst=F6rung? > > Hat Jemand vielleicht eine Idee oder einem Tipp f=FCr mich?? Auf englisch oder in besserem Deutsch fragen stellen, Weiterarbeiten, Konkrete Fragen ohne konjunktiv stellen, relevantere Informationen zu den Fragen liefern.Article: 129341
Chindgi, I apologize for not replying in German, my written German is worse than my spoken German, which is only at grammer school level. It seems like you have the conversion of the analog sine wave to digital (AD), and conversion back again (DA) working in both VHDL, and hardware, yet you say you can not see anything on the oscilloscope. First, did you simulate the design? Does the simulation test bench work? Second, are you able to input, and output static (unchanging) DC voltages? This would be my first test, before I tried AC (sine waves). If this is an issue with clocking (sampling), the DC will work, and then the AC will have issues with frequency response (just guessing). If the DC does not work, then I would use a logic analyzer (if it is Xilinx, Chipscope(tm) is soft IP that may be part of your design, and allows you to probe your digital signals inside the FPGA and see if they are what you expect in the DC case). http://www.xilinx.com/ise/optional_prod/cspro.htm Perhaps a German speaker will be more helpful to reply, AustinArticle: 129342
Thanks a lot Austin! /MikhailArticle: 129343
On Feb 21, 5:17=A0am, auguste.chin...@googlemail.com wrote: > Hallo, > ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und > wollte darauf nun mal ein Software Defined Radio (SDR) > implementieren. > Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, > etc..) > ganz gut . Genauso kann ich auch VHDL und VERILOG. > Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt > einem SDR > auf oben genanntem Board (oder anderen) zu implementieren zweck > Erfahrungsaustauch. > > Im folgenden einem detaillierten =DCberblick =FCber was ich bis jetzt > gemacht habe: > > Zun=E4chst strebe ich nur mal den Empfang von AM Signal an, damit man > auch etwas zum Vorf=FChren hat. > > Hardwarem=E4=DFig ist auf dem Board einiges da: einer DA-Wandler (LM4550) > von National und einer externen AD-Wandler (LTC2208) von Linear > Technology. Ich habe bereit alle Software entwickelt > (ADC.vhd,DAC.vhd, > DDC.vhd,...). Nun muss ich meine Signale testen: und zwar mit einem > Funktionsgenerator m=F6chte ich einem Sinus erzeugen, danach den Sinus > mit der FPGA verarbeiten durch die AD und DA -Wandler . Allerding > sollte > ich die gleiche Signale wieder empfangen. > > Beispiel.: > Sinus(1Khz)----> ADC-->FPGA--->DAC--->Sinus(1Khz) > Ich kann schon etwas am Ausgang (nach der DA-Wandler) mit dem > Kopfh=F6rer > h=F6ren. Allerdings k=F6nnte ich das mit dem Oszilloskop nicht messen . > Ich > habe schon vieles ausprobiert ohne Erfolg und frage wo das Problem > liegen kann? Ob es am Downsampling liegt oder eher an einer > Clockst=F6rung? > > Hat Jemand vielleicht eine Idee oder einem Tipp f=FCr mich?? > > Ich freue mich auf alle Vorschl=E4ge und bedanke mich im Voraus.. > > Chindji Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal die "lingua franca" dieser Industrie und Technologie. Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen zusammensetzst, um mit Deinem Projekt voranzukommen. Viel Erfolg ! Peter Alfke, Xilinx Applications Engineering From puiterl@notaimvalley.nl Thu Feb 21 09:08:59 2008 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!nx02.iad01.newshosting.com!newshosting.com!newsfeed.icl.net!newsfeed.fjserv.net!syros.belnet.be!news.belnet.be!transit.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail Message-Id: <47bdb02b$0$14359$e4fe514c@news.xs4all.nl> From: Paul Uiterlinden <puiterl@notaimvalley.nl> Subject: Re: TCL testcase in Modelsim. Newsgroups: comp.arch.fpga,comp.lang.vhdl Followup-To: comp.arch.fpga Date: Thu, 21 Feb 2008 18:08:59 +0100 References: <7b4ca020-5aad-4432-81f9-b58337de0e8c@h11g2000prf.googlegroups.com> Organization: AimValley User-Agent: KNode/0.10.5 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 25 NNTP-Posting-Host: 80.127.156.247 X-Trace: 1203613739 news.xs4all.nl 14359 [::ffff:80.127.156.247]:61215 X-Complaints-To: abuse@xs4all.nl Xref: prodigy.net comp.arch.fpga:141648 comp.lang.vhdl:73872 X-Received-Date: Thu, 21 Feb 2008 12:09:03 EST (newsdbm02.news.prodigy.net) bigyellow wrote: > Hello, > > Does anybody have experience on writing TCL testcase in Modelsim? I > only have VHDL simulation license of Modelsim, I used to write both > testbench and testcase in VHDL. But I feel VHDL is not that nice to > implement testcase. Then you should get to know VHDL better. VHDL offers a lot of high level constructs and ways to write behavioral code. If you come from an RTL back ground, then the hardest thing I suppose is switching to a behavioral mind set. You are freed from all limitations otherwise imposed to you by the synthesizer. > So I am thinking to implement my testbench in VHDL, and write the > testcases in TCL for my next project. I would not go into that path. As others already said: it is not portable. And VHDL offers much more than Tcl. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not.Article: 129344
Dwayne Dilbeck wrote: > Simulation speed depends on how the original tool handled the VHDL > testbench. > In general the TCL is going to be slower. IF you need a faster Testbecnh. > Look into System C. But in general a VHDL testbench is not limiting the simulation speed, the design is. The testbench is written in a behavioral way, which simulates much faster than the RTL code of the design. -- Paul Uiterlinden www.aimvalley.nl e-mail addres: remove the not.Article: 129345
Parunoy, What you describe is not supported in Spartan 3A. AustinArticle: 129346
On 21 Feb., 18:27, austin <aus...@xilinx.com> wrote: > Parunoy, > > What you describe is not supported in Spartan 3A. > > Austin I did think s3a ICAP has access to FPGA configuration ? I know there are no demos available, but to say that S3a is totally incapable of runtime reconfig? or I have i missed something? the lack of tools, demos and documentation doesnt always mean that the feature itself is missing, only that is harder to use. AnttiArticle: 129347
>Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass >nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja >offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal >die "lingua franca" dieser Industrie und Technologie. > >Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich >schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen >zusammensetzst, um mit Deinem Projekt voranzukommen. >Viel Erfolg ! >Peter Alfke, Xilinx Applications Engineering If he's more comfortable with German then let him write in German, whether or not it's his native language. Of course, there may be, as you say, few who understand him and can reply. I know almost no German, but that's my loss as much as his. If I see here a language I don't understand, I just ignore it. If this is a "single-language" group, I'm in the worng place. I don't do segregation. MikeArticle: 129348
>LFSRs are fine for a psuedo-random sequence. If it needs to be truely >random however (such as with crypto), an LFSR is not suitable because >the output is predictable given the history. If you do use an LFSR, >take only one bit per clock of the LFSR, as the bits are highly >correlated in the shift register. Maybe one could exploit gated clocks, signal races, metastability etc.. to get randomness without resorting to hardware? (like transistor white noise).Article: 129349
Antti, The 3A configuration bits have potential to "glitch" when reconfigured, so one has to carefully select what to reconfigure, and then make sure it works as desired. So, yes, you can physically do it, but it may not perform as desired. This is different in Virtex devices, where it is fully supported (or a full as we can be right now). Austin
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