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Dave wrote: > lets assume I have two signals, each carrying 8 bits of information. > One signal is a so called configuration signal and has exactly 4 bits > that are HIGH and 4 bits that are LOW. Now depending on on the values > of the configuration signal I wanna reorder the bits in the other signal > in the following way: If a bit is set in the configuration signal, then > the corresponding bit in the source register will be part of the most > significant 4 bits of the result signal. If a bit in the configuration > signal is not set then the corresponding bit in the source register will > be part of the least significant 4 bits. Difficult to describe, so here > an example > Source: A B C D E F G H > Configuration: 1 0 1 0 1 0 1 0 > Result = ACEG BDFH > So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 > LSB bits. Is there maybe a better approach to do implement this on an FPGA? A 64K by 8 lookup table will do it. You need more than a few muxes, especially if the result bits have to come out in order. Consider the positions that D could possibly come out in, for example, and figure out how to get it to those positions. It might be best to look at the problem backwards. Consider each output bit, which input bits could possibly be routed there, and which configuration bits will indicate each of those. You might also look at a priority encoder. -- glenArticle: 129026
Hi Kolja, like John wrote earlyer in this thread: The joy and the challenge of electronics includes wrapping your mind around the problem and figuring out how you can dice the problem up to get the desired result. Different engineers will produce different "right" results. Yours is a nice idea I would hardly think of, because I'm avoiding loops to create combinatorical logic. Mainly because I can not estimate what ammount of logic will be created. But that's just some bad habit of me. :-) Of course a test synthesis will show the results in an instant and the result can be accepted or dumped according to design requirements. Well done. Regards Eilert comp.arch.fpga schrieb: > On 12 Feb., 07:56, backhus <n...@nirgends.xyz> wrote: > >> And if the signals actually do have 8 bits of parallel data, you can >> still use the above solution, if you can clock this circuit at 8 times >> the datarate (if possible). Of course you need another two 8 bit >> parallel to serial SRs. > > You can even use this thinking to model a parallel single clock > solution. > You write a for loop and just omit the registers. > > Essentially what you create is a chain, where bit N is either taken > from the > right neighbour or from the input depending selctor bit at that > position. > (i.e. one output skips all 0s, the other all 1s) > > Kolja SulimmaArticle: 129027
Hello Uncle Noah, What a good news ! My needs are the source code (file 1), The toolchain as well (file 2), Benchmark would be appreciable (file 3), So btw all files :) Thank you very much. Best regards. PS : Does somebody knows if Picoga source was downloadable ? Or if there is another reconfigurable datapath, or reconfigurable coarse-grain or fine-grain architecture available at download ? "Uncle Noah" <nkavv@skiathos.physics.auth.gr> a écrit dans le message de news: 0ca7e343-6d12-42c3-816f-e39f772dce95@i29g2000prf.googlegroups.com... On Feb 12, 7:10 pm, "Jean-sébastien LEROY" <jean.sebastien.le...@club- internet.fr> wrote: > Hello all, > > You have a snapshot of the XiRisc softcore processor sources ? > > It seems that sources are not available to download now anywhere ... > > Best regards. Hi indeed the XiRisc website has been down for more than a year. I believe what you need would be: 1. The VHDL source code distro. I have two different versions of this, one with a few more features (caches and an AMBA interface) and another one. (<1MB) 2. I have 4 different versions of the Xirisc gcc-based toolchain. The toolchain includes some additional "profiling" tools as well. (~30-50MB) 3. A set of nice (and mostly self-contained) benchmark programs. (~4MB) Which ones are OK to you? Do you need a toolchain as well? I can have a look on some ol' archives since 2002-2004 around my home PC. Will be there in a few hours (now i'm in the office). Kind regards Nikolaos Kavvadias PS1: Xirisc is nice and rather complete soft-core. Have used this for a couple of research publications. It is probably a little large for a small FPGA (200k system gates). If stripped, i believe it can fit in a S3E500. PS2: Fabio Campi and most of the Xirisc people might be around. You could ask them as well, on the status of Xirisc, the level of support etc.Article: 129028
gavin@allegro.com (Gavin Scott) writes: > everphilski@gmail.com <everphilski@gmail.com> wrote: >> I'm interested in learning more about DSP's and actually getting my >> feet wet with DSP hardware. I have three primary interests: > >> 1) robotics > > For robotics I think you're better off in the microcontroller realm, > with something like your Amtel AVR or a Parallax Propeller that will > easily interface with all kinds of easily available and relatively > inexpensive modules (www.sparkfun.com kinda stuff). I think of > robotics more as a system integration problem. The Propeller is interesting, it'll certainly get you thinking parallel which will stand you in good stead for FPGAs (and for future processors!) > >> 2) computer vision > > Machine vision is pretty much entirely a software issue I think, You may think so - I'd disagree! Machine vision is an *algorithms* thing. Algorithms are often easiest to prototype in SW at a desk with a webcam, but if you want to make them run "standalone" then targetting an FPGA for the highly parallel parts makes a lot of sense. Of course, to do that successfully, you have to build your algorithms with FPGAs in mind - and to do that, you have to have tried to implement some already :-) > so if you want to learn about it, I'd consider starting with a PC > and a $20 webcam and the free programming language of your choice > along with a book or two on the subject. Agreed! But if you *ever* want it to run outside of a PC, run around the loop of "taking the algorithms into embedded hardware and changing them to suit" early and lots of times. You'll learn more that way. >> My second question is, what is the best way to start learning? In >> doing reading I see the Spartan 3E evaluation board seems to be highly >> recommended. The board looks neat, I'm just curious what the best way >> to learn is. > > The Spartan 3 starter board is fine (I have one), but to get started > and get a feel for things you can start by downloading the free ISE > WebPack software from Xilinx to see what the development process looks > like for their FPGAs. You can design/code, build and simulate all > without actually having any actual hardware. Yeah, but it's much more fun when you can see that LED flashing like you told it to instead of a wiggly waveform on screen :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 129029
Specification EDK version:8.2.02i FPGA Board: Virtex II Pro I just upgraded EDK 8.2i to 8.2.02i. In 8.2i compilation of my source code using mb-g++ works. Compilation however, failed when upgraded to service pack 2. I added #include <stdio.h> to all header files in EDK. Yet the following error appears. Please advice. ./microblaze_0/lib//libxil.a(xsysace_l.o): In function `XSysAce_RegRead32': /cygdrive/c/cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/ xsysace_l.c:111: undefined reference to `XIo_EndianSwap16' /cygdrive/c/cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/ xsysace_l.c:115: undefined reference to `XIo_EndianSwap16' ./microblaze_0/lib//libxil.a(xsysace_l.o): In function `XSysAce_RegRead16': /cygdrive/c/cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/ xsysace_l.c(.text+0x78): undefined reference to `XIo_EndianSwap16' ./microblaze_0/lib//libxil.a(xsysace_l.o): In function `XSysAce_RegWrite32': /cygdrive/c/cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/ xsysace_l.c(.text+0xb4): undefined reference to `XIo_EndianSwap16' /cygdrive/c/cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/ xsysace_l.c(.text+0x10c): undefined reference to `XIo_EndianSwap16' ./microblaze_0/lib//libxil.a(xsysace_l.o)(.text+0x14c):/cygdrive/c/ cachinggplusplus/microblaze_0/libsrc/sysace_v1_01_a/src/xsysace_l.c: more undefined references to `XIo_EndianSwap16' follow collect2: ld returned 1 exit status make: *** [TestApp_Peripheral/executable.elf] Error 1 Done! Thank you. Priyantha De Silva From thorstenkiefer@gmx.de Wed Feb 13 01:51:14 2008 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!nx02.iad01.newshosting.com!newshosting.com!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.freenet.de!news.albasani.net!news01.khis.de!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <47b2bd8d$0$26904$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <thorstenkiefer@gmx.de> Subject: Re: Spartan 3A starter kit Newsgroups: comp.arch.fpga Date: Wed, 13 Feb 2008 10:51:14 +0100 References: <704c96b0-93b6-4417-88c3-d89ab7f87eaf@z17g2000hsg.googlegroups.com> User-Agent: KNode/0.10.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 19 Organization: CNNTP NNTP-Posting-Host: d74ce373.read.cnntp.org X-Trace: DXC=@bFVPknhL1H]ERPN0>`82KWoT\PAgXa?A7oZaIHiSKnMf0R5AK2MPCF;b6j[U0Bn<A^aOSOgEUU9LMDZ3[M\5eaI X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:141324 X-Received-Date: Wed, 13 Feb 2008 04:51:11 EST (newsdbm02.news.prodigy.net) anas_waris wrote: > Hi, > > Does any one know any examples on the xilinx web site or in the CD > (which is sent with the starter kit) that can be downloaded to > development board. If someone can help me on this, it would be great. > I have received my board from Xilinx, i did find one example on the > website, but that is for another fpga, and the fpga i am having in my > board is XC3S700A. Can anyone help me on this. > > Regards, > Anas. http://www.amazon.com/FPGA-Prototyping-VHDL-Examples-Spartan-3/dp/0470185317/ref=pd_bbs_sr_2?ie=UTF8&s=books&qid=1202896224&sr=8-2 I have that book at home. It is exactly, what we need !!!!!!!Article: 129030
Hi, is there a library for that , or do I have to code it myself ? Would you be interested in s.th. like that ? Regards ThorstenArticle: 129031
> Xilinx's FireBlaze processor simulation on a FPGA. Do you mean Xilinx's MicroBlaze processor? If so, note that this is a general purpose CPU with a fairly average MIPs spec. You'd easily be able to get comparable or better performance with an off the shelf microprocessor -and without all the headaches!Article: 129032
Hi all, I have a source clock 125MHz (ck125), and it has a derived clock 25MHz(ck25). I find that Quartus generates ck25 by the clock tree of ck125. To a register A (regA), ck125 has a clock arrival time 4ns. To the register which generates ck25 and is clocked by ck125, the ck125 also has a clock arrival time 4ns. A register B (regB) is clocked by ck25, and there is path from regB to regA. Shortest clock path from ck125 to regA is 4.5ns. Longest clock path from ck25 to regA is 12ns. Quartus say the Largest clock skew is -7.5ns, and the Largest regB to regA requirement is 0.5ns. (125MHz is 8ns period, 8 - 7.5 = 0.5 ) Unfortunately, i have a path from regB to regA is1ns. What can i do...? QQ Thanks, CKArticle: 129033
On Feb 12, 5:33 pm, chrisde...@gmail.com wrote: > Hi Dave, > > my mistake. Here is what i intended it to be. > > to paraphrase: > #1: RTS(PC) -> CTS(FPGA) 0 = PC has no data to send to FPGA. If PC > sends data without asserting its RTS, > UART will not shift > in the inputs. > 1= PC should assert this > if it has data to send. only then can FPGA can receive data > from PC > > #2: RTS(FPGA) -> CTS(PC) 0 = receive buffer on UART attached to > microblaze is full. During this time, PC should > no longer transmit > to FPGA. once receive buffer has been cleared, FPGA will set > the RTS line again. > 1 = PC can transmit to > FPGA as the UART receive buffer is not full. > > did you spot any mistake? Is there a need for FPGA to use DSR? > > Chris > > On Feb 12, 11:47 pm, Dave Pollum <vze24...@verizon.net> wrote: > > > On Feb 11, 10:55 am, chrisde...@gmail.com wrote: > > <snip> > > 1) rts on PC side will drive FPGA cts pin. If rts on PC side = 1, then > > transmission from FPGA to PC will be possible. otherwise, the FPGA > > cannot transmit anything back to PC. > > 2) cts on PC side is driven by FPGA rts pin. FPGA rts pin = 1 once the > > receiver buffer in UART peripheral attached to microblaze is full. > > this will disable PC from sending any more data to microblaze on the > > FPGA. > > <snip> > > > to paraphrase: > > #1: RTS(PC) -> CTS(FPGA) 1 = FPGA transmits to PC > > #2: RTS(FPGA) -> CTS(PC) 1 = PC _does not_ transmit to FPGA > > > Is this really what happens, or did you mistype? > > -Dave Pollum Hi All: This may indeed be a problem but how does debug make it all work. georgeArticle: 129034
On Feb 13, 6:08=A0am, "C-M, Chang" <cmchan...@gmail.com> wrote:
> Hi all,
>
> I have a source clock 125MHz (ck125), and it has a derived clock
> 25MHz(ck25).
> I find that Quartus generates ck25 by the clock tree of ck125.
> To a register A (regA), ck125 has a clock arrival time 4ns.
> To the register which generates ck25 and is clocked by ck125, the
> ck125 also has
> a clock arrival time 4ns.
> A register B (regB) is clocked by ck25, and there is path from regB to
> regA.
> Shortest clock path from ck125 to regA is 4.5ns.
> Longest clock path from ck25 to regA is 12ns.
> Quartus say the Largest clock skew is -7.5ns, and the Largest =A0regB to
> regA requirement
> is 0.5ns. (125MHz is 8ns period, =A08 - 7.5 =3D 0.5 )
> Unfortunately, i have a path from regB to regA is1ns.
> What can i do...? QQ
>
> Thanks,
> CK
=46rom your description, I'm guessing that your derived clock ck25 is
done via flip flops and trying to synthesize a 25 MHz clock from a 125
MHz clock....this method is prone to failure in FPGA land due to the
unavoidable skew between these two 'clocks' as you're witnessing.
The much better approach is to simply clock everything with the 125
MHz clock and use ck25 as a clock enable.
Example:
process(Clk125)
begin
if rising_edge(Clk125) then
if (Ck25 =3D '1') then
-- Put stuff here that needs to be 'clocked' by 25 MHz
end if;
end if;
end process;
ck25 simply needs to be a one clock cycle pulse that is active every
5th clock cycle, you should be able to modify your existing code that
generates ck25 to do this.
The other method would be to use a PLL to divide down the 125 MHz to
create a real 25 MHz clock that is phase aligned with the 125
MHz...but it would be simpler to try the clock enable approach first
and see where you end up.
Kevin Jennings
Article: 129035> Hello Uncle Noah, Hi J-S > What a good news ! > > My needs are the source code (file 1), > The toolchain as well (file 2), > Benchmark would be appreciable (file 3), > So btw all files :) I'll have to use a file-upload service for all these. I have some work to do at the univ. office tomorrow (today's there is a panGreek strike:). I believe i will finish the work around 4-5pm. So around 19:00 Greenwich time, I will post here about the files. I'm sending you (right here now) a XiRisc VHDL distro by email, to see what it is about. > Does somebody knows if Picoga source was downloadable ? > Or if there is another reconfigurable datapath, or reconfigurable > coarse-grain or fine-grain architecture available at download ? The only publicly available reconfigurable datapath i can think of now is the CF_RCA which can be found at the Opencores site. It is written in a functional language called Confluence from which you can generate (ugly lookin') VHDL and/or Verilog. It is a NEWS network for 4-bit data. Kind regards Nikolaos Kavvadias PS: Are you involved on a Univ. or joint academia-industry project on processor architecture? Or is it a hobby endeavour?Article: 129036
I've been programming embedded micros for a long time, and have a decent understanding of hardware. I finally ordered an FPGA development kit (still in the mail) because I find the whole FPGA concept fascinating. What I don't grasp is when an FPGA is the best choice. To get a better feel for this, I'd like to hear some comments on when an FPGA is the best fit, and also when an FPGA turned out to be a poor choice. Many thanks for any advice. MikeArticle: 129037
On 13 f=E9v, 05:08, Thorsten Kiefer <thorstenkie...@gmx.de> wrote: > Hi, > is there a library for that , or do I have to code it myself ? > Would you be interested in s.th. like that ? > > Regards > Thorsten VHDL-2008 provides a float package: http://www.eda.org/fphdl/ PatrickArticle: 129038
I am using for the first time a Xilinx RocketIO module (I have years of FPGA experience though); normally I prefer to explicitly write on my code all the instatiations. Manual UG196 says:" The RocketIO GTP Transceiver Wizard is the preferred tool to generate a wrapper to instantiate a GTP_DUAL primitive." Any experience and advice about coding vs wizard in the case of RocketIO ? My application requires to use the GTP for a simple but non-standard protocol (8b/10b with a custom packet). Regards, Tullio Grassi FermilabArticle: 129039
Rob, On Feb 13, 4:18 am, Rob <BertyBoos...@googlemail.com> wrote: > > Xilinx's FireBlaze processor simulation on a FPGA. > > Do you mean Xilinx's MicroBlaze processor? If so, note that this is a > general purpose CPU with a fairly average MIPs spec. You'd easily be > able to get comparable or better performance with an off the shelf > microprocessor -and without all the headaches! Yes, I meant MicroBlaze, thanks for catching the typo. This is good, so you are saying you would prefer working with a discrete microcontroller interfaced to a FPGA, instead of a FPGA with a MicroBlaze (or other core) onboard? Thanks, PhilipArticle: 129040
Gavin, On Feb 12, 7:18 pm, ga...@allegro.com (Gavin Scott) wrote: > everphil...@gmail.com <everphil...@gmail.com> wrote: > > I'm interested in learning more about DSP's and actually getting my > > feet wet with DSP hardware. I have three primary interests: > > 1) robotics > > For robotics I think you're better off in the microcontroller realm, > with something like your Amtel AVR or a Parallax Propeller that will > easily interface with all kinds of easily available and relatively > inexpensive modules (www.sparkfun.comkinda stuff). I think of > robotics more as a system integration problem. > I'd tend to agree with you, it's an integration problem. I was trying, I guess, to come up with a good excuse to learn FPGA's and then DSP techniques. I have a lot of ideas, but robotics is something I actually have practical experience in so I figured I could sub out the FPGA for the AVR/MC68HC11/PIC's I've used in the past as a learning experience, before going on to other projects like vision processing and radio processing where I know very little and I'd have to learn more than just the FPGA design aspects. That was my thought. > > 3) software defined radios. > > For SDR maybe some DSP hardware (or FPGA maybe, though I'm not sure > how much fun doing serious DSP in a Spartan 3 would really be) probably > makes sense. I think there might be a few reasonably priced > experimenter's boards out there. > Could I get you to expand on the difference between "DSP hardware" and "FPGA" in this context? My (albeit new) understanding was, DSP techniques were implemented on FPGA hardware to do digital signal processing. Or are you talking about a chip tailored specifically to audio processing versus a general purpose FPGA? > FPGAs are pretty cool, especially the "hardware becomes software" aspect > which is quite appealing to those of us with more of a software > background, but they're also very complex so if you're really interested > in learning to design for FPGAs (programming in VHDL/Verilog etc.) > then great, but if you're more interested in the applications than > in the technology then something less generic and more specific to > the problem you're trying to solve might greatly simplify things. > I am interested in learning. I do have experiance with various microcontrollers and I write various simulations/data reduction codes at work, but nothing in real time like a DSP would perform. It kind of sounds like fun. > Just my random thoughts. > I do appreciate them, thank you. > G. PhilipArticle: 129041
i think FPGAs is a good choice when 1). there's lots of data parallelism inside the algorithm you gonna run on FPGAs. FPGAs is enabled to exploit such data parallelism and achieve amazing performance; 2). when your design needs to change frequently, FPGAs is a good choice b/c it can be configured tens of thousands of times without bothering PCB change; 3). also, low volume in production, low speed in design. otherwise, ASICs will probably be your solution. On Feb 13, 9:01 am, Mike Silva <snarflem...@yahoo.com> wrote: > I've been programming embedded micros for a long time, and have a > decent understanding of hardware. I finally ordered an FPGA > development kit (still in the mail) because I find the whole FPGA > concept fascinating. What I don't grasp is when an FPGA is the best > choice. To get a better feel for this, I'd like to hear some comments > on when an FPGA is the best fit, and also when an FPGA turned out to > be a poor choice. Many thanks for any advice. > > MikeArticle: 129042
"Mike Silva" <snarflemike@yahoo.com> wrote in message news:24a760f9-e4d0-4bb7-8392-a32957d14f07@e25g2000prg.googlegroups.com... > I've been programming embedded micros for a long time, and have a > decent understanding of hardware. I finally ordered an FPGA > development kit (still in the mail) because I find the whole FPGA > concept fascinating. What I don't grasp is when an FPGA is the best > choice. To get a better feel for this, I'd like to hear some comments > on when an FPGA is the best fit, and also when an FPGA turned out to > be a poor choice. Many thanks for any advice. > > Mike Hi Mike, Did you try Google? fpga vs microcontroller Please come back when you have a specific application in mind that a Google search does help with. Cheers, Syms. p.s. It's very close on Googlefight! http://googlefight.com/index.php?lang=en_GB&word1=fpga&word2=microcontrollerArticle: 129043
On Wed, 13 Feb 2008 06:01:40 -0800 (PST), Mike Silva <snarflemike@yahoo.com> wrote: >I've been programming embedded micros for a long time, and have a >decent understanding of hardware. I finally ordered an FPGA >development kit (still in the mail) because I find the whole FPGA >concept fascinating. What I don't grasp is when an FPGA is the best >choice. To get a better feel for this, I'd like to hear some comments >on when an FPGA is the best fit, and also when an FPGA turned out to >be a poor choice. Many thanks for any advice. > >Mike Looking at an FPGA as a 'step up' from a MCU, the primary advantages are Speed, Parallelism and Pin count. The downsides are power consumption, power management ( multiple rails), packaging ( BGAs etc.) and availability (fewer parts routinely available off-the-shelf) .Article: 129044
Hi, anyone can tell me the differences between PLL and DCM in Virtex5 in terms of pros and cons? thank you.Article: 129045
"chestnut" <adam0818@gmail.com> wrote in message news:7000e8f0-54d4-417d-9b7b-ce282c7be05b@e25g2000prg.googlegroups.com... > Hi, > > anyone can tell me the differences between PLL and DCM in Virtex5 in > terms of pros and cons? thank you. STW. Google this:- pll dcm site:xilinx.com HTH., Syms.Article: 129046
On Wed, 13 Feb 2008 07:56:57 -0800 (PST), everphilski wrote:
>> For robotics I think you're better off in the microcontroller realm,
>> with something like your Amtel AVR or a Parallax Propeller that will
>> easily interface with all kinds of easily available and relatively
>> inexpensive modules (www.sparkfun.comkinda stuff). I think of
>> robotics more as a system integration problem.
>>
>
>I'd tend to agree with you, it's an integration problem. I was trying,
>I guess, to come up with a good excuse to learn FPGA's and then DSP
>techniques.
Depending on what sort of hardware you expect to have for
your robotics, FPGAs can actually be pretty neat for the
very low-level interfacing stuff. Standard mechatronics
functions such as quadrature-encoder counters, PWM motor
drivers and so forth go nicely into FPGAs, and the digital
design is relatively straightforward so you can concentrate
on the FPGA-specific aspects. Because you have an FPGA to
play in, you're not locked to the limitations of software
(response speed? time resolution?) and you're not limited
by what a specific device manufacturer chooses to build
and sell - so, for example, it's easy to make encoder
counters that automatically latch the count value at the
moment of an index pulse, so that your s/w can interrogate
that latched value at leisure; encoder counters with some
built-in timed interpolation or velocity measurement;
unusual PWM structures to meet specialised needs;
programmable triggering of external outputs when an
axis reaches a preset position... Lots of stuff like
that, which is tiresome to do in software - and probably
near-impossible to do with microsecond time resolution.
In some ways it's a waste of an FPGA, but hey, the thing
is sitting there waiting for you to do something with it...
Just don't forget to think about the electrical robustness
of connections to the FPGAs. Modern FPGAs have fairly
feeble I/O structures [*] working at 3V or less, and they
don't take kindly either to >5V external connections, or
to the kind of unpleasant electromagnetic crud that
tends to come for free with anything electromechanical.
Much care with level shifters, buffers and snubber
circuitry is needed to protect your FPGA investment.
The nice folk at sci.electronics.design will likely be
pretty helpful about that sort of thing, and will be
up-to-date with what's available to make it easier.
[*] Feeble by the standards of industrial automation.
No slight on the FPGA manufacturers intended!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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Article: 129047On 2$B7n(B13$BF|(B, $B2<8a(B9$B;~(B42$BJ,(B, KJ <kkjenni...@sbcglobal.net> wrote: > On Feb 13, 6:08 am, "C-M, Chang" <cmchan...@gmail.com> wrote: > > > > > > > Hi all, > > > I have a source clock 125MHz (ck125), and it has a derived clock > > 25MHz(ck25). > > I find that Quartus generates ck25 by the clock tree of ck125. > > To a register A (regA), ck125 has a clock arrival time 4ns. > > To the register which generates ck25 and is clocked by ck125, the > > ck125 also has > > a clock arrival time 4ns. > > A register B (regB) is clocked by ck25, and there is path from regB to > > regA. > > Shortest clock path from ck125 to regA is 4.5ns. > > Longest clock path from ck25 to regA is 12ns. > > Quartus say the Largest clock skew is -7.5ns, and the Largest regB to > > regA requirement > > is 0.5ns. (125MHz is 8ns period, 8 - 7.5 = 0.5 ) > > Unfortunately, i have a path from regB to regA is1ns. > > What can i do...? QQ > > > Thanks, > > CK > > From your description, I'm guessing that your derived clock ck25 is > done via flip flops and trying to synthesize a 25 MHz clock from a 125 > MHz clock....this method is prone to failure in FPGA land due to the > unavoidable skew between these two 'clocks' as you're witnessing. > > The much better approach is to simply clock everything with the 125 > MHz clock and use ck25 as a clock enable. > > Example: > process(Clk125) > begin > if rising_edge(Clk125) then > if (Ck25 = '1') then > -- Put stuff here that needs to be 'clocked' by 25 MHz > end if; > end if; > end process; > > ck25 simply needs to be a one clock cycle pulse that is active every > 5th clock cycle, you should be able to modify your existing code that > generates ck25 to do this. > > The other method would be to use a PLL to divide down the 125 MHz to > create a real 25 MHz clock that is phase aligned with the 125 > MHz...but it would be simpler to try the clock enable approach first > and see where you end up. > > Kevin Jennings- $Bp,i6Ho0zMQJ8;z(B - > > - $Bp}<(Ho0zMQJ8;z(B - Thanks KJ for anser and told my question clear. But unfortunately again, my boss deny to change design (coding from somewhere). In my project, I think that ck125 and ck25 are set as global clock network. I guess a global clock network need 4ns delay, so my ck125 has 4ns delay, and ck25 has 8ns delay. (4ns from ck125 and 4ns itself global clock network). Does Quartus have any option let ck25 just has 4ns delay. Or can i use something like: set_instance_assignment -name MAX_DELAY 0.5ns -from regB -to regA, (i think this no work) or set max_clock_arrival_skew ,min_data_arrival_skew or SETUP_RELATIONSHIP can someone told me in the situatuin which choise is better, and is right, Because i can not change code. Thanks. Thanks KJ again very much. C.-M.Article: 129048
chestnut, PLL is a well known, and well understood building block: filters jitter (jitter out is the intrinsic jitter of the VCO in the PLL), able to synthesize a Fout which is some M and some D, Fout=M/D * Fin. PLL's continue to provide an output when they have no input. Knowing that a PLL is locked is often difficult, as the PLL is an analog circuit. The DCM is a Xilinx invention, which uses matched delay lines to provide precise phase shift, zero clock insertion delay, multiple precise phase outputs (90, 180, 270 degree), and some degree of M/D synthesis. The block is all digital and synchronous, so completely deterministic behavior. Jitter is not filtered, as the output is just a delayed copy of the input (jitter is only added). Locked is a state of a state machine. DCM operates over a much wider range of Fin, Fout than a PLL due to architecture. There are some tasks where either may be used. There are some tasks where one has advantages. There are very few tasks where one can not be used at all. AustinArticle: 129049
[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
answer.]
Hi
I'm not a VHDL expert, just learning, so please don't shout.
I'm using Xilinx ISE9.2sp4 and have the following code as part of a state
machine:
CP_IN_OUTPUT_DECODE: process (state_cp_in)
begin
if state_cp_in = sta_idle then
RDY <= 'Z';
BUSY <= '0';
end if;
if state_cp_in = sta_1 then
RDY <= '0';
BUSY <= '0';
end if;
if state_cp_in = sta_2 then
RDY <= '1';
BUSY <= '1';
end if;
...
...etc
The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
RDY is a pin on the device.
During operation, I can see RDY go low in sta_1, but not high in sta_2. I
know it gets to sta_2 as I can observe BUSY. I don't think RDY is tri-stated
in sta_2 as there is an external pull-up; it just stays low. Gray encoding
is used.
If I change the RDY to rdyi (signal) and then have:
RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
outside of the decode process then it all behaves itself.
Apart from lack of experience, what mistake(s) have I made?
Thanks.
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