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On Sep 1, 1:04=A0pm, xenix <last...@gmail.com> wrote: > Hello all, > I am looking to find information/books in Camera design with CCD and > FPGA. till now i havent find any. Have you something spotted? > > regards At Elphel we have both CCD=A0and CMOS sensors drivers implemented in the FPGA. The code is distributed under GNU=A0GPL v3, the hardware documentation is under GNU=A0FDL. You can browse the code on http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x3x3/ & http://elphel.cvs.sourceforge.net/elphel/elphel353-7.1/fpga/x347/ Best regardsArticle: 134826
Svenn Are Bjerkem wrote:
> In a fairly large design I am doing some debugging on the system board
> directly. When I discover a mistake and modify the vhdl code, the
> whole design goes through synthesis and place-and-route. Many parts of
> the design are never touched by my modifications, and I wonder if it
> is possible to speed up the debug-modify-compile
I finish the debug-modify-compile loop in simulation.
Even though simulation requires significant time on the front end,
debugging typos and changes is quick and straightforward.
-- Mike Treseler
Article: 134827one can generate on a Virtex-5 device? Thanks, QingboArticle: 134828
Why does Quartus run with lowest priority level (19) under Linux? It also seems like if you nice quartus_sh to some higher priority when you start it the sub-processes (like qartus_map etc) will still have priority 19. I find this a little odd. Is there a reason for this? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 134829
Andreas Ehliar wrote: > On 2008-09-01, David Brown <david@westcontrol.removethisbit.com> wrote: >> I believe (my own thoughts) that in an FPGA design, generating and >> compiling modules is equivalent to compilation in software, and routing >> and placing is equivalent to static linking. If there are components >> that are isolated and communicate through standard and fixed interfaces, >> then it could be argued that these are separate "works" and not part of >> a complete "derived work", and the GPL/LGPL will not spread across the >> interface. But the opposite could also be argued - the router and >> placer software will dig into components on each side of the interface, >> and the implementation of these components will depend on each other. >> This of course gives you a more efficient bitstream - but it means that >> the final bitstream cannot be split into separate parts and is therefore >> a single combined "work". > > First of all: Thanks to Genode Labs for releasing this source code under > an open source license! I hope this initiative will bring you lot of > goodwill and customers! > > However, I have a few things to say regarding open source and hardware. > The license question for open source hardware is a pretty interesting one. > I feel that there are many questions here such as the one you list above. > My personal belief is that it is not legally possible to distribute a > design which contains both components under GPL and components under a more > restrictive license. > In this case, the main aim of Genode Labs is almost certainly that people can download the IP, examine it, play with it, try it out, and use it for testing or academic work - but they can't sell products using it until they buy a commercial license from Genode Labs. You are also free to modify the code and pass it around - but only under the GPL. This sort of dual-licensing is popular in the software world - it is very nice for users, developers and experimenters, with minimal risk to the company (there will always be some people who download the GPL code and use it illegally - but they are unlikely to have paid for a legitimate license if there were no GPL version available). > Regarding your comments about standard interfaces: A GPL program which > calls a proprietary library using a standardized calling convention > specified in the ABI can not be legally distributed AFAIK. (Ignoring the > system library exception.) > That's basically correct, AFAIU (ignoring, as you say, the system library exception). > > Some things to think on: > http://www.bitlaw.com/copyright/maskwork.html > > Someone has actually gone to the trouble of making a license for hardware: > http://technocrat.net/d/2007/2/5/14355 <-- Some interesting discussion > regarding a draft version of this license. > http://www.tapr.org/ohl.html <-- A page with the complete license (follow > the links on the top) > > Unfortunately the hardware license above is not aimed at HDL code according > to the author. > > Another hardware license is the one included in Opencores' DDR SDRAM > controller: http://www.opencores.org/projects.cgi/web/ddr_sdr/overview > (Unfortunately I cannot link directly to the license file as Opencores now > requires you to register to look at files in the CVS repository.) > I'm not sure how much thought that went into the creation of this license > and I'm therefore not willing to use it myself without reading the opinion > of a lawyer about it. > > > My personal belief is that there might be some problems with GPL as a license > for HDL code. On the other hand, Sun has released OpenSparc under the GPL > which I see as a clear indication that the GPL is a viable license for > hardware. See http://www.opensparc.net/faqs/licensing/ for what they think > this means in a hardware design. (They are using GPLv2 at the moment.) > Sun is a company with a long history of love/hate relationships with open source and licenses, so their choices are never a good indication of anything. On the one hand they will donate a great deal of code and resources to open source projects like Open Office - on the other hand, they released the ZFS code under their own CDL license making it open source and yet unusable with the Linux kernel. The choice of the GPL for the OpenSparc is similar - it effectively restricts its use to evaluation and academic work.Article: 134830
Petter Gustad wrote: > Why does Quartus run with lowest priority level (19) under Linux? It > also seems like if you nice quartus_sh to some higher priority when > you start it the sub-processes (like qartus_map etc) will still have > priority 19. I find this a little odd. Is there a reason for this? > I'd imagine the idea is that you can continue working with other programs while the long-running processes run in the background. Modern Linux kernels typically have schedulers that automate this (giving higher priority to short-running interactive processes), but there is no harm in running something like Quartus at low priority unless you are simultaneously running another process that tries to use all available processing time.Article: 134831
On 2008-09-03, David Brown <david@westcontrol.removethisbit.com> wrote: > Sun is a company with a long history of love/hate relationships with > open source and licenses, so their choices are never a good indication > of anything. What I meant was that Sun's choice is a clear indication that they expect the GPL to work correctly for hardware even though it is originally designed as a copyright license for software. /AndreasArticle: 134832
>=A0The choice of the GPL > for the OpenSparc is similar - it effectively restricts its use to > evaluation and academic work Not if they used the LGPL, it isn't. JonArticle: 134833
On Tue, 2 Sep 2008 05:24:00 -0700 (PDT), "jack.harvard@googlemail.com" <jack.harvard@googlemail.com> wrote: >Hi, > >I wrote a dual-port ram model according to xst example, it should be >inferred to a dual-port block ram with both ports writable at the same >time but different addresses. However, I got an error msg - "You are >apparently trying to describe a RAM with several write ports for >signal <x>. This RAM cannot be implemented using distributed >resources." Any hints what might have gone wrong? thanks, Focus on this: "This RAM cannot be implemented using distributed resources". There is apparently something about your template (or its interaction with XST) that prevents this RAM being mapped into BlockRams. I can't help with details, I don't do Verilog. But search for DPRAM template examples that do work, or try some basic variations, e.g. combining both "if" clauses into the same clocked process, or assigning doa<=dia inside the write clause, to see if you can get past this block. - BrianArticle: 134834
On Wed, 3 Sep 2008 00:10:58 -0700 (PDT), Qingbo <qingbow@gmail.com> wrote: >one can generate on a Virtex-5 device? > >Thanks, >Qingbo More than you can connect to external memory. How many I/O pins do you have? - BrianArticle: 134835
> That is almost an exact description of the system used on Altera's NIOS
> development kits - and probably thousands of other designs.
Also see:
http://www.xilinx.com/support/documentation/application_notes/xapp079.pdf
(July 2000)
Article: 134836On Sep 3, 1:10=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 2 Sep 2008 05:24:00 -0700 (PDT), "jack.harv...@googlemail.com" > > <jack.harv...@googlemail.com> wrote: > >Hi, > > >I wrote a dual-port ram model according to xst example, it should be > >inferred to a dual-port block ram with both ports writable at the same > >time but different addresses. However, I got an error msg - "You are > >apparently trying to describe a RAM with several write ports for > >signal <x>. This RAM cannot be implemented using distributed > >resources." Any hints what might have gone wrong? thanks, > > Focus on this: "This RAM cannot be implemented using distributed > resources". > There is apparently something about your template (or its interaction > with XST) that prevents this RAM being mapped into BlockRams. > > I can't help with details, I don't do Verilog. But search for DPRAM > template examples that do work, or try some basic variations, e.g. > combining both "if" clauses into the same clocked process, =A0or assignin= g > doa<=3Ddia inside the write clause, to see if you can get past this block= . > > - Brian It looks that a "feature" of XST, the template won't be synthesized to dual-port rams with both writes http://www.xilinx.com/support/answers/22385.htm No matter how I try. =3D=3D=3DFrom Xilinx=3D=3D=3D Dual-port RAM support is only for Virtex-2 Pro families and newer, and is not intended for older devices. If you target one of the newer devices, the correct type of RAM is inferred. To work around the issue, you can either instantiate the block RAM primitive that you want to use, or use CORE Generator to generate the RAM.Article: 134837
Hi All, The TimingAnalyzer is a program that can be used for drawing timing diagrams and performing timing analysis. There is a free version that anyone can use and a commercial version planned. You can download and use it now. I was announcing updates on this newsgroup hoping to find beta testers which worked but more beta testers are needed. If your interested in helping with the effort, please let me know. You can read all about it and download it from: www.timing-diagrams.comArticle: 134838
Hi,
I coded a very simple state machine (verilog code below).
The state machine has the "default" condition; this should ensure that
if an illegal state is reached, the machine will recover and go back
to a legal state.
I synthesized it with Xilix XST (ISE 9.2) with the Encoding option one-
hot.
I really suspect that the synthesis does not handle properly the
illegal states; for instance looking at the RTL schematics or the
technolgy schematics generated by ISE: if I assume that there is an
illigal state like "000" I see that the machine will stay there
forever.
Is there any more formal way to prove it (to myself and to the xilinx
support) other than a visual inspection of the schematic ?
Simulation (with xilix simulator) is not easy because in simulation
the machine will never go to an illigal state.
But I suspect that is what happens very rarely on my real hardware
(and this is costing me a lot).
Thanks,
Tullio
//////////////////////////////////////////////////////
`timescale 1ns / 1ps
module I2D_State (
input clk, Er, DV,
output reg I2D );
reg [2:0] I2D_State = 3'b001;
// Detect a transition of (Er, DV) from (0, 0) to (0, 1)
always @(posedge clk) case(I2D_State)
3'b001: begin
I2D <= 0;
if (~Er & ~DV) I2D_State <= 3'b010; // (0, 0) detected
end
3'b010: if (~Er & DV) begin
I2D_State <= 3'b100; // (0, 1) detected
I2D <= 1;
end // else do nothing, regs will keep their values.
3'b100: begin
I2D_State <= 3'b001; // stay only 1 tick in this state.
I2D <= 0;
end
default: I2D_State <= 3'b001;
endcase
endmodule
/////////////////////////////////////////////
Article: 134839XST-Guide: "XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine enters an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode. To activate Safe FSM implementation: [...] " Did you really "activate" Safe FSM implementation ? I (personally) wouldn't like to activate it on a 1-hot FSM, as it intoduces "a lot" of additional ressources... Regards JochenArticle: 134840
On Sep 3, 7:21=A0am, "jack.harv...@googlemail.com" <jack.harv...@googlemail.com> wrote: <snip> > Dual-port RAM support is only for Virtex-2 Pro families and newer, and > is not intended for older devices. If you target one of the newer > devices, the correct type of RAM is inferred. <snip> What device are you working with? V2Pro is getting a bit long in the tooth by now.Article: 134841
On 3 Sep, 16:54, John_H <newsgr...@johnhandwork.com> wrote: > On Sep 3, 7:21=A0am, "jack.harv...@googlemail.com"<jack.harv...@googlemai= l.com> wrote: > > <snip>> Dual-port RAM support is only for Virtex-2 Pro families and newer= , and > > is not intended for older devices. If you target one of the newer > > devices, the correct type of RAM is inferred. > > <snip> > > What device are you working with? =A0V2Pro is getting a bit long in the > tooth by now. It's a Spartan3A.Article: 134842
Your state machine should never get into an "illegal state" regardless of what it does if you are operating in a "standard" environment (ie, not in space, in a nuclear reactor, or in the engine bay of a car). If it is getting into such a state, your design breaks synchronous design principles. Adding in a default case to try to "fix" that is at best fixing a symptom instead of the cause and at worse could break your system. Are you sure your system actually could tolerate randomly going into your default state? I suspect the inputs to your state machine are not actually synchronized into the state machine's clock domain. If you are currently using a synchronizer, ensure that the delay between the first and second flip-flops is as little as possible. At very high frequencies, it is possible that the routing delay between the two flip-flops in a synchronizer plus the possible metastable delay in your synchronizer can exceed one clock cycle. As an aside, if you are actually operating in an extreme environment and do need to consider state corruption due to particle-induced events, you can actually force the state machine into an illegal state since you're using Verilog. Just do a gate-level simulation and use the Verilog "force" keyword to override the state variable into what you want it to be. This can be useful to see if your system actually will survive going to the default case.Article: 134843
tullio wrote: > Hi, > > I coded a very simple state machine (verilog code below). > The state machine has the "default" condition; this should ensure that > if an illegal state is reached, the machine will recover and go back > to a legal state. An "extracted" FSM won't be "safe" unless you specify a safe option or explicitly code it and turn off the FSM extraction mode. But there is no reason for an FSM to be safe unless you expect metastability or alpha particle hits. Making the FSM safe requires a lot of extra logic and a decrease in speed. -KevinArticle: 134844
On Wed, 3 Sep 2008 08:00:31 -0700 (PDT), tullio
<tullio.grassi@gmail.com> wrote:
>Is there any more formal way to prove it (to myself and to the xilinx
>support) other than a visual inspection of the schematic ?
>Simulation (with xilix simulator) is not easy because in simulation
>the machine will never go to an illigal state.
Yes... simulate it properly! Use a 'force' statement to set your state
register to an illegal value, clock it, see what happens.
Of course, this is hard work, it's pretty tedious, it looks a lot like
programming, and you're much more likely to make a mistake in your
testbench than your RTL. So, I've gone to the trouble of doing it for
you. Testbench attached below; you'll notice that it tests the entire
FSM, rather than just the illegal state exit.
The good news is that your RTL works. save the code below to
'test1.tv', save your own code as 'test.v', and run rtv:
# rtv test1.tv test1.v
(Log) (150 ns) 15 vectors executed (22 passes, 0 fails)
As a sanity check, change the expected output value in the last
statement from 0b001 to 0b111, and rtv's output changes to:
# rtv test1.tv test1.v
(Error) ('test1.tv', line 36, 149 ns) 'top.I2D_State.I2D_State':
expected 'b111; got 'b001
(Log) (150 ns) 15 vectors executed (21 passes, 1 fails)
Now get a Verilog netlist out of XST, and repeat the test with the
netlist rather than 'test1.v'. If the test now fails, XST is broken.
You can get rtv from www.maia-eda.net.
-Evan
[and yes, this *is* a plug for Maia; couldn't help myself. The code
below is trivial; it gets much better than this].
=============================================================
test code: watch out for line wrapping; some of the comments
may appear to be on a second line
DUT {
module I2D_State( // declare the module
input clk, Er, DV,
output reg I2D);
signal(inout [2:0] I2D_State); // declare any internal sigs to
test
// declare any clocks, and any vectors
create_clock clk;
[clk, I2D_State, Er, DV] -> [I2D_State, I2D];
}
// no FSM reset, so force to a known state, and check transition from
3`b001
[.C, 0b001, 1, 1] -> [0b001, 0]; // force the state register
[.C, .R, 1, 1] -> [0b001, 0]; // release the state register
[.C, -, 1, .X] -> [0b001, 0]; // leave the state register
undriven
[.C, -, .X, 1] -> [0b001, 0];
[.C, -, 0, 0] -> [0b010, 0];
// transition from 3`b010
[.C, -, 1, .X] -> [0b010, 0];
[.C, -, .X, 0] -> [0b010, 0];
[.C, -, 0, 1] -> [0b100, 1];
// transition from 3`b100
[.C, -, .X, .X] -> [0b001, 0];
// force to an illegal state, check exit
[.C, -, .X, .X] -> [-, -]; // flush: see FAQ
[.C, 0b000, .X, .X] -> [0b000, -]; // force the state register to 0
[.C, .R, .X, .X] -> [0b001, -]; // confirm that we recover to
0b001
// try another illegal state
[.C, -, .X, .X] -> [-, -]; // flush: see FAQ
[.C, 0b111, .X, .X] -> [0b111, -]; // force the state register to
0b111
[.C, .R, .X, .X] -> [0b001, -]; // confirm that we recover to
0b001
======================================================================
Article: 134845I am trying to look for information on the "Spartan-3A FPGA Starter Kit Board User Guide" and other sites regarding to this problem I am having. One of the requirements of my program is to display a number, each second, on the Spartan-3A LCD. I see that some LEDs are flashing, while the LCD shows the numbers. I have not commanded that in the program. I understand that this must be happening because something is failing (perhaps because of the way I described the circuit/programmed). My question is: Do you know where can I find information that tells, for example, what means an 'on' LED0 and/or LED3, from time to time, while the LCD is showing the characters? Thank you, m mArticle: 134846
Evan Lavelle wrote:
> On Wed, 3 Sep 2008 08:00:31 -0700 (PDT), tullio
> <tullio.grassi@gmail.com> wrote:
...
>
> The good news is that your RTL works....
>
> Now get a Verilog netlist out of XST, and repeat the test with the
> netlist rather than 'test1.v'. If the test now fails, XST is broken.
> ...
If XST doesn't pass the test, that doesn't mean it is broken in this
case. An extracted FSM is not supposed to be identical to RTL. That is
the whole idea of FSM extractors. They take the RTL and recode it,
possible using a different encoding, and also removing logic related to
moving to a default state. You can turn off the extractor, but you
wouldn't want to.
Here's an example. These two counters operate in the same way:
reg [7:0] count1=0, count2=0;
always@(posedge clk)
begin
if (count1==135) count1 <= 0;
else count1 <= count1 + 1;
if (count2>134) count2 <= 0;
else count2 <= count2 + 1;
end
You can see that both counters are identical, but if synthesized
according to the RTL, count2 will have a lot more logic and will be
slower, because the > with synthesize a subtractor. But it's just a
waste of logic, because count2 will never have a value of 136 or
greater, unless there is an alpha hit or setup violation from a too-fast
clock. You actually want the synthesizer to realize this and violate
the RTL during synthesis.
-Kevin
Article: 134847tullio wrote: > Hi, > > I coded a very simple state machine (verilog code below). > The state machine has the "default" condition; this should ensure that > if an illegal state is reached, the machine will recover and go back > to a legal state. > I synthesized it with Xilix XST (ISE 9.2) with the Encoding option one- > hot. > I really suspect that the synthesis does not handle properly the > illegal states; for instance looking at the RTL schematics or the > technolgy schematics generated by ISE: if I assume that there is an > illigal state like "000" I see that the machine will stay there > forever. > Is there any more formal way to prove it (to myself and to the xilinx > support) other than a visual inspection of the schematic ? > Simulation (with xilix simulator) is not easy because in simulation > the machine will never go to an illigal state. > But I suspect that is what happens very rarely on my real hardware > (and this is costing me a lot). Your example seems to have only 3 active states, so one way to be sure, is to explicitly code the unwanted states. You can chose a simple binary code, which gives one more illegal state, or one-hot, which gives 5 more to cover. Also watch Reset exit : that is usually chosen as a 'safe' state. -jgArticle: 134848
> > More than you can connect to external memory. > > How many I/O pins do you have? > > - Brian I am thinking to use all left I/O pins for DRAM access, maybe about 500 on a LX110. Thanks,Article: 134849
Svenn, Try using SmartGuide for incremental place and route. http://toolbox.xilinx.com/docsan/xilinx9/help/iseguide/html/ise_using_smart= guide.htm On Sep 2, 10:09=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > Svenn Are Bjerkem wrote: > > In a fairly large design I am doing some debugging on the system board > > directly. When I discover a mistake and modify the vhdl code, the > > whole design goes through synthesis and place-and-route. Many parts of > > the design are never touched by my modifications, and I wonder if it > > is possible to speed up the debug-modify-compile > > I finish the debug-modify-compile loop in simulation. > Even though simulation requires significant time on the front end, > debugging typos and changes is quick and straightforward. > > =A0 =A0 =A0 =A0-- Mike Treseler
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