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Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? The CS pin, according to the docs, should be connected to high logic level. I have connected all VCCO to 3.3V. Anyone?Article: 135001
Your Lordship, "lordsathish" <lordsathish@gmail.com> wrote in message news:e83b20be-1aaf-41c7-9117-2444c9f686da@b38g2000prf.googlegroups.com... > Hi all.... > Can Soft microprocessor like microblaze, nios replace DSP > processors...? Not in your case, sunshine. Anyone who apparently uses a very poorly defined usenet post as their first port of call in their research, is clearly destined to FAIL, so there's no point in helping. > Or is there any soft DSP processor...? STW Read this, it might help you. http://catb.org/~esr/faqs/smart-questions.html Syms.Article: 135002
>Hi all.... >Can Soft microprocessor like microblaze, nios replace DSP >processors...? Not for computationally-intensive DSP tasks. >Or is there any soft DSP processor...? No free one that I can recommend. Others may know better. >Thanks >Article: 135003
> I'm quite curious about your timing constraint information. =A0I spent > time on the weekend trying to find out how to do that, but the Xilinx > docs, IMHO, are just as bad as their software -- and I couldn't find > anything useful. does THIS help ? http://toolbox.xilinx.com/docsan/xilinx10/books/docs/cgd/cgd.pdf http://toolbox.xilinx.com/docsan/xilinx10/books/docs/qst/qst.pdf /JochenArticle: 135004
On 09 Sep 2008 20:56:04 -0700, thutt <thutt151@comcast.net> wrote: >"Alessandro" <apoppi@email.it> writes: > >> thutt wrote: >> >> > All the I/O is actually constrained, but I have not done anything with >> > timing yet. I guess I'll try to check out information about timing. >> > Thanks for the info. Hopefully this will pan out. >> >> NET clk_pin TNM_NET = clk_ref_grp; >> TIMESPEC TS01 = PERIOD : clk_ref_grp : 20.00 : PRIORITY 1; # 50.00 MHz >I'm quite curious about your timing constraint information. I spent >time on the weekend trying to find out how to do that, but the Xilinx >docs, IMHO, are just as bad as their software -- and I couldn't find >anything useful. > >Where did you find this information about 'NET clk_pin'? To what do >you add it? In the VHDL? In the user constraints? I try to avoid >using ISE as much as possible, so please tell me what document you >found this information in, and then I think I can extrapolate to how >to control the command line programs (which I drive from a Makefile). You can add most constraints in either the VHDL code or the user constraints. In practice things like pin allocations and timing constraints are usually best added in the user constraint file (.ucf) which is easily handled in a text editor. It's as important to your project as the VHDL files, whether you are using the GUI or the command line. (This keeps the VHDL cleaner and more portable for one thing. There are a few valid uses for constraints in the VHDL code, but IMO no essential ones. If you're curious, google for "Death of the RLOC") It's not a bad idea to try the graphical constraints tool - once - for adding a few constraints then use these as prototypes for the rest. Or reading the .ucf for sample projects. Also build the project once using the GUI, look for the "command_log" file, and extract command lines from it. - BrianArticle: 135005
Brian Drummond wrote: > > If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5) > for most FPGAs you just use the * operator and expect the tools to use > the in-built multipliers. > > For more details, read the documentation on these multiplier or DSP48 > blocks. > > For larger operators, this works well enough as long as you don't need > the highest achevable speeds (maybe this is fixed in ISE 10?). If you follow the multiply with several plain old register stages, the synthesis tool will properly absorb the registers into a pipelined structure (at least, XST with ISE9 will).Article: 135006
On Tue, 9 Sep 2008 21:49:03 +0200, "Alessandro" <apoppi@email.it> wrote: |james wrote: | |> Add $20 tothe base price and you get a XC3S1200 instead of the XC3S500 |> onthe NEXYS 2 board. Then you will have more than enough room for a |> dual port SDRAM controller. I would still believe that the ZX would |> fit well into the XC3S500 with a dualport SDRAM controller. | |I took a look at the micron psdram's datasheet; I suppose a dualport sdram |controller is a piece of logic that translates an asynchronous access |(microprocessor side) to a synchronous one (ram side). | |--------- A dual port SDRAM controller will allow two outside devices/processes access to the same ram ie, microprocessor and video processor or what other device that needs access to memory. The interface to each port can be very simple or even made to look as if the device/process is accessing static ram. All depends on how much code you want to write and above and beyond thebasic SDRAM controller. |You're not talking about using the blockram as a dualport cache, are you? No. jamesArticle: 135007
On 10 Sep, 07:19, lordsathish <lordsath...@gmail.com> wrote: > Hi all.... > Can Soft microprocessor like microblaze, nios replace DSP > processors...? With custom instructions - yes. > Or is there any soft DSP processor...? Yes - http://www.ceva-dsp.com/ JonArticle: 135008
On Sep 10, 4:49 am, "Symon" <symon_bre...@hotmail.com> wrote: > Your Lordship, > > "lordsathish" <lordsath...@gmail.com> wrote in message > > news:e83b20be-1aaf-41c7-9117-2444c9f686da@b38g2000prf.googlegroups.com... > > > Hi all.... > > Can Soft microprocessor like microblaze, nios replace DSP > > processors...? > > Not in your case, sunshine. Anyone who apparently uses a very poorly defined > usenet post as their first port of call in their research, is clearly > destined to FAIL, so there's no point in helping. > > > Or is there any soft DSP processor...? > > STW > > Read this, it might help you.http://catb.org/~esr/faqs/smart-questions.html > > Syms. Moron...Article: 135009
On Tue, 9 Sep 2008 09:27:28 -0700 (PDT), bgong86@gmail.com wrote:
|The FPGA editor does list each element with the <> instead of the [].
|I had wondered about that myself and tried using the other symbols
|(i.e. count_a<0>) but with no success. Has anyone been successful
|doing RPM with busses and have an example of the correct syntax?
|
|Brian
|---------------
In ISE Webpack under Synthesize Properties under synthesis options is
bus delimiter. You can change it from the default <> to {},[] or ().
james
Article: 135010On Tue, 9 Sep 2008 15:28:12 -0700 (PDT), KJ <lkjrsy@gmail.com> wrote: |Hello everyone. | |I try to implement an image processing in Virtex5. But What I have now |is ISE7.1i. |I think that it's not working for Virtex5. So is there anyone who can |tell me what version of ISE is ok with Virtex5 | |Thank you for reading. |============= Per Xilinx webpage: ISE Webpack 8.2i and 9.1i supports the LX30 only. 9.2i supports the LX30/T and LX50/T. Version 10 supports all of the Virtex 5. jamesArticle: 135011
On Wed, 10 Sep 2008 09:49:04 +0100, "Symon" <symon_brewer@hotmail.com> wrote: |Your Lordship, | |"lordsathish" <lordsathish@gmail.com> wrote in message |news:e83b20be-1aaf-41c7-9117-2444c9f686da@b38g2000prf.googlegroups.com... |> Hi all.... |> Can Soft microprocessor like microblaze, nios replace DSP |> processors...? | |Not in your case, sunshine. Anyone who apparently uses a very poorly defined |usenet post as their first port of call in their research, is clearly |destined to FAIL, so there's no point in helping. | |> Or is there any soft DSP processor...? | |STW | |Read this, it might help you. |http://catb.org/~esr/faqs/smart-questions.html | |Syms. | |++++++++++++++++++ Oh no the internet question police has struck!!!!!! Be afraid! Be very afraid! :) jamesArticle: 135012
Pablo, I would first try to remove the location constraint, although it sounds from the answer record that it won't be enough and this IDELAYCTRL has to be removed. In that case you will need to comment out the IDELAYCTRL instantiation. The fact that IDELAY blocks are instantiated only means that IDELAYCTRL(s) is/are required, but it/they have to be located in the right place on the die. The tools are probably smart enough to instantiate the required IDELACTRL blocks but not smart enough to ignore user's instantiations or something like that. You will probably need to search through the coregen generated source files to find the troubling instantiation and the location constraint unless it is in the ucf file, but I guess it is in the source... Hopefully there is a source... If all you have is a netlist, then try using the script mentioned in the answer record. /Mikhail "rao" <raonpc@gmail.com> wrote in message news:bc66df26-c640-47c4-8092-3c1f617ec29f@25g2000prz.googlegroups.com... > Hi > > I am using a pci core(generated from coregen, with version v4.3) in > my design. Till now i was succesfully implementing in ISE9.1i. I > started to migrate my design to ISE10.1i and I am receiving IDELAYCTRL > locking problems (Xilinx changed locking approach in ISE10.1i). > > Here's one solution they are pointing to.. > http://www.xilinx.com/support/answers/30966.htm > > The error is as below.. > ---------------------------------- > ERROR:Place:1064 - The delay controller "PCI_CORE/XPCI_IDC0" has > been locked > with the following location constraint:COMP "PCI_CORE/XPCI_IDC0" > LOCATE = SITE "IDELAYCTRL_X0Y2" > LEVEL 1 > However, none of the delay elements calibrated by this controller > are being used. The delay controller should be removed from the > design. Please correct your design and rerun. For more details, please > search the Xilinx Answers Database at > http://www.xilinx.com/support/answers/index.htm. > ----------------------------------- > > As the errors says "none of the delay elements calibrated by this > controller are being used" -- I don't > understand this. I use synplify and checked the synthesized > netlist(rtl view and technology view) and I see IODELAY blocks > instantiated. > > Any help is appreciated. > > Thanks > Pablo > > >Article: 135013
Hiya folks, maybe somebody with more experience with all this can help me out. I'm trying to get into GAL/CPLD types of technology, and found that the ATF1500 series from Atmel is interesting, since it's programmable in-circuit without the added cost of a programmer. But before I buy anything I wanted to fiddle around with making files with their WinCupl program to make sure it can do the sorts of things I have in mind (and just to make sure I can actually figure it out!). Well, the problem is, whenever I tried to simulate anything I make for that chip, I get warnings. In the test.so file that I get after compiling, I get many lines of: [0033sa] Please note: jedec vectors cannot be created with undefined pin numbers Some of the lines are also followed by pin names I gave in my .PLD file. The .SI file never gets generated. I thought I was doing something wrong, so I went to look in the example source files that come with WinCupl and tried to compile/simulate those, but oddly enough, I get the same warning from them. What's odder is that if I specify the older chips for the design, just plain GALs for example, this doesn't happen. I tried to build stuff from the command line instead, to see if it was giving any errors there that I wasn't seeing in the GUI. I can compile it fine, just like in WinCupl, but I can't even get csim to run as far as it does in the GUI. It tells me this every time: [0001sk] could not open: &.abs I'd much appreciate any light anyone can shed on these issues!Article: 135014
On Sep 10, 7:14=A0am, "MM" <mb...@yahoo.com> wrote: > Pablo, > > I would first try to remove the location constraint, although it sounds f= rom > the answer record that it won't be enough and this IDELAYCTRL has to be > removed. In that case you will need to comment out the IDELAYCTRL > instantiation. The fact that IDELAY blocks are instantiated only means th= at > IDELAYCTRL(s) is/are required, but it/they have to be located in the righ= t > place on the die. The tools are probably smart enough to instantiate the > required IDELACTRL blocks but not smart enough to ignore user's > instantiations or something like that. > > You will probably need to search through the coregen generated source fil= es > to find the troubling instantiation and the location constraint unless it= is > in the ucf file, but I guess it is in the source... Hopefully there is a > source... If all you have is a netlist, then try using the script mention= ed > in the answer record. > > /Mikhail > > "rao" <rao...@gmail.com> wrote in message > > news:bc66df26-c640-47c4-8092-3c1f617ec29f@25g2000prz.googlegroups.com... > > > > > Hi > > > =A0I am using a pci core(generated from coregen, with version v4.3) in > > my design. Till now i was succesfully implementing in ISE9.1i. I > > started to migrate my design to ISE10.1i and I am receiving IDELAYCTRL > > locking problems (Xilinx changed locking approach in ISE10.1i). > > > =A0Here's one solution they are pointing to.. > > =A0http://www.xilinx.com/support/answers/30966.htm > > > =A0The error is as below.. > > =A0---------------------------------- > > =A0ERROR:Place:1064 - The delay controller "PCI_CORE/XPCI_IDC0" has > > been locked > > =A0with the following location constraint:COMP "PCI_CORE/XPCI_IDC0" > > LOCATE =3D SITE "IDELAYCTRL_X0Y2" > > =A0 LEVEL 1 > > =A0 However, none of the delay elements calibrated by this controller > > are being used. The delay controller should =A0 be removed from the > > design. Please correct your design and rerun. For more details, please > > search the Xilinx Answers Database at > >http://www.xilinx.com/support/answers/index.htm. > > =A0----------------------------------- > > > =A0As the errors says "none of the delay elements calibrated by this > > controller are being used" -- I don't > > =A0understand this. I use synplify and checked the synthesized > > netlist(rtl view and technology view) and I see IODELAY blocks > > instantiated. > > > =A0Any help is appreciated. > > > Thanks > > Pablo- Hide quoted text - > > - Show quoted text - Thanks HTH and Mikhail.Article: 135015
"TehPron" <spamgoeshere9@yahoo.com> wrote in message news:cfac168f-89cb-4be5-9c52-83381983e32d@f63g2000hsf.googlegroups.com... > > Moron... Is that directed at me? If so, many thanks for your expert opinion. It's especially ironic to receive a rebuke from the guy who's apparently taken it upon himself to splatter usenet with replies to messages that he considers spam. I find it interesting that despite your enthusiastic, if somewhat irritating, personal crusade against spammers, you don't seem overly worried about folks posting questions about subjects on which they seem to have done absolutely no research whatsoever. I also notice you chose to not sign your post with your name. However, unless I'm mistaken, you appear to be posting from the same IP address as 'Rickman'. You know, the guy who has trouble multiplying negative numbers together (see 2nd link below). Is this a coincidence? http://groups.google.com/group/comp.arch.fpga/msg/87da3b0b4ada5e95?dmode=source http://groups.google.com/group/comp.lang.vhdl/msg/4e0566f1a5d75d52?hl=en&dmode=source Hugs and kisses, Syms. xxArticle: 135016
"james" <george@washington.edu> wrote in message news:qtkfc41rp279t350cld5dn0de2ltg1nqak@4ax.com... > |++++++++++++++++++ > > Oh no the internet question police has struck!!!!!! > > Be afraid! Be very afraid! :) > > james > Hi James, Fair enough. It just that sometimes the sheer selfishness of people's posts really get to me. The guy clearly never even bothered to enter the terms of his question into a search engine, yet expects folks who post here to help him out on a subject which is well covered both on the vendors' websites and in the archives of this newsgroup. And...excessive...use...of...bloody...ellipsises...wind...me...up... :-) Anyway, believe it or not, I was trying to help the guy ask better questions to get better answers. That link I posted has helped me many times. Cheers, Syms.Article: 135017
Could anyone recommend me some method to Load an application stored in External DDR Sdram without the use of XMD? PD: My board has not any Flash memory.Article: 135018
> Thanks HTH and Mikhail. HTH = Hope This Helps :)))Article: 135019
FyberOptic wrote:
> Hiya folks, maybe somebody with more experience with all this can help
> me out. I'm trying to get into GAL/CPLD types of technology, and
> found that the ATF1500 series from Atmel is interesting, since it's
> programmable in-circuit without the added cost of a programmer. But
> before I buy anything I wanted to fiddle around with making files with
> their WinCupl program to make sure it can do the sorts of things I
> have in mind (and just to make sure I can actually figure it out!).
>
> Well, the problem is, whenever I tried to simulate anything I make for
> that chip, I get warnings. In the test.so file that I get after
> compiling, I get many lines of:
>
> [0033sa] Please note: jedec vectors cannot be created with undefined
> pin numbers
>
> Some of the lines are also followed by pin names I gave in my .PLD
> file.
those are a 'software artifact', and are always generated.
The .SI file never gets generated. I thought I was doing
> something wrong, so I went to look in the example source files that
> come with WinCupl and tried to compile/simulate those, but oddly
> enough, I get the same warning from them. What's odder is that if I
> specify the older chips for the design, just plain GALs for example,
> this doesn't happen.
That is because the CPLD series use a fitter, and they use a Virtual
switch, when compiling .
The .SI file is YOUR file, it should not be created by the tools.
A typical SI file portion looks like this
ORDER:
ALE, %1,
CEN0,RDN,WRN, %1,
bAD2,bAD1,bAD0, %1,
DB7..DB0, %1,
oePa7..oePa0,%1,
Pa7..Pa0,%1,
SelPage,
;
VECTORS:
$msg " POR ";
0 111 *** 00000000 ******** ******** *
0 111 *** 00000000 ******** ******** *
$msg " Adr= 5, Write to DDRa";
0 011 *** 00000101 ******** ******** *
1 011 *** 00000101 ******** ******** *
The .SO file created looks like this
{MANY lines like this }
[0033sa] Please note: jedec vectors cannot be created with undefined pin
numbersoePc7
{Ignore those, and get to the important stuff...}
29: ORDER:
30: ALE, %1,
31: CEN0,RDN,WRN, %1,
32: bAD2,bAD1,bAD0, %1,
33: DB7..DB0, %1,
34: oePa7..oePa0,%1,
35: Pa7..Pa0,%1,
36: SelPage,
37: ;
38:
===============================================
S
e
oooooooo l
C bbb eeeeeeee P
A ERW AAA DDDDDDDD PPPPPPPP PPPPPPPP a
L NDR DDD BBBBBBBB aaaaaaaa aaaaaaaa g
E 0NN 210 76543210 76543210 76543210 e
===============================================
POR
0001: 0 111 LLL 00000000 LLLLLLLL ZZZZZZZZ H
0002: 0 111 LLL 00000000 LLLLLLLL ZZZZZZZZ H
Adr= 5, Write to DDRa
0003: 0 011 LLL 00000101 LLLLLLLL ZZZZZZZZ H
0004: 1 011 HLH 00000101 LLLLLLLL ZZZZZZZZ H
and the .JED file has this at the end, when 'append JED with vectors' is
enabled.
You DO need to have no floating pins for this step to work
(ie all pins must have PinNames)
You CAN float a design and then paste the Fitter Pin report block
straight back into CUPL, to quickly move from Float to Locked pins.
C9D44*
P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
*V0001 10N0ZZZXXNXXXXNXXZ000NNX00X0XNXXXXN0XZZZZN11
*V0002 10N0ZZZXXNXXXXNXXZ000NNX00X0XNXXXXN0XZZZZN11
*V0003 00N1ZZZXXNXXXXNXXZ010NNX00X0XNXXXXN0XZZZZN11
*V0004 01N1ZZZXXNXXXXNXXZ010NNX00X0XNXXXXN0XZZZZN11
>
> I tried to build stuff from the command line instead, to see if it was
> giving any errors there that I wasn't seeing in the GUI. I can
> compile it fine, just like in WinCupl, but I can't even get csim to
> run as far as it does in the GUI. It tells me this every time:
>
> [0001sk] could not open: &.abs
>
> I'd much appreciate any light anyone can shed on these issues!
This is the batch line we use, for CUPL from an editor
cupl -m1lxfjnabes -u \WinCUPL\shared\atmel.DL %1%2.PLD
and IIRC we also replace the shared\find1502.exe, with
Fit1502.exe renamed as Find1502.exe (that removes one level of
indirection, and puts all the engine-room exe's into the same
directory )
It will then run on a Flash drive.
hth
-jg
Article: 135020thutt wrote: >> NET clk_pin TNM_NET = clk_ref_grp; >> TIMESPEC TS01 = PERIOD : clk_ref_grp : 20.00 : PRIORITY 1; # 50.00 >> MHz > I'm quite curious about your timing constraint information. I spent > time on the weekend trying to find out how to do that, but the Xilinx > docs, IMHO, are just as bad as their software -- and I couldn't find > anything useful. > > Where did you find this information about 'NET clk_pin'? To what do > you add it? In the VHDL? In the user constraints? I try to avoid All the statements are in the .ucf file. The "clk_pin" is just the name of the signal attached to the 50MHz clock oscillator, specified in a pin constraint in usual way: NET "clk_pin" LOC = "C9" | IOSTANDARD = LVCMOS33 ; The constraint just tells that this is a 50MHz clock. I don't know exactly how it works (and I'll certainly read the two links provided by Jochen), I just copied the first one from a fpgaarcade source code (asteroids, if I remember). I made the second (75MHz) by myself, recalculating timings with the ratio of 50 to 75 (the difference in frequency). clk_pll is the name of an internal signal clock, not a physical pin. I'm not really sure that using "TS01" twice is a good practice, I have to learn about it. > using ISE as much as possible, so please tell me what document you > found this information in, and then I think I can extrapolate to how > to control the command line programs (which I drive from a Makefile). I found it in the source code of an fpgaarcade game. You will find similar things in many xilinx projects (for example the default picoblaze project, flashed into the board as a factory default and downloadable from the xilinx site): this is what's inside it's .ucf file: NET "clk" LOC = "C9" | IOSTANDARD = LVTTL; # Period constraint for 50MHz operation NET "clk" PERIOD = 20.0ns HIGH 50%; > 75MHz? On a Spartan 3E board? What pin is that? Do you have the > UCF name? The spartan fpga has some "DCM" units (digital clock managers) which will generate almost any frequency you need, starting from a given clock source (50MHz in our case). A dcm will multiply then divide the frequency in a very flexible way. You can create an instance for a dcm by running the "Core Generator" under the ISE/Accessories program group or, inside ISE, by adding a source file to the project then selecting "IP Coremanager" instead of, for example, a new .vhd file). You then select "fpga features and design" then "clocking" then the fpga family then "single DCM_SP, then "customize". The clock manager can simply shift the input clock by 90, 180, 270 degrees or generate a different frequency. For the latter, you should check the box "CLKFX" (it is a pin on the drawn component on the screen). You input the osc clock (50MHz) and the desired output frequency, then the gui will calculate the parameters and tell if it could be done or not. For example, the zx-badaloc project runs at 85MHz generated by a dcm with *17 multiply then /10 divide (50*17/10 = 85). You can easily obtain a 300MHz clock by multiplying by 6 the 50MHz input clock. Then, the gui generates a "component" and a wrapper to be placed in the project. I remember I've had problems launching from inside ISE so I prefer starting the core manager from the start menu, as described above. The wrapper for my 85MHz clock was: COMPONENT pll PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; then the "connections" to my signals: -- PLL mainpll: pll PORT MAP( CLKIN_IN => clk_pin, -- oscillatore clock 50MHz CLKFX_OUT => clk_pll -- clock sintetizzato 85MHz ); Ciao! AlessandroArticle: 135021
lordsathish <lordsathish@gmail.com> wrote: >Hi all.... >Can Soft microprocessor like microblaze, nios replace DSP >processors...? >Or is there any soft DSP processor...? >Thanks That depends on what you want to do (performance). I've used Xlinx's picoblaze for DSP functions several times. Some dedicated logic for stuff like linear to a-law conversion and multiplication helps a lot. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135022
> In ISE Webpack under Synthesize Properties under synthesis options is
> bus delimiter. You can change it from the default <> to {},[] or ().
Thanks, James, that's good to know. However, I'm still trying to
figure out the correct RPM syntax for busses in Verilog. Changing the
bus delimiter option didn't helped the RPM code to get used in the
design. Anymore ideas?
Brian
Article: 135023lordsathish <lordsathish@gmail.com> writes: > Can Soft microprocessor like microblaze, nios replace DSP > processors...? Yes. > Or is there any soft DSP processor...? Yes.Article: 135024
"Alessandro" <apoppi@email.it> wrote in message news:ga6lv4$e0a$1@aioe.org... > Take a look at this waveforms, captured on real hardware (my xilinx 3E Thanks for that, and the write up. You're having way more fun than I am this moment. >> I think I saw 10ns 1Mx8 TSSOP SRAM not very long ago for < $20. A >> quick look through DigiKey should answer that pretty quickly. > > I think I may go on both sides. I think I will find a PQ208 board and add > a static ram, but I'd also like to experiment with the psdram on the > nexys2. I will probably be seeking for both. I recall now where and why I was shopping that. Avnet sells a great little $40 card with an S3-400A and PSOC/USB2. It doesn't come with any RAM, and not enough I/O on the headers if I put the memory there. It might be worth a quick look for your needs. The price would be unbeatable if you can fit inside its pin budget.
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