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Messages from 131975

Article: 131975
Subject: AHB and APB master VHDL generator
From: "beky4kr@gmail.com" <beky4kr@gmail.com>
Date: Fri, 9 May 2008 00:01:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
This project demonstrates an easy way to create AMBA masters and
slaves. It includes an AHB master, AHB slave, APB master and APB
slave.
http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html

Article: 131976
Subject: SDIO CRC7 + VCD waves
From: "beky4kr@gmail.com" <beky4kr@gmail.com>
Date: Fri, 9 May 2008 00:03:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
The SDIO standard defines two kinds of CRC. CRC7 for command and CRC16
for data. This code is a CRC7. The module is checked via a SDIO
generator. The SDIO slave is capable only in responding to the first
few commands during initialization. VCD waves of the entire design
will be supplied as well.
http://bknpk.no-ip.biz/SDIO/CRC7.html

Article: 131977
Subject: Re: SDIO CRC7 + VCD waves
From: Alain <no_spa2005@yahoo.fr>
Date: Fri, 9 May 2008 00:14:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 9 mai, 09:03, "beky...@gmail.com" <beky...@gmail.com> wrote:
> The SDIO standard defines two kinds of CRC. CRC7 for command and CRC16
> for data. This code is a CRC7. The module is checked via a SDIO
> generator. The SDIO slave is capable only in responding to the first
> few commands during initialization. VCD waves of the entire design
> will be supplied as well.http://bknpk.no-ip.biz/SDIO/CRC7.html

Your home page "http://bknpk.no-ip.biz/" has some virus
"Worm.Win32.Fujack.al" ....

Article: 131978
Subject: 5 V oscillator output to GCLK
From: maverick <sheikh.m.farhan@gmail.com>
Date: Fri, 9 May 2008 01:01:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator
which gives clk output at 5V p-p swing.  I am using the FPGA in LVTTL
mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to
one of the GCLK pins of the Spartan 3 FPGA? Should I put a current
limiting resistor in the clock path before I feed it to the GCLK pin?
Any issues with that?

Best Wishes,
Farhan

Article: 131979
Subject: Re: AHB and APB master VHDL generator
From: Guru <ales.gorkic@email.si>
Date: Fri, 9 May 2008 01:32:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 9, 9:01=A0am, "beky...@gmail.com" <beky...@gmail.com> wrote:
> This project demonstrates an easy way to create AMBA masters and
> slaves. It includes an AHB master, AHB slave, APB master and APB
> slave.http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html

Fu...off, you have a virus on the server.

Article: 131980
Subject: Xilinx Platform USB Cable II
From: Clemens <Clemens@hotmail.com>
Date: Fri, 09 May 2008 11:32:20 +0100
Links: << >>  << T >>  << A >>
Hi

I have intended an upgrade to Xilinx 9.2 or higher from version 7.1.
With this newer versions my programming cable is no longer supported.
So I am thinking of buying a Xilinx Platform USB Cable II. I wonder if
there is a backwards compatibility so that I could use it with the 7.1 
version if the worst comes to the worst? Especially if it is compatible 
with Chipscope 7.1 because I havent seen a free webpackage for this 
software tool yet!

Many thanks,
Clemens

Article: 131981
Subject: Re: AHB and APB master VHDL generator
From: sky465nm@trline4.org
Date: Fri, 9 May 2008 12:34:08 +0200 (CEST)
Links: << >>  << T >>  << A >>
Guru <ales.gorkic@email.si> wrote:
>On May 9, 9:01 am, "beky...@gmail.com" <beky...@gmail.com> wrote:
>> This project demonstrates an easy way to create AMBA masters and
>> slaves. It includes an AHB master, AHB slave, APB master and APB
>> slave.http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html

>Fu...off, you have a virus on the server.

Seems it was an iframe pointing to www.ctv163.com/wuhan/down.htm
But it's no problem to browse with a secure browser on secure os.


Article: 131982
Subject: Re: Xilinx Platform USB Cable II
From: Clemens <Clemens@hotmail.com>
Date: Fri, 09 May 2008 11:35:22 +0100
Links: << >>  << T >>  << A >>
> Especially if it is compatible with Chipscope 7.1 because I havent seen a free webpackage for this 
> software tool yet!

My mistake, just seen that there is already a 10.1 version out for ISE 
as well as for Chipscope to download! Anyway, does anyone confirm me 
backwards capability so that it also works with 7.1 ?

thanks!

Article: 131983
Subject: Vritex2PRO: LVDCI for inputs?
From: Goli <togoli@gmail.com>
Date: Fri, 9 May 2008 04:24:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I am using Virtex2Pro, and I have assigned LVDCI IO standards for all
my LVCMOS receivers. I was wondering if LVDCI has any significance for
inputs. For outputs it adds a series termination resistor, what does
it do for inputs? Does it add parallel resistor?? The user guide does
not state anything clearly.

--
Goli

Article: 131984
Subject: Re: Xilinx Platform USB Cable II
From: sky465nm@trline4.org
Date: Fri, 9 May 2008 13:51:04 +0200 (CEST)
Links: << >>  << T >>  << A >>
Clemens <Clemens@hotmail.com> wrote:
>Hi

>I have intended an upgrade to Xilinx 9.2 or higher from version 7.1.
>With this newer versions my programming cable is no longer supported.

What kind of programming cable do you have .. ?


Article: 131985
Subject: Re: 5 V oscillator output to GCLK
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 09 May 2008 13:23:40 +0100
Links: << >>  << T >>  << A >>
On Fri, 9 May 2008 01:01:45 -0700 (PDT), maverick
<sheikh.m.farhan@gmail.com> wrote:

>Hi,
>I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator
>which gives clk output at 5V p-p swing.  I am using the FPGA in LVTTL
>mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to
>one of the GCLK pins of the Spartan 3 FPGA? Should I put a current
>limiting resistor in the clock path before I feed it to the GCLK pin?
>Any issues with that?

Better to use a resistive divider to (a) drop the 5V to 3.3V and (b)
match the impedance of the signal trace. My preference would be for
series termination, i.e. place the resistive divider at the oscillator
end, assuming the clk trace is a simple trace (no major stubs feeding
different destinations).

If the oscillator can't drive such a low impedance, you need a higher
impedance divider. Then I would place it aas close as possible to the
Spartan pin.

- Brian

Article: 131986
Subject: Re: Xilinx Platform USB Cable II
From: Clemens <Clemens@hotmail.com>
Date: Fri, 09 May 2008 13:28:12 +0100
Links: << >>  << T >>  << A >>
sky465nm@trline4.org wrote:
> Clemens <Clemens@hotmail.com> wrote:
>> Hi
> 
>> I have intended an upgrade to Xilinx 9.2 or higher from version 7.1.
>> With this newer versions my programming cable is no longer supported.
> 
> What kind of programming cable do you have .. ?
> 

Multilinx its called...

Article: 131987
Subject: Re: Quartus 7.2 and PCI Express
From: =?ISO-8859-1?Q?G=F3rski_Adam?=
Date: Fri, 09 May 2008 15:59:40 +0200
Links: << >>  << T >>  << A >>
axalay pisze:
> because I need restart system? and windows is not see the devise

So use second PC. It's chiper than license.

Adam

Article: 131988
Subject: Re: 5 V oscillator output to GCLK
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Fri, 9 May 2008 07:10:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 9 Mai, 14:23, Brian Drummond <brian_drumm...@btconnect.com> wrote:
> My preference would be for
> series termination, i.e. place the resistive divider at the oscillator
> end, assuming the clk trace is a simple trace

Do both:
One resistor in series at the source, one resistor to ground at the
destination.
You get a transmission line that is terminated at both ends. A
reflection caused
by a mismatch at the destination is dampened at the source.

This provides essentially the best signal quality you can get. The
only disadvantage
is the reduced swing at the destination. But this is exactly what the
OP wants.

Kolja Sulimma

Article: 131989
Subject: Re: Quartus 7.2 and PCI Express
From: axalay <axalay@gmail.com>
Date: Fri, 9 May 2008 07:34:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
I do it!!! Yes! :)

Article: 131990
Subject: Re: ANNC: FPGA Design Software Webcast
From: "BobW" <nimby_NEEDSPAM@roadrunner.com>
Date: Fri, 9 May 2008 07:37:44 -0700
Links: << >>  << T >>  << A >>

"CBFalconer" <cbfalconer@yahoo.com> wrote in message 
news:4823ACED.97C41D24@yahoo.com...
> John Larkin wrote:
>> CBFalconer <cbfalconer@yahoo.com> wrote:
>>
> ... snip ...
>>
>>> Please snip the quotes on your replies.
>>
>> Feel free to snip whatever you like.
>
> The point of that request is to avoid burdoning all group users
> with the burdon of paging down over irrelevant material, and to
> reduce the overall load on the Usenet system.
>
> -- 
> [mail]: Chuck F (cbfalconer at maineline dot net)

I get it, Chuck. It's okay to overload Usenet with spam but it's not okay to 
overload Usenet by not trimming one's replies.

You should run for president. Next week, perhaps, you'll explain how to 
reconcile the Arabs and the Jews.

Bob
-- 
== NOTE: I automatically delete all Google Group posts due to uncontrolled 
SPAM == 



Article: 131991
Subject: Re: Quartus 7.2 and PCI Express
From: axalay <axalay@gmail.com>
Date: Fri, 9 May 2008 07:52:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 9 =A7=DE=A7=D1=A7=DB, 17:59, G=A8=AErski Adam
<gorskia@.................wp....................pl..................>
wrote:
> axalay pisze:
>
> > because I need restart system? and windows is not see the devise
>
> So use second PC. It's chiper than license.
>
> Adam

I am not rich :) I have notebook, but work in  him very inconvenient.
question is clouse :)

Article: 131992
Subject: Re: Vritex2PRO: LVDCI for inputs?
From: austin <austin@xilinx.com>
Date: Fri, 09 May 2008 07:57:01 -0700
Links: << >>  << T >>  << A >>
Goli,

LVDCI does nothing for inputs.  LVDCI is series terminated only at the
drivers.

HSTL_DCI, SSTL_DCI use parallel termination at the receiver.

See the user's guide.

Austin

Article: 131993
Subject: Re: 5 V oscillator output to GCLK
From: "David Spencer" <davidmspencer@verizon.net>
Date: Fri, 09 May 2008 15:53:25 GMT
Links: << >>  << T >>  << A >>

"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message 
news:0d885ecd-0839-416b-98fd-1ff4f1835806@34g2000hsh.googlegroups.com...
> On 9 Mai, 14:23, Brian Drummond <brian_drumm...@btconnect.com> wrote:
>> My preference would be for
>> series termination, i.e. place the resistive divider at the oscillator
>> end, assuming the clk trace is a simple trace
>
> Do both:
> One resistor in series at the source, one resistor to ground at the
> destination.
> You get a transmission line that is terminated at both ends. A
> reflection caused
> by a mismatch at the destination is dampened at the source.
>
> This provides essentially the best signal quality you can get. The
> only disadvantage
> is the reduced swing at the destination. But this is exactly what the
> OP wants.
>
> Kolja Sulimma

A better solution would be to feed the clock through a 3.3V buffer that is 
5V tolerant. An AHC family device would do the job I think. In fact, a 
74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin 
package. 



Article: 131994
Subject: Re: 5 V oscillator output to GCLK
From: KJ <kkjennings@sbcglobal.net>
Date: Fri, 9 May 2008 09:11:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 9, 11:53=A0am, "David Spencer" <davidmspen...@verizon.net> wrote:

>
> A better solution would be to feed the clock through a 3.3V buffer that is=

> 5V tolerant. An AHC family device would do the job I think. In fact, a
> 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin
> package.- Hide quoted text -
>

By what measure would an IC be a "better solution" than two resistors?

KJ

Article: 131995
Subject: ISE 9.2 - how do I extract component/slice placements for locking
From: Fred <fred__bloggs@lycos.com>
Date: Fri, 9 May 2008 09:23:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
Is there any NGD reader which can extract placement information?

I know I can use FPGA editor and go through all the primitives, one by
one, but this would be a mamoth task!  Any ideas?

Article: 131996
Subject: Re: 5 V oscillator output to GCLK
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 9 May 2008 09:41:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
maverick wrote:
> Hi,
> I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator
> which gives clk output at 5V p-p swing.  I am using the FPGA in LVTTL
> mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to
> one of the GCLK pins of the Spartan 3 FPGA? Should I put a current
> limiting resistor in the clock path before I feed it to the GCLK pin?
> Any issues with that?
>
> Best Wishes,
> Farhan

I just got a 3.3V oscillator driving a 2.5V input working.  The
oscillator has miserable drive capability and I suspect the 5V
oscillator you're using may have poor drive capability as well.

Unless you have a rare high-drive oscillator OR if you're oscillating
at a leisurely rate, do like the FPGA vendor recommends: use a 100 ohm
series resistor.

If you use a resistor divider, your parasitics can severely slow down
your edges.  Our 125 MHz oscillator looked almost like a sine wave and
was reduced in amplitude to the point we were getting 25% duty cycle.
Not good for our application.  If it was a 20 MHz oscillator, the
resitor divider would probably be fine.  If we could deal with 25%
duty cycle we could have probably used what was there.  The series
resistor just plain works.  The input protection on the Spartan3 is
pretty robust so you can drive the many milliamps (if you have many
milliamps) into the protection diode without affecting reliability.

If I wanted to be detailed, I'd understand the drive capability, the
frequency, and the parasitics involved.

- John_H

Article: 131997
Subject: Re: ISE 9.2 - how do I extract component/slice placements for locking
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Fri, 09 May 2008 11:14:43 -0600
Links: << >>  << T >>  << A >>
Fred wrote:
> Is there any NGD reader which can extract placement information?
> 
> I know I can use FPGA editor and go through all the primitives, one by
> one, but this would be a mamoth task!  Any ideas?

Are you trying to floorplan or trying to figure out how PAR performed 
placement?  If the former, PlanAhead is a very nice tool for 
floorplanning.  -Kevin

Article: 131998
Subject: Re: Chirp generator / CORDIC algo ?
From: Duane Clark <user@domaininvalid.com>
Date: Fri, 09 May 2008 10:27:09 -0700
Links: << >>  << T >>  << A >>
XSterna wrote:
> 
> I still be curious about the lookup table because as I told you I
> don't have any experience in all that. Do you have any information
> (links or book references) about this method ? I have at the moment no
> idea about the memory I will need for all the chirps, so it could be a
> good solution.

In this case the lookup table has a phase input of however many bits of 
resolution you determine you need, and a sine output of the number of 
bits for your ADC, divided by 4 because you only need one quadrant of 
the sine.

Take a look at the diagram of the AD9858 to see how this is done. You 
start with an accumulator that accumulates frequency. It will be loaded 
with the starting frequency, and then on every frequency step (possibly 
less than your 200MHz), the frequency will increment by a constant 
amount. That is, the input to the accumulator is your frequency sweep 
step size (aka sweep rate).

The output of that goes to the input of the phase accumulator. This 
probably operates at your 200MHz. You will need to have a large number 
of bits in the phase accumulator to get good accuracy.

The upper bits of the output of the phase accumulator goes to the sine 
lookup table; the "phase to amplitude conversion" block in the AD9859 
diagram.

You can easily model this in Matlab, and determine how many bits you 
will need at each stage for your design.

Article: 131999
Subject: Re: Anyway to secure a Xilinx NGC file ?
From: austin <austin@xilinx.com>
Date: Fri, 09 May 2008 10:43:53 -0700
Links: << >>  << T >>  << A >>
Jim,

Copying the bitstream is trivial, so why bother with the NGC?

What is the vulnerability you are analyzing?

Who is your threat? (a major government, or an individual hacker...)

Not knowing what you are trying to protect (and why), we can't provide
you with an answer.

Austin



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Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
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1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
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2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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