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Alan Nishioka wrote:
> On Apr 11, 7:02 pm, kevin93 <ke...@whitedigs.com> wrote:
>> On Apr 11, 2:32 pm, Fei Liu <fei....@gmail.com> wrote:
>>
>>> Hello
>>> I am working on playing simple 11 kbytes/second 8bit WAV data through my
>>> FPGA stereo jack. I used the following synthesis to play the sound data
>>> delivered through the serial interface. I also used the mono_dac demo
>>> module.
>>> My problem is I am getting a very high noise to signal ratio although I
>>> can hear the speech. The sound file plays crystal clear on my host
>>> computer.
>> <.. snip ..>
>>
>>> //PWM audio(
>>> // .clk(clk),
>>> // .PWM_in(rx_data),
>>> // .PWM_out(aud_l)
>>> //);
>>> wire audio;
>>> FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk));
>>> mono_dac mono(
>>> .signed_data(rx_data),
>>> .volume(3'b100),
>>> .audio(audio),
>>> .clk(clk)
>>> );
>> <.. snip ..>
>>
>> 8-bit WAV files use offset binary rather than signed values (i.e. 0 is
>> the most negative, 128 is mid-scale 255 is full-scale)
>>
>> kevin
>
> And to convert signed to offset or to convert offset to signed you
> just have to invert the top bit (MSB). Since it is so easy, it might
> be worth it to just try it and see if it works.
>
> Alan Nishioka
Hmm, it doesn't seem to work. I use libsndfile and libserial to decode
and deliver data to serial port in this code:
static const sf_count_t nframes = 16;
signed char data;
char ptr[nframes];
int count = 0;
while(sfh.readRaw(ptr, nframes)){
count ++;
if(!(count%1000)) printf("Frames: %d\n", count);
int i = 0;
while(i < nframes){
data = ptr[i];
data -= 0x80;
my_serial_stream << data;
i++;
}
}
I just get a load of noise. I analyzed the signal sent to serial port
(from the Tx output), there is no glitch.
Fei
Article: 131151kislo <kislo02@student.sdu.dk> wrote: >On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote: >> i got a problem with the Spartan 3E starter kit from Xilinx, no matter >> what Mode pins are set for, the DONE LED is always turned on when i >> power on the board. I cannot connect to the board via JTAG pin headers >> either. All the voltages are correct. What could be the problem ? any >> thing i can do to debug it ? i have another Spartan 3E board and it >> works fine. >the LED is on even though i hold PROG_B low Check shorts. Check power voltages. Check the schematics.Article: 131152
Fei Liu wrote:
> Alan Nishioka wrote:
>> On Apr 11, 7:02 pm, kevin93 <ke...@whitedigs.com> wrote:
>>> On Apr 11, 2:32 pm, Fei Liu <fei....@gmail.com> wrote:
>>>
>>>> Hello
>>>> I am working on playing simple 11 kbytes/second 8bit WAV data
>>>> through my
>>>> FPGA stereo jack. I used the following synthesis to play the sound data
>>>> delivered through the serial interface. I also used the mono_dac demo
>>>> module.
>>>> My problem is I am getting a very high noise to signal ratio although I
>>>> can hear the speech. The sound file plays crystal clear on my host
>>>> computer.
>>> <.. snip ..>
>>>
>>>> //PWM audio(
>>>> // .clk(clk),
>>>> // .PWM_in(rx_data),
>>>> // .PWM_out(aud_l)
>>>> //);
>>>> wire audio;
>>>> FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk));
>>>> mono_dac mono(
>>>> .signed_data(rx_data),
>>>> .volume(3'b100),
>>>> .audio(audio),
>>>> .clk(clk)
>>>> );
>>> <.. snip ..>
>>>
>>> 8-bit WAV files use offset binary rather than signed values (i.e. 0 is
>>> the most negative, 128 is mid-scale 255 is full-scale)
>>>
>>> kevin
>>
>> And to convert signed to offset or to convert offset to signed you
>> just have to invert the top bit (MSB). Since it is so easy, it might
>> be worth it to just try it and see if it works.
>>
>> Alan Nishioka
>
> Hmm, it doesn't seem to work. I use libsndfile and libserial to decode
> and deliver data to serial port in this code:
>
> static const sf_count_t nframes = 16;
> signed char data;
> char ptr[nframes];
> int count = 0;
>
> while(sfh.readRaw(ptr, nframes)){
> count ++;
> if(!(count%1000)) printf("Frames: %d\n", count);
> int i = 0;
> while(i < nframes){
> data = ptr[i];
> data -= 0x80;
> my_serial_stream << data;
> i++;
> }
> }
>
> I just get a load of noise. I analyzed the signal sent to serial port
> (from the Tx output), there is no glitch.
>
> Fei
Do you suppose "my serial stream" might present the data backwards from
what you expect? See if you can generate a nice, clean tone with a
square wave - 0x00 for a few cycles then 0xff for a few cycles. If
that's clean, try 0x00 paired with 0x01 then 0x00 and 0x80. See which
of those two is audible.
Good luck. Troubleshooting is where the real thought comes in.
- John_H
Article: 131153Fei Liu wrote: > Hello > I am working on playing simple 11 kbytes/second 8bit WAV data through my > FPGA stereo jack. I used the following synthesis to play the sound data > delivered through the serial interface. I also used the mono_dac demo > module. > > My problem is I am getting a very high noise to signal ratio although I > can hear the speech. The sound file plays crystal clear on my host > computer. > > Another problem I have with simple WAV file is I don't know how to > extract volume information. So I hardwired 3'b100 as the volume. > > I could use some help figuring out the source of the high noise. Is this > caused by timing issue? > > Fei > > WAV file info: > File : 11k8bitpcm.wav > Length : 152312 > RIFF : 152304 > WAVE > fmt : 16 > Format : 0x1 => WAVE_FORMAT_PCM > Channels : 1 > Sample Rate : 11025 > Block Align : 1 > Bit Width : 8 > Bytes/sec : 11025 > data : 152267 > End > > ---------------------------------------- > Sample Rate : 11025 > Frames : 152267 > Channels : 1 > Format : 0x00010005 > Sections : 1 > Seekable : TRUE > Duration : 00:00:13.811 > Signal Max : 128 (0.00 dB) > > `include "timescale.v" > > module serial_snd( > clk, > rx, > tx, > led0, > led1, > led2, > aud_l, > aud_r > ); > > parameter clk_freq=50000000; > parameter blink_freq = 25; > > (* LOC="E12" *) input clk; > (* LOC="F16" *) input rx; > (* LOC="E15" *) output tx; > (* LOC="R20" *) output led0; > (* LOC="T19" *) output led1; > (* LOC="U20" *) output led2; > (* LOC="Y10" *) output aud_l; > (* LOC="V10" *) output aud_r; > > wire data_ready; > wire RxD_idle; > wire [7:0] rx_data; > reg [blink_freq:0] count = 0; > > // serial port receiver > async_receiver #(.clk_freq(clk_freq)) ar( > .clk(clk), > .RxD(rx), > .RxD_data_ready(data_ready), > .RxD_data(rx_data), > .RxD_idle(RxD_idle) > ); > > // Serial port transmitter > async_transmitter #(.clk_freq(clk_freq)) serializer( > .clk(clk), > .TxD(tx), > .TxD_start(data_ready), > .TxD_data(rx_data) > ); > > // Blink LED0 with a frequency slightly slower than once per second > assign led0 = count[blink_freq]; > assign led2 = RxD_idle; > > // LED1 lights on when there is incoming data from serial line, it lasts > 2^20 clks > state_holder #(.clk_hold(20)) bl(clk, data_ready, led1); > > //PWM audio( > // .clk(clk), > // .PWM_in(rx_data), > // .PWM_out(aud_l) > //); > wire audio; > FD fd_aud_lt_inst (.D(audio),.Q(aud_l),.C(clk)); > > mono_dac mono( > .signed_data(rx_data), > .volume(3'b100), > .audio(audio), > .clk(clk) > ); > > assign aud_r = 8'bz; > > always @(posedge clk) begin > count <= count + 1; > end > > endmodule Ah I found the problem, it's because the rx_data is only valid for a single clk after data_ready signal is high. So the fix is quite simple, use a register to buffer rx_data when data is available! Because xapp154 chipset requires audio in signal to hold for 2**(MSBL+1) clks after it changes. FeiArticle: 131154
On 12 Apr., 14:16, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > I was recently very disappointed with the performance of Xilinx > systemACE, but the problem was in my head, a thinking problem and too > little homework - the issue is not related to systemACE or CF cards, > but it is present by almost all flash cards - the "controller > overhead" > > very short: any flash-card (except smartmedia or x-d) will only give > some 1-2MB/s data rate when using single sector read commands. Ok it > may differ a little, but by NO MEANS the advertised data rates can be > achieved without multi-sector reads > > so there is NO WAY to optimize systemACE driver to get better > performance as long the complete fat library is not optimized to read > data from card in large junks that are sent to CF card as multi-sector > reads > > PS, if there is some trick, or if some CF/SD card has VERY small > controller overhead i would be interested to know > > Antti http://antti-lukats.blogspot.com/ Ha a goodnight sleep makes wonders we do not usually expect the need to make disassembly and read it, but this time it explained something: without looking up Microblaze instruction timings and doing very raw thumb "cycle count" pro read byte in Xilinx low level systemACE driver (microblaze, no barrel shifter): 100 system clocks per byte data read from systemACE ! ========================================= for 125MHz system clock it means that XILINX DRIVER overhead alone limits the bandwidth to around 1MB/s !! so there is place to optimize and gain more data bandwidth AnttiArticle: 131155
Peter Alfke wrote: (snip) > Thats the way when you cannot use the simplest method, called 8B10B, > where 10 bits are used to transmit the content of 8 data bits. > Transceivers often include the necessary encoder/decoder, and DC > balancing is automatically included. The penalty is a 25% loss in > throughput ( e.g. only 2.5 Gbps from a 3,125 Gbps channel. > Scrambling is populat with the telephone people. I wouldn't call 8B10B the simplest. Manchester code used by many ethernet systems, also known as phase modulation or phase encoding (1600BPI 9 track tapes) is simpler, self clocking, and less efficient in bandwidth. 800BPI 9 track tape is NRZI coded and relies on odd parity for a transition in at least one track. That requires very careful azimuth adjustment on the drive. With phase encoding for 1600BPI each track clocks separately. 6250BPI are GCR coded, I don't know the specific code. -- glenArticle: 131156
On Sun, 13 Apr 2008 00:50:44 -0800, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >Peter Alfke wrote: >(snip) > >> Thats the way when you cannot use the simplest method, called 8B10B, >> where 10 bits are used to transmit the content of 8 data bits. >> Transceivers often include the necessary encoder/decoder, and DC >> balancing is automatically included. The penalty is a 25% loss in >> throughput ( e.g. only 2.5 Gbps from a 3,125 Gbps channel. >> Scrambling is populat with the telephone people. > >I wouldn't call 8B10B the simplest. > >Manchester code used by many ethernet systems, also known as >phase modulation or phase encoding (1600BPI 9 track tapes) is >simpler, self clocking, and less efficient in bandwidth. True, though Peter's point may be that it's simpler to turn on the existing 8B10B solution than implement your own Manchester code. - BrianArticle: 131157
On 13 Apr., 06:40, sky46...@trline4.org wrote: > kislo <kisl...@student.sdu.dk> wrote: > >On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote: > >> i got a problem with the Spartan 3E starter kit from Xilinx, no matter > >> what Mode pins are set for, the DONE LED is always turned on when i > >> power on the board. I cannot connect to the board via JTAG pin headers > >> either. All the voltages are correct. What could be the problem ? any > >> thing i can do to debug it ? i have another Spartan 3E board and it > >> works fine. > >the LED is on even though i hold PROG_B low > > Check shorts. > Check power voltages. > Check the schematics. all checkedArticle: 131158
On 13 Apr., 12:26, kislo <kisl...@student.sdu.dk> wrote: > On 13 Apr., 06:40, sky46...@trline4.org wrote: > > > kislo <kisl...@student.sdu.dk> wrote: > > >On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote: > > >> i got a problem with the Spartan 3E starter kit from Xilinx, no matter > > >> what Mode pins are set for, the DONE LED is always turned on when i > > >> power on the board. I cannot connect to the board via JTAG pin headers > > >> either. All the voltages are correct. What could be the problem ? any > > >> thing i can do to debug it ? i have another Spartan 3E board and it > > >> works fine. > > >the LED is on even though i hold PROG_B low > > > Check shorts. > > Check power voltages. > > Check the schematics. > > all checked when measured all the signals are grounded, including the unconnected jtag signals (which should be pulled high from internal pull ups) .. can the FPGA be damaged somehow ?Article: 131159
Hi there - I'm very new to FPGAs and so I'm probably doing many dumb things. I recently got a Spartan 3E Starter Kit (http:// www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable). I followed the guide shown here: http://www.fpga4fun.com/ISEQuickStart.html to make a new project. When selecting the device I said: Product Category: All Family: Spartan 3E Device: XC3S500E Package: FG320 Speed: -4 I wasn't sure about the speedgrade - but I googled around and found some other people had used -4 for that option on similar boards. Is that the correct choice? How would I figure that out? Also, what exactly does the speedgrade mean? The help file wasn't very verbose about it. Thanks! -MichaelArticle: 131160
Michael wrote: > > I wasn't sure about the speedgrade - but I googled around and found > some other people had used -4 for that option on similar boards. Is > that the correct choice? How would I figure that out? Also, what > exactly does the speedgrade mean? The help file wasn't very verbose > about it. > > Thanks! > > -Michael Hi Michael, It's written on the chip. You'll see 4C somewhere, I expect. This is speedgrade 4, commercial temperature range. The speedgrade is used to guarantee the speed of the innards of the device. Read the datasheet, and look for the 'switching characteristics' section. HTH., Syms.Article: 131161
On Apr 13, 6:25=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > Michael wrote: > > > I wasn't sure about the speedgrade - but I googled around and found > > some other people had used -4 for that option on similar boards. Is > > that the correct choice? How would I figure that out? Also, what > > exactly does the speedgrade mean? The help file wasn't very verbose > > about it. > > > Thanks! > > > -Michael > > Hi Michael, > It's written on the chip. You'll see 4C somewhere, I expect. This is > speedgrade 4, commercial temperature range. The speedgrade is used to > guarantee the speed of the innards of the device. Read the datasheet, and > look for the 'switching characteristics' section. > HTH., Syms. Hi Symon - you're right - 4C is printed on the chip. Thanks for the help! I've just run into one other problem: I tried changing my code around a bit - I changed one of the output names and added a new output. I then went to assign package pins and assigned pins to the two new outputs. I then tried to generate a programming file. This gave me an error about the .ucf containing a reference to the old name of the output whose name I changed. I couldn't figure out why that would happen though. When I did the "assign package pins" shouldn't it have fixed that? I mean - when I assign package pins doesn't that create the .UCF file? Eventually I clicked on "Edit Constraints (text)" and removed the line (which was the very first line, oddly enough, above where it says "#PACE: Start of Constraints generated by PACE") that referenced the old output name. That fixed the problem and I was able to generate the programming file and program it just fine. But what was the proper way to deal with that? I'm very new to all this so I want to make sure I don't get into any bad habits. Thanks! -MichaelArticle: 131162
Hello I need a large Virtex-5 FPGA like the SX95T on a PCIe board with DDR2 memory. HiTech Global has a variety of boards with these features but I rarely here that company mentioned on this newsgroup. Does anyone out there have experience with HiTech Global eval boards? How is their quality and documentation? Any replies about HiTech Global would be very helpful. PeteArticle: 131163
On Apr 13, 4:01=A0pm, kislo <kisl...@student.sdu.dk> wrote: > On 13 Apr., 12:26, kislo <kisl...@student.sdu.dk> wrote: > > > > > > > On 13 Apr., 06:40, sky46...@trline4.org wrote: > > > > kislo <kisl...@student.sdu.dk> wrote: > > > >On 12 Apr., 21:00, kislo <kisl...@student.sdu.dk> wrote: > > > >> i got a problem with the Spartan 3E starter kit from Xilinx, no mat= ter > > > >> what Mode pins are set for, the DONE LED is always turned on when i= > > > >> power on the board. I cannot connect to the board via JTAG pin head= ers > > > >> either. All the voltages are correct. What could be the problem ? a= ny > > > >> thing i can do to debug it ? i have another Spartan 3E board and it= > > > >> works fine. > > > >the LED is on even though i hold PROG_B low > > > > Check shorts. > > > Check power voltages. > > > Check the schematics. > > > all checked > > when measured all the signals are grounded, including the unconnected > jtag signals (which should be pulled high from internal pull ups) .. > can the FPGA be damaged somehow ?- Hide quoted text - > > - Show quoted text - Hi, Did you try to read the device in JTAG chain ? Or Try put the FPGA in Master Serial Mode and check if it drives "CCLK" pin to see if the device is alive ! I still think that the issue lies with some sort of short circuit on board. Recheck the schemetics and if possible, upload it some where. So that others could see those and give their comment. Hope this helps /MHArticle: 131164
Hi,
Does anyone know if user defined Primitives are supported with XST, I
have the following code and it is giving error,
primitive mymultiplexer
(y, a, b, c0, c1, c2, c3);
output y;
// reg y;
input a, b, c0, c1, c2, c3;
table
// a b c0 c1 c2 c3 y
0 0 1 ? ? ? : 1 ;
0 0 0 ? ? ? : 0 ;
0 0 x ? ? ? : x ;
1 0 ? 1 ? ? : 1 ;
1 0 ? 0 ? ? : 0 ;
1 0 ? x ? ? : x ;
0 1 ? ? 1 ? : 1 ;
0 1 ? ? 0 ? : 0 ;
0 1 ? ? x ? : x ;
1 1 ? ? ? 1 : 1 ;
1 1 ? ? ? 0 : 0 ;
1 1 ? ? ? x : x ;
x 0 1 1 ? ? : 1 ;
x 0 0 0 ? ? : 0 ;
x 1 ? ? 1 1 : 1 ;
x 1 ? ? 0 0 : 0 ;
0 x 1 ? 1 ? : 1 ;
0 x 0 ? 0 ? : 0 ;
1 x ? 1 ? 1 : 1 ;
1 x ? 0 ? 0 : 0 ;
x x 0 0 0 0 : 0 ;
x x 1 1 1 1 : 1 ;
endtable
endprimitive
ISE reports: Unsupported Switch or UDP primitive.
I can work around this problem, but writing code as modules, but I was
just wondering if I have to enable something in the tool and get it
working.
Article: 131165> > We try to please. > > If Lars had only given his real and usable e-mail address, he would > > have had the properly formatted information in minutes... > > Peter Alfke > > ...along with 593 emails offering pills to give him a 13 inch penis, and 264 > emails offering a share of "an abandoned sum of$15million USD(Fifteen > million US dollars)only" from "FOREIGN REMITTANCE DEPT. BANK OF AFRICA ( > BOA) OUAGADOUGOU, BURKINA FASO". > > Why not leave the TechXclusives on the website until they've been turned > into whatever 'corporate image thing' the new VP has decided on? > > Love you all loads, Syms. That is exactly why i didn't provide my regular email address there. Forgot to add the line: Remove the obvious from my email address to mail me. I still get about 50 spam letters a day fromold posts before I realized just how bad it was. Regarding blogs v.s. old style TechXclusives, let's giv it a try. I am sure we all appreciate the huge effort that Peter and Austin (among others) put into keeping us all on the right track. Huge thanks for that! /Lars And, yes, remove the obvious from my email address to mail me...Article: 131166
Eric Smith wrote: > Roger wrote: >> Will there be a 64 bit WebPack version of ISE in the near future? > > Is it really necessary? WebPack doesn't support parts large enough > to exhaust the memory avialable in the 32-bit world. Processors using the amd64 ISA have a number of advantages other than just access to larger amounts of memory. They've got more general purpose registers, 64-bit arithmetic, and slightly less legacy baggage. So for some tasks, a program compiled for 64-bit windows/*nix will run noticeably faster than one compiled for 32-bit mode - even if it does not use much memory. I have no idea if that applies to ISE, however.Article: 131167
In comp.arch.fpga FPGA <FPGA.unknown@gmail.com> wrote: >Is task in verilog equivalent to procedure in VHDL? I am trying to >convert a verilog file to vhdl. >Verilog => >// string data type >reg [8*4:1]a; >reg [8*255:0]b; >VHDL => >Is the above equivalent to >variable a : string(1 to 8*4) >variable b : string(1 to 8*255) Just a thought..: variable b : string(0 to 8*255)Article: 131168
More than helpful, it has all of it. Thanks. lc Arlet Ottens wrote: > > This may be helpful: > > http://toolbox.xilinx.com/docsan/xilinx82/books/docs/lib/lib.pdfArticle: 131169
Tks,
lc.
vladitx wrote:
> On Apr 12, 12:59 pm, LC <cupidoREM...@mail.ua.pt> wrote:
>> Can someone help me with the details of the following
>> components:
>>
>> SRL16E
>
> In Verilog-2001:
>
> module SRL16E #(
> parameter INIT=16'h0000
> ) (
> output Q,
> input A0,
> input A1,
> input A2,
> input A3,
> input CE,
> input CLK,
> input D
> );
>
> reg [15:0] r;
>
> assign Q = r[{A3, A2, A1, A0}];
>
> initial
> r = INIT;
>
> always @(posedge CLK)
> if (CE)
> r <= {r[14:0], D};
>
> endmodule
Article: 131170> > Just a thought..: > variable b : string(0 to 8*255) Unfortunatly not. String has a range that uses positive instead of integer, so must always be 1 to somthing. You cant use downto either.Article: 131171
Im trying to include a chipscope core into XPS 9.2 using the Debug
configuration screen. When i set up the core and try to update
bitstream i get following error:
ERROR:MDT - chipscope_icon_0 (chipscope_icon) - Generating the core :
chipscope_icon_0....
Chipscope Core Generator Error :
Unable to find the Chipscope Core Generator : generate.exe in the
path
Registry search for a Chipscope Installation also failed.
Please ensure that a valid Chipscope Installation exists for this
Chipscope
Core to work
Please verify that the MHS Parameters for "chipscope_icon_0" core
are valid
and the generated Chipscope Core Generator arg file :
"implementation/cs_coregen_chipscope_icon_0.arg" is valid
*************************************************************
while executing
"error "Generating the core : $params(INSTANCE)....
Chipscope Core Generator Error :
$err
Please verify that the MHS Parameters for \"$params(INSTANC..."
(procedure "::hw_chipscope_icon_v1_01_a::icon_generate" line
91)
invoked from within
"::hw_chipscope_icon_v1_01_a::icon_generate 41551224"
ERROR:MDT - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
That is weird, since chipscope is working fine in ISE .. i have tryed
to add the chipscope to the registry path but no luck .. what could be
that problem ?
Regards
Article: 131172please i need you help on that. searching throutgh the internet nothing is somethin like step by step guide:(Article: 131173
On Sun, 13 Apr 2008 23:02:23 -0700 (PDT), Goli <togoli@gmail.com> wrote: >Hi, > >Does anyone know if user defined Primitives are supported with XST, I >have the following code and it is giving error, > >primitive mymultiplexer ... >endprimitive > >ISE reports: Unsupported Switch or UDP primitive. > >I can work around this problem, but writing code as modules, but I was >just wondering if I have to enable something in the tool and get it >working. The nearest to an "user defined primitive" is a "black box". You can start by creating a module, and synthesise that module separately, (to a .ngc file) ensuring that XST will not add I/O pins for that module. (There are options settings to do that) Then you can use that "black box" in your design. I don't do Verilog, but in VHDL you attach a "box_type" attribute set to "black_box" to that component. Verilog does it differently but I can't help with that. XST won't worry that the insides of that module aren't defined, it will leave the black box empty. The back end tools (Translate, MAP, PAR etc) need access to the .ngc file created earlier for the module, to complete the design by filling in the "black box". Typically you keep all your black boxes in either the project directory, or a separate directory and set options for the "Translate" tool to find that directory. This is just a sketch of a solution; you will need to read Xilinx documentation (and search for "black box") for more details. EDK uses this technique for pre-compiled processor cores, but you can do the same thing yourself. - BrianArticle: 131174
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some verilog in my collegiate days - but that was quite some time ago and it is all very fuzzy now. I have decided that as an EE I should be familiar with FPGAs - so I'm re-educating myself. With that said - which would be more useful to learn in the industrial world: Verilog or VHDL? Thanks! -Michael
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