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We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We needed i/o pins to control motors and use various sensors and camera. The board contains EXP expansion slots, ( somewhere I found it is called QTE connector?). We are confused as how to easily connect our sensors like optical encoder, camera and output for our motor drivers using these EXP slots? Somewhere we found that we need to use QSE connector but we are not clear about it. We need a low cost solution !!!!! Can we find the connectors to match with EXP slot at one end and have simple wires at the other end?? Hope to get reply soon!!!!Article: 132401
On 23 Mai, 20:08, Peter Alfke <pe...@xilinx.com> wrote: > Kolja, I should have referred you to the XAPP860. My oversight... Easy enough. The application notes link to each other. > Regarding -3 devices, they do exist for all the smaller part types, > but not for the largest ( '200 and above). > -2 might be good enough for your application. -3 has a faster clock > distribution, but there is little (if any) difference in the LVDS and > ISERDES structures. At those speeds 100ps make a big difference. The application notes show, that at 1200Mbps the sampling windows is twice as large on a -3 than it is on a -2 device. However, it really seems to be the case that -2 is good enough. Especially as we can run the device easily at +3% supplies. Thank you for the pointer, KoljaArticle: 132402
I have a PowerPC (Virtex2PRO) and SDRAM (programm and data memory). I anderstand that the bootloader may be use to load programm from systemACE or FLASH Memory. But I whant load programm from configurePROM to SDRAM. Is it possible? Somebody help me?Article: 132403
On May 22, 12:29 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 22 May 2008 08:12:14 +0100, "HT-Lab" wrote: > >set XIL_TIMING_ALLOW_IMPOSSIBLE=1 > > Hey, that's not fair... When I want to do a "never ifdef" by > testing an env var or macro that is sure to be absent, I usually > use IMPOSSIBLE_THINGS_BEFORE_BREAKFAST - and that one is getting > awfully, awfully close :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I think the OP's problem is that he has set the timing driven packing and placement option for Map. Turning this off allows map to complete and generate the timing so you can find the failing path. In essence, turning on timing driven packing and placement allows map to do the first half of place & route. This is where the timing error prevents map completion. Regards, GaborArticle: 132404
May I use SPI Flash to fixed this problem? Xilinx reccomend External Memory Controller to connect Flash, but I am not see in "IP Configure" SPI FLASH to connect to EPC.Article: 132405
Hi, Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to realize simple "fifo core" using core generator. I have done all the procedure and the core have been created. So I instance created component in my design and it looks like this ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:08:49 05/22/2008 -- Design Name: -- Module Name: fifotest - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --Library XilinxCoreLib; -- synthesis translate_on library work; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fifotest is port ( clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); rd_en: IN std_logic; rst: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; full: OUT std_logic); end fifotest; architecture Behavioral of fifotest is component fifo_v4_3 port ( clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); rd_en: IN std_logic; rst: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; full: OUT std_logic); end component; begin ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG your_instance_name : fifo_v4_3 port map ( clk => clk, din => din, rd_en => rd_en, rst => rst, wr_en => wr_en, dout => dout, empty => empty, full => full); ------------INSTANTIATION Template ------------ end Behavioral; but when I wanted to implement my module I have got this error ERROR:NgdBuild:604 - logical block 'your_instance_name' with type 'fifo_v4_3' I was reading on the xilinx help but there is written that I should do this This error occurs when a netlist is not found. In EDK user-defined PCOREs, if the VHDL for the PCORE is using both HDL and NGC or EDIF netlists, the STYLE attribute for the MPD file for that core must be set correctly. When using both HDL and NGC or EDIF netlists, ensure that the STYLE = MIX is set in the peripheral MPD file. The MPD file can be found in the following directory: <project_directory>\pcore\<core_name>\data But I can' find this MPD file in my core directory. Actually, directory where my core is realized consist only directory temp. I am totally confused. Has anyone had similar type of problem. I repeat that from the core generator I don't receive any kind of message that there are some errors in my designed core. Any kind of help is welcome Thanks to everyone ZoranArticle: 132406
On May 25, 5:45 am, raghunanda...@gmail.com wrote: > Hi, > Im getting the following error when trying to run the ML505 Standard > IP Core Demo project from Xilinx. Im trying with the project that > Xilinx gave me,without any modifications. > > <error starts here> > > INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey > placement request which requires the combination > of the following comp blocks into the SLICE_X39Y78 site. comp: > mb_plb/N4 comp: > mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ > arbctrl_sm_cs_FSM_FFd6 The fragment blocks involved > are as follows: LUT symbol > "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ > arbctrl_sm_cs_FSM_FFd6-In_SW0" (Output Signal = > mb_plb/N4) FMux symbol "mb_plb/mb_plb/ > GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd6- > In" > (Output Signal = mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/ > I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd6-In) FLOP symbol > "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ > arbctrl_sm_cs_FSM_FFd6" (Output Signal = > mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ > arbctrl_sm_cs_FSM_FFd6) The top reasons for failure > were: -> A legal placement was never found for LUT symbol > "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ > arbctrl_sm_cs_FSM_FFd6-In_SW0". > Final packing quit early. > > </error> > > The error is solved when I turn on Xplorer script, though the run time > goes through the roof. How can I get the issue resolved? > > Raghu. Well, you did part of the resolution: run Xplorer script on it. After you've run the script, it should provide you with the combination of settings it used to build your image. Record those and use them for future iterations. Now you won't need to run the script, and you're build-time should be much less.Article: 132407
Hi I have a simple 4x4 array defined as follows: type rib is array (0 to 3) of std_logic_vector(3 downto 0); signal RanIB : rib; In my combinational logic stage I evaluate a new column that I wanna store in my 4x4 array at the next clock cycle. However, the problem is that at the next clock cycle I also wanna update one row of the same array and set to ZERO all the values in a specific row. The problem is that also the row index of the newly added column should be set to ZERO at the same clock... Cleary I will get an undefined value for one element in my array when I try to write from two sources at the same time. Is there an elegant way to implement this stuff? For clarification a little example ;) My array looks as follows: 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 At the next clock cycle I wanna update column 2 for instance 1 1 1 0 1 1 0 1 1 0 0 0 <------ UPDATE 1 1 1 1 But also I wanna set to zero all the values in row 0 0 1 1 0 0 1 0 1 "U" 0 0 0 <------ UPDATE 0 1 1 1 ^ | | update with zeros at the same clock cycle So if I just do it straightforward I will get an undefined value for RANIB(0,2).Article: 132408
OK, so I have this core I wrote which wants to read and write data to an= d = from SDRAM in a Spartan-E3 500 Microblaze system. There will be quite a lot of data moving around, and also I want the thi= ng = to be self-serving, not need to call the CPU to make a request to = opb_central_dma, so I connected it to the mch_opb_sdram controller using= = one of the MCH/XCL channels, not on the OPB bus. There will be another = core with the same interface, the SDRAM acting like a large FIFO between= = the two (and also storing microblaze code and data). Anyway, it looks good in ISE simulator (simulating only my core) and the= n = in the FPGA it fails. The SDRAM controller locks up and doen't respond = even to the CPU. That is a small problem, I must have done something wro= ng = ;) I'm using EDK 9.1i With ChipScope, this is the thing trying to emit a XCL Write transaction= : http://home.peufeu.com/nik/fpga/mch_scope2.png Note that here it emits to the FIFO every 2 clock cycles. Is this a = problem ? Can the SDRAM controller stall ? - It emits a 32-bit address on the MCH_data lines, which is actyally = address 0 - Control is set to 1 to indicate a write transaction - Write is set to 1 to push it in the FIFO - Cacheline size is set to 4 (which I hope is 4 words ?) so the core emi= ts = 4 32-bit datums, setting Control to 0 and pulsing Write each time - The core now wants to write another burst so it emits again the addres= s = (this time 0x10), sets Control to 1 ans pulses Write - FIFO is full so it waits forever. Apparently the mcb sdram controller isn't reading from the other side of= = the FIFO... Now this is the thing trying to emit a XCL Read transaction : http://home.peufeu.com/nik/fpga/mch_scope1.png It emits 4 read commands (address + control=3D0 + pulse Write). Thet it waits for read data that never comes. Soooooo..... there isn't much documentation on this subject it seems ;) If anybody has information, I would be very, very happy !!!! Thanks ;)Article: 132409
Hi all, I am experimenting incremental compilation following the Quartus II software handbook. But somehow the fitter ignores the logiclock region assignments so it will redo the placement and routing everytime. Here is the related message: ---- Info: Detected 34 design partitions (excluding Top) using post-fit netlists and LogicLock region assignments -- ignoring LogicLock region assignments ---- What could be the reason the fitter ignores the logiclock region assignments? The fitter's effort is set to Standard fit right now, could this be the reason? Your help is greatly appreciated. HuaArticle: 132410
Hi I have a very basic question. Xilinx permits me to initialize Block RAM with an external data file. The thing I am just wondering is, how do I download this file on the FPGA? Do I need to have a UART to download this file? Because I cant find an option with CHipscope, there I can just configure the FPGA with a new bit stream. Cheers for helpful comments, FlohArticle: 132411
LOL, I found the solution. So, in order to enable the MCH/XCL on the mch_opb_sdram controller, one= = must *activate* the Microblaze instruction/data cache and *connect* them= = to the mch_opb_sdram. After doing that, mch_opb_sdram realized my core w= as = connected to it too and started responding to its calls... I wonder why = = this is the case but since I will most likely need the caches anyway, I = = probably won't investigate this. When googling I found questions on the list about the XCL (the Xilinx = docs are pretty brief) here is how I did it : - Everything is registered on the clock edge as usual - It's two FIFOs, so - Read Fifo : - If ReadData_Exists =3D 1 you can read 1 datum and pulse Read to cons= ume = it - Write FIFO : - To write a value, set Access_Data and Access_Control to required = values and pulse Access_Write - if IsFull =3D 1 while you pulse Access_Write, you lose, the FIFO = contents will be corrupted and you can reboot your board Therefore not possible to put if(IsFull...) in a state machine, you mu= st = wait a cycle after each write or use combinatorial logic... The rest is as the docs say : - Write Address and Control =3D 1 - Wait - Receive N datums - Write Address and Control =3D 0 - Write N datums N being the Cache Line Size defined in your opb_mch_sdram parameters. This core would be very cool to use in a CPU-less environment where you= = just need to connect a few peripherals which will read and write to = buffers in SDRAM. Bandwidth is decent, too, I get about 70 MB/s from a 16-bit 50 MHz SDRA= M, = with 4-word bursts. I would probably get a little more with longer bursts, and a lot more = with DDR, or more bits of course ;) An annoying thing is that the FIFO has a "I'm full" signal but not a = "Only 1 free slot remaining" signal, which makes pipelining less = straightforward. Enjoy !Article: 132412
On 26 May=FDs, 18:57, Florian <Flo...@yahoo.com> wrote: > Hi > > I have a very basic question. Xilinx permits me to initialize Block RAM > with an external data file. The thing I am just wondering is, how do I > download this file on the FPGA? Do I need to have a UART to download > this file? Because I cant find an option with CHipscope, there I can > just configure the FPGA with a new bit stream. > > Cheers for helpful comments, > Floh Have a look at the .coe file in google. You can instantiate your rams by this file through core generator (this is for xilinx). Or you can define your own ram so that you can instantiate your ram as instantiating an array. Have a look at Mike Treseler's home page. Chipscope only makes you see what is going on FPGA. --enesArticle: 132413
<cherin99@gmail.com> wrote in message news:2f382c23-6f98-4197-92dc-b981fe7d4203@v26g2000prm.googlegroups.com... >I intend to build an fpga programer for the spartan fpgas of xilinx > > I am not sure about the file that i should send over the jtag to > program the fpga. > I got conflicting information from 2 different forums. > > Someone told me that i could either use the .bit or the .bin file. > According to him i just had to send one of these files to the jtag > programer. > > Someone else told me that i would have to generate either a .svf or > a .xsvf file from the .bit file using iMPACT. According to him i > should be specifying the devices in the jtag chain in iMPACT for > generating the correct .svf file. > Your best bet (in terms of minimal work) is to port Altera's JAM player to your programmer architecture, which is typically trivial to do. You can then create a .svf file from iMPACT, convert this to a .jbc file using the Altera utilities (I think you need to run 'svf2jam' followed by the JAM compiler), and program the file with your ported JAM player. I always thought it rather ironic that Altera provided such an easy way for in-system programming Xilinx parts!Article: 132414
> > Have a look at the .coe file in google. You can instantiate your rams > by this file through core generator (this is for xilinx). Or you can > define your own ram so that you can instantiate your ram as > instantiating an array. Have a look at Mike Treseler's home page. > Chipscope only makes you see what is going on FPGA. Thanks Enes, but the problem is that I still have to resythesize the whole design if I use the Core generator. XST allows allows to specify the RAM data in a text file and I can read then the contend from this file when running the architecture. However, I havent found any option in Chipscope nor Impact that allows me to download such a data file to the FPGA. SO I wonder if the only way to do that is using an UART Interface? Cheers, F.Article: 132415
R. Hofman a écrit : > Hi > > I have a simple 4x4 array defined as follows: > > type rib is array (0 to 3) of std_logic_vector(3 downto 0); > signal RanIB : rib; > > > For clarification a little example ;) > > > My array looks as follows: > > 1 1 1 0 > 1 1 0 1 > 1 1 1 0 > 1 1 1 1 > > At the next clock cycle I wanna update column 2 for instance > > 1 1 1 0 > 1 1 0 1 > 1 0 0 0 <------ UPDATE > 1 1 1 1 > > But also I wanna set to zero all the values in row 0 > > 0 1 1 0 > 0 1 0 1 > "U" 0 0 0 <------ UPDATE > 0 1 1 1 > ^ > | > | > update with zeros at the same clock cycle > > So if I just do it straightforward I will get an undefined value for > RANIB(0,2). Hello Your array will be managed by a single process. So you don't have to worry about any conflict. Just define what you want to happen in cell (2, 0) NicolasArticle: 132416
On 26 May=FDs, 20:23, Florian <Flo...@yahoo.com> wrote: > Thanks Enes, but the problem is that I still have to resythesize the > whole design if I use the Core generator. XST allows allows to specify > the RAM data in a text file and I can read then the contend from this > file when running the architecture. However, I havent found any option > in Chipscope nor Impact that allows me to download such a data file to > the FPGA. SO I wonder if the only way to do that is using an UART Interfac= e? > > Cheers, > F. Hi Florian, Actually I haven't been in such a situation before but as I know this is not possible by using these tools. You have to reach to the rams externally via a protocol. If there is something like you said, which I don't know, I will be glad if I can learn it too. Regards --enesArticle: 132417
On May 26, 4:57 pm, Florian <Flo...@yahoo.com> wrote: > Hi > > I have a very basic question. Xilinx permits me to initialize Block RAM > with an external data file. The thing I am just wondering is, how do I > download this file on the FPGA? Do I need to have a UART to download > this file? Because I cant find an option with CHipscope, there I can > just configure the FPGA with a new bit stream. > > Cheers for helpful comments, > Floh I'm not aware of any tools that would let you change the contents of RAM in a configured FPGA without requiring you to design your own interface and logic to write received data into the Block RAM. I've often thought this would be a useful feature (It would be especially nice to be able to dump the contents of a block RAM with Chipscope). What is possible is to change the data in the configuration bit stream so that when you configure the FPGA the RAM is initialised with the data you require, without having to iterate through synthesis and PAR. It's been a while since I did anything like this but I seem to remember there is a tool included in the Picoblaze package from Xilinx called Data2Mem that did exactly this to include the code for the processor in the bit stream. Take a look at the flow this tool required and you should be able to adapt it to your needs. SimonArticle: 132418
On May 26, 11:42 am, Hua <Tommy...@gmail.com> wrote: > Hi all, > > I am experimenting incremental compilation following the Quartus II > software handbook. But somehow the fitter ignores the logiclock region > assignments so it will redo the placement and routing everytime. Here > is the related message: > > ---- > Info: Detected 34 design partitions (excluding Top) using post-fit > netlists and LogicLock region assignments -- ignoring LogicLock region > assignments > ---- > > What could be the reason the fitter ignores the logiclock region > assignments? The fitter's effort is set to Standard fit right now, > could this be the reason? > > Your help is greatly appreciated. > > Hua Hi Hua, The info message indicates that Incremental Compilation is indeed active and that placement is being preserved for the 34 partitions. All the message is saying is that you have at least one LogicLock region set to Autosize and/or Floating, but because you are asking Quartus to preserve a previous placement, the LogicLock assignment is being ignored. To avoid seeing this message, you should use the "Set Size and Origin to Previous Fitter Results" command on the LogicLock regions window right-click menu to remove the Autosize and/or Floating properties. For more information on Quartus Incremental Compilation, I recommend you check out the Incremental Compilation Resource Center at: http://www.altera.com/support/software/incremental/sof-qts-increment-comp.html Thanks! GabrielArticle: 132419
The IO drive level constrain specifies the drive level of a output signal .. if i am using LVCMOS33 with a drive level of 8mA how can i determine the the output impedance if using f.x a 50ohm characteristic impedance of my trace?Article: 132420
"kislo" <kislo02@student.sdu.dk> wrote in message news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com... > The IO drive level constrain specifies the drive level of a output > signal .. if i am using LVCMOS33 with a drive level of 8mA how can i > determine the the output impedance if using f.x a 50ohm characteristic > impedance of my trace? From the IBIS files. Use them with your SI simulator. HTH., Syms.Article: 132421
Here is my question/issue: say you have: y : out std_logic; signal x: std_logic; you don't assign any value to "x" but you have a condition in your code.. i.e if (x= '1') then y <= '1'; else y <= '0'; end if; how does the x power up? high/low?? is that part/technology dependent? the reason I am asking this is because, I have a part that used to work all the time but now I got a different part (same mfg), programmed with the same programming file and it seems like x is powering up differently. Thanks, MartinArticle: 132422
On 27 Mai, 05:18, marts...@gmail.com wrote: > signal x: std_logic; > > you don't assign any value to "x" [..] > how does the x power up? high/low?? is that part/technology dependent? > > the reason I am asking this is because, I have a part that used to > work all the time but now I got a different part (same mfg), > programmed with the same programming file and it seems like x is > powering up differently. Try a Reset on Power up. For most FPGAs there is a global value for Powerup content that is valid before you use a reset. First of all, inspect the synthesis result. Only latches and FF are set during power up. All other signals depend on the contentg of Inputs, FF and latches. bye ThomasArticle: 132423
On May 27, 12:25 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 27 Mai, 05:18, marts...@gmail.com wrote: > > > signal x: std_logic; > > > you don't assign any value to "x" > [..] > > how does the x power up? high/low?? is that part/technology dependent? > > > the reason I am asking this is because, I have a part that used to > > work all the time but now I got a different part (same mfg), > > programmed with the same programming file and it seems like x is > > powering up differently. > > Try a Reset on Power up. > For most FPGAs there is a global value for Powerup content that is > valid before you use a reset. > First of all, inspect the synthesis result. Only latches and FF are > set during power up. All other signals depend on the contentg of > Inputs, FF and latches. > > bye Thomas Thomas, Thanks for your input. But what I was trying to figure out is that...If I am not using the reset, or not assign any values to signal, what happens in that case? I do know how to fix it but I was just curious to find out, why was this working for sometime but now doesn't work with a different part (same mfg)? Thanks, MartinArticle: 132424
On May 26, 1:39 pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: > R. Hofman a =E9crit : > > > > > Hi > > > I have a simple 4x4 array defined as follows: > > > type rib is array (0 to 3) of std_logic_vector(3 downto 0); > > signal RanIB : rib; > > > For clarification a little example ;) > > > My array looks as follows: > > > 1 1 1 0 > > 1 1 0 1 > > 1 1 1 0 > > 1 1 1 1 > > > At the next clock cycle I wanna update column 2 for instance > > > 1 1 1 0 > > 1 1 0 1 > > 1 0 0 0 <------ UPDATE > > 1 1 1 1 > > > But also I wanna set to zero all the values in row 0 > > > 0 1 1 0 > > 0 1 0 1 > > "U" 0 0 0 <------ UPDATE > > 0 1 1 1 > > ^ > > | > > | > > update with zeros at the same clock cycle > > > So if I just do it straightforward I will get an undefined value for > > RANIB(0,2). > > Hello > Your array will be managed by a single process. So you don't have to > worry about any conflict. Just define what you want to happen in cell (2, = 0) > > Nicolas Nicolas is right. You are thinking that somehow when you make two assignments to the same signal or variable that it will cause a conflict. That is not correct. If you have a conflict, it is because you have improperly constructed code, not because of what you are trying to do with the code. First, you need to decide what you want the design to do in the case of updating both a row and a column. Then you construct the code to do that. Remember that you are not writing software, you are describing hardware. The code does not know that you are writing to a row or a column. It only knows that you are making assignments to a signal or a variable. If you are having trouble figuring out how to construct your code, make a stab at it and we will be happy to correct mistakes and give suggestions on how you can do it better. But it is not much fun for us to write the code for you. So give it a try and show us what you come up with. BTW, what you are calling a row is a column and your column is a row. Rows run left-right and columns up-down. Rick
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