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Messages from 139875

Article: 139875
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: jleslie48 <jon@jonathanleslie.com>
Date: Fri, 17 Apr 2009 15:29:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 17, 10:55 am, jleslie48 <j...@jonathanleslie.com> wrote:
> here's the pinout of a board I'm using:
>
> #            chipset:
> #            xc3s500e-4cp132
> #
> #             3s500E
> #             xxxxx-xxxx
> #             korea
> #             C6-DGQ     4C
> #
> #             apparently the c6 defines the packages as CPG132 as per
> #             xilinx document ds312.pdf
>
> #     1  --|DGND                 5V IN |--  40
> #     2  --|DGND                 DGND  |--  39
> #     3  --|PIN3  dual           PIN38 |--  38 dual/gclk
> #     4  --|PIN4  dual           PIN37 |--  37 dual
> #     5  --|PIN5  rhclk/dual     PIN36 |--  36 I/O
> #     6  --|PIN6  rhclk/dual     PIN35 |--  35 dual/gclk
> #     7  --|PIN7  rhclk/dual     PIN34 |--  34 lhclk
> #     8  --|PIN8  rhclk/dual     PIN33 |--  33 lhclk
> #     9  --|PIN9  rhclk/dual     PIN32 |--  32 I/O
> #     10 --|PIN10 I/0            PIN31 |--  31 lhclk
> #     11 --|PIN11 dual           PIN30 |--  30 I/O
> #     12 --|PIN12 dual           PIN29 |--  29 lhclk
> #     13 --|PIN13 lhclk          PIN28 |--  28 lhclk
> #     14 --|PIN14 rhclk/dual     PIN27 |--  27 I/O
> #     15 --|PIN15 dual           PIN26 |--  26 I/O
> #     16 --|PIN16 gclk           PIN25 |--  25 I/O
> #     17 --|PIN17 gclk           PIN24 |--  24 vref
> #     18 --|PIN18 lhclk          PIN23 |--  23 I/O
> #     19 --|DGND                 DGND  |--  22
> #     20 --|DGND                 DGND  |--  21
>
> I checked against the Xilinx documentation for the type associated
> with the pins so I mapped them out using xilinx ds312.pdf and came up
> with this type configuration for CP132 Ball.
>
> It seems what I put out on the output pins is relevant.  Pin15 has a
> 1/4 second blink code, while pins 17 and 18 have a 2mhz signal going
> out and all is OK.
> If I swap pins 15 and 18,  I lock up.   IF I drive  Pin 13 with the
> 2mhz signal, no problem also.
>
> Simply put, if I drive PIN13 or PIN18 (the lhclk types) at 2mhz, no
> problem, but if I drive them at 4hz, they lock up the fpga.
>
> Any insight or suggested reading/ places to look in the multitude of
> summary reports that ISE generates?  I found it strange that nothing
> strange appears in the build process or in testbench, but when I
> download the program, the FPGA locks up and only a power down and up
> resets it.

Ok, its not that simple.   I've been messing with this all day.  I
can't find a pattern
that is repeatable.

Right now I'm driving PIN18 at 2mhz 50% duty cycle, and PIN 17
similiarly.

If I so much as add PIN 15 to the UCF, the PORT layout, and simply tie
the same
std_logic wire that drives PIN18 to PIN15, the FPGA fails.

I also checked the pin's types once more, I documented them wrong. it
turns out PIN15 is not DUAL but rather I/O
the layout of the pins is:

 #     1  --|DGND                 5V IN |--  40
 #     2  --|DGND                 DGND  |--  39
 #     3  --|PIN3  dual           PIN38 |--  38 dual/gclk
 #     4  --|PIN4  dual           PIN37 |--  37 dual
 #     5  --|PIN5  rhclk/dual     PIN36 |--  36 I/O
 #     6  --|PIN6  rhclk/dual     PIN35 |--  35 dual/gclk
 #     7  --|PIN7  rhclk/dual     PIN34 |--  34 lhclk
 #     8  --|PIN8  rhclk/dual     PIN33 |--  33 lhclk
 #     9  --|PIN9  rhclk/dual     PIN32 |--  32 I/O
 #     10 --|PIN10 I/0            PIN31 |--  31 lhclk
 #     11 --|PIN11 dual           PIN30 |--  30 I/O
 #     12 --|PIN12 dual           PIN29 |--  29 lhclk
 #     13 --|PIN13 lhclk          PIN28 |--  28 lhclk
 #     14 --|PIN14 rhclk/dual     PIN27 |--  27 I/O
 #     15 --|PIN15 I/O            PIN26 |--  26 I/O
 #     16 --|PIN16 gclk           PIN25 |--  25 I/O
 #     17 --|PIN17 gclk           PIN24 |--  24 vref
 #     18 --|PIN18 lhclk          PIN23 |--  23 I/O
 #     19 --|DGND                 DGND  |--  22
 #     20 --|DGND                 DGND  |--  21


It really got frustrating for a while,  I added Pin13 for a stretch,
and then deleted it but no matter what I did,
The place and route report complained that PIN13 was unrouted.  The
pinout report also showed PIN13 in there.
No amount of  of re-run all fixed the problem.  I made a new project,
dragged copies of my sources over, and re-built the project, and that
finally destroyed all references to the PIN13  However since then,
Even if I try and drive pin 15 at 4hz, it fails.

I don't know if I'm supposed to be changing some of the defaults in
the build process, or if I need to update my ISE package.

My ISE package is 10.1 and I also loaded service pack 3, but I know
there are more patches to the software available.  I just hate to load
updates unless I know they are directly associated to some
functionality I need.

Article: 139876
Subject: Dual-frequency quartz oscillator with a FPGA ?
From: whygee <whygee@yg.yg>
Date: Sat, 18 Apr 2009 01:03:28 +0200
Links: << >>  << T >>  << A >>
Hello,

this is with great emotion that I am designing my first FPGA board.
However, the clock frequency that I desire is only available as
a discrete quartz, not oscillator (and integrated oscillators are more expensive).
And I don't find a dedicated quartz input in the chips I use
(the eval boards all use integrated oscillators).
There is no way I can use the PLL to get the desired frequencies
because the ratio is quite complex and would result in unacceptable drift
(not that it matters now but it's better to do things correctly
from the beginning, and now is the best time since it's a first draft).

So I have to make a quartz oscillator circuit and it would use the
FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
with 18pF capacitors to the ground and a series resistor (1K Ohm)
that limits the current in the quartz (I have seen other values as well).
I could use an external single not gate to reduce the chance of
parasitic pickup but I would like to keep the circuit simple now
and drift is more annoying than jitter, since a PLL will generate
higher frequencies and this will be filtered.

In VHDL this amounts to something like

  OSC_out <= not( OSC_in ) and OSC_EN;
  PLL_in <= OSC_in;

* OSC_out would be in low drive configuration (like 2mA)
with a series resistor.

* OSC_in would be tied to a pin that connects directly to the PLL
   and/or the internal clock network.


I also need to select one quartz among 2 as a source for the
base clock. I would like to connect the 2 quartz with a common OSC_in pin,
while each quartz has a dedicated OSC_outX pin.
This is the simplest idea I can find, with a relatively benign
transition mechanism : only the transition signal has to be
synchronised (a couple of D latches), instead of having 2 separate
clocks that must run simultaneously.
It also avoids a 4-register "glitch-free switch"
(see http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitchfree.html )
and the transition does not create a dramatic phase change.
I even wonder what would happen if the 2 quartz are
temporarily used in parallel (so the new quartz will start up a few
cycles before transition). Note that frequency changes should
not occur often and the frequencies are only 10% apart.

OSC_out1 <= not( OSC_in ) if ( OSC_en1 == '1' ) else 'Z'
OSC_out2 <= not( OSC_in ) if ( OSC_en2 == '1' ) else 'Z'

===> OSC_en1 and OSC_en2 could overlap during a few cycles

Did I miss something ? Do I forget any trap with quartz oscillators
and FPGAs ? Does the routing in the FPGA fabric play a big role
(considering a frequency in the 10MHz range) ? How can I be sure
that the oscillator will start up and switch correctly ?
How many cycles should the frequency overlap last ?
Is there a better method ?
Has anybody done this, and what are the results ?

Thank you for sharing your thoughts,
yg

-- 
http://ygdes.com / http://yasep.org

Article: 139877
Subject: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
From: mng <michael.jh.ng@gmail.com>
Date: Fri, 17 Apr 2009 17:29:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 17, 5:44=A0am, olliH <oliver.hofh...@googlemail.com> wrote:
> On 17 Apr., 00:20, mng <michael.jh...@gmail.com> wrote:
>
>
>
> > On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com"
>
> > <oliver.hofh...@googlemail.com> wrote:
> > > Hi everybody,
>
> > > in my design i have a timing problem with an ADC. I have this problem
> > > since my design has become more dense:
> > > [...]
> > > How do i now define the relationship between the CLK-output and the
> > > SCLK-input for example? In the datasheet are the timing-
> > > specifications.
>
> > CLK to SCLK varies from 100 to 300 ns. Your clock has a period of
> > 10ns, so I am not sure what you want to accomplish with timing
> > constraints. How do you communicate with the ADC?
>
> > -Mike
>
> Hi, the ADC is directly connected to the FPGA-Pins. The communication
> is realized with a state machine that runs in the fpga.

The ADC CLK is ~2 MHz or less, and your FPGA runs at 100 MHz. In this
situation I would simply sample SCLK for rising edges -- timing
constraints aren't useful here. If you are trying to do it a different
way, I have no idea what it is, and you will have to provide more
details.

-Mike

Article: 139878
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Fri, 17 Apr 2009 21:42:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 2:03=A0am, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

I have tried chrystal drive with Xilinx spartan-3A, and failed - it
did not work reliable
- if you look at msgs here, then Xilinx is keep saying it is NOT
DOABLE..

OTOH Lattice say they do this XP devices

so please test the circuit that it really works as reliable as needed
the xilinx oscillator had startup problems, and I never got it
starting
reliable with correct frequency

Antti












Article: 139879
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: Peter Alfke <alfke@sbcglobal.net>
Date: Fri, 17 Apr 2009 23:20:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 17, 4:03=A0pm, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

To build a reliable xtal oscillator, you need a single-stage inverting
amplifier with moderate gain and moderate roll-off (phase response) at
high frequency.
Using an FPGA input + output loop, you get a multi-stage amplifier
with enormous gain, poor phase response, plus hysteresis.
That does not give you an oscillator that starts reliably under all
circumstances.
Buy a canned oscillator, manufactured by people who know this
business.
Last time we at Xilinx offered a specialized single-stage oscillator-
amplifier was in the XC3000 family, 20 years ago. And it still gave us
headaches under extreme conditions ( 32 kHz, high temp, low temp, etc)
Peter Alfke
Peter Alfke

Article: 139880
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Fri, 17 Apr 2009 23:45:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 9:20=A0am, Peter Alfke <al...@sbcglobal.net> wrote:
> On Apr 17, 4:03=A0pm, whygee <why...@yg.yg> wrote:
>
>
>
>
>
> > Hello,
>
> > this is with great emotion that I am designing my first FPGA board.
> > However, the clock frequency that I desire is only available as
> > a discrete quartz, not oscillator (and integrated oscillators are more =
expensive).
> > And I don't find a dedicated quartz input in the chips I use
> > (the eval boards all use integrated oscillators).
> > There is no way I can use the PLL to get the desired frequencies
> > because the ratio is quite complex and would result in unacceptable dri=
ft
> > (not that it matters now but it's better to do things correctly
> > from the beginning, and now is the best time since it's a first draft).
>
> > So I have to make a quartz oscillator circuit and it would use the
> > FPGA I/Os. To the best of my knowledge, this is a "simple inverting gat=
e"
> > with 18pF capacitors to the ground and a series resistor (1K Ohm)
> > that limits the current in the quartz (I have seen other values as well=
).
> > I could use an external single not gate to reduce the chance of
> > parasitic pickup but I would like to keep the circuit simple now
> > and drift is more annoying than jitter, since a PLL will generate
> > higher frequencies and this will be filtered.
>
> > In VHDL this amounts to something like
>
> > =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> > =A0 PLL_in <=3D OSC_in;
>
> > * OSC_out would be in low drive configuration (like 2mA)
> > with a series resistor.
>
> > * OSC_in would be tied to a pin that connects directly to the PLL
> > =A0 =A0and/or the internal clock network.
>
> > I also need to select one quartz among 2 as a source for the
> > base clock. I would like to connect the 2 quartz with a common OSC_in p=
in,
> > while each quartz has a dedicated OSC_outX pin.
> > This is the simplest idea I can find, with a relatively benign
> > transition mechanism : only the transition signal has to be
> > synchronised (a couple of D latches), instead of having 2 separate
> > clocks that must run simultaneously.
> > It also avoids a 4-register "glitch-free switch"
> > (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-=
sw...)
> > and the transition does not create a dramatic phase change.
> > I even wonder what would happen if the 2 quartz are
> > temporarily used in parallel (so the new quartz will start up a few
> > cycles before transition). Note that frequency changes should
> > not occur often and the frequencies are only 10% apart.
>
> > OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> > OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> > =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> > Did I miss something ? Do I forget any trap with quartz oscillators
> > and FPGAs ? Does the routing in the FPGA fabric play a big role
> > (considering a frequency in the 10MHz range) ? How can I be sure
> > that the oscillator will start up and switch correctly ?
> > How many cycles should the frequency overlap last ?
> > Is there a better method ?
> > Has anybody done this, and what are the results ?
>
> > Thank you for sharing your thoughts,
> > yg
>
> > --http://ygdes.com/http://yasep.org
>
> To build a reliable xtal oscillator, you need a single-stage inverting
> amplifier with moderate gain and moderate roll-off (phase response) at
> high frequency.
> Using an FPGA input + output loop, you get a multi-stage amplifier
> with enormous gain, poor phase response, plus hysteresis.
> That does not give you an oscillator that starts reliably under all
> circumstances.
> Buy a canned oscillator, manufactured by people who know this
> business.
> Last time we at Xilinx offered a specialized single-stage oscillator-
> amplifier was in the XC3000 family, 20 years ago. And it still gave us
> headaches under extreme conditions ( 32 kHz, high temp, low temp, etc)
> Peter Alfke
> Peter Alfke- Hide quoted text -
>
> - Show quoted text -

Peter

the issue is that canned oscillators are not available for all
frequencies,
and sometimes the on chip clock can not be used to generate the
required frequency.

I assume the OP is targetting Actel FPGA not Xilinx part. Well the
basics still apply
so I would also suggest canned oscillator, and

actel PLL can work in frequency dither mode where user circuitry is
connected into
feedback loop, this allows pretty much any frequency to be generated
and switched
on the fly as well

actel app note is for proasic, but it would work on pa3 as well, but a
pin to pin
loopback wire is required because of clock routing restrictions

similar technic was also used by Ken Chapman for S3E, again there is
no
ready made solution for S3A, but after some experiments i have
succeeded
with S3A also. S6 has PLL already... but i think OP needs solution now
and not 2011

Antti

















Article: 139881
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Fri, 17 Apr 2009 23:47:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 2:03=A0am, whygee <why...@yg.yg> wrote:
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more ex=
pensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
> =A0 OSC_out <=3D not( OSC_in ) and OSC_EN;
> =A0 PLL_in <=3D OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
> =A0 =A0and/or the internal clock network.
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin=
,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (seehttp://www.design-reuse.com/articles/5827/techniques-to-make-clock-sw=
...)
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <=3D not( OSC_in ) if ( OSC_en1 =3D=3D '1' ) else 'Z'
> OSC_out2 <=3D not( OSC_in ) if ( OSC_en2 =3D=3D '1' ) else 'Z'
>
> =3D=3D=3D> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> --http://ygdes.com/http://yasep.org

actel Fusion has crhystal osc support, but only for one chrystal

Antti



Article: 139882
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: whygee <whygee@yg.yg>
Date: Sat, 18 Apr 2009 11:01:35 +0200
Links: << >>  << T >>  << A >>
Thank you for the useful answers :-)

Antti.Lukats@googlemail.com wrote:
> actel Fusion has crhystal osc support, but only for one chrystal

The fusion osc is meant for a 32768Hz Xtal, not the 10MHz range
(I should check though) and I target the A3P125-250 type
(that's much cheaper... and i'll look at the analog stuff later)


> Antti
yg

-- 
http://ygdes.com / http://yasep.org

Article: 139883
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: -jg <Jim.Granville@gmail.com>
Date: Sat, 18 Apr 2009 02:07:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 11:03=A0am, whygee <why...@yg.yg> wrote:
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?

As others have said, unreliable and risky.,

If you want Xtal operation, use something like TinyLogic 74LVC1GX04
crystal oscillator
or, use 74LVC2GU04

Oscillators have a startup time, so you may prefer to run them all the
time, and
switch inside the FPGA.

-jg



Article: 139884
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: "Andrew Holme" <ah@nospam.co.uk>
Date: Sat, 18 Apr 2009 10:11:12 +0100
Links: << >>  << T >>  << A >>

"whygee" <whygee@yg.yg> wrote in message 
news:49e90f52$0$21740$7a628cd7@news.club-internet.fr...
> Hello,
>
> this is with great emotion that I am designing my first FPGA board.
> However, the clock frequency that I desire is only available as
> a discrete quartz, not oscillator (and integrated oscillators are more 
> expensive).
> And I don't find a dedicated quartz input in the chips I use
> (the eval boards all use integrated oscillators).
> There is no way I can use the PLL to get the desired frequencies
> because the ratio is quite complex and would result in unacceptable drift
> (not that it matters now but it's better to do things correctly
> from the beginning, and now is the best time since it's a first draft).
>
> So I have to make a quartz oscillator circuit and it would use the
> FPGA I/Os. To the best of my knowledge, this is a "simple inverting gate"
> with 18pF capacitors to the ground and a series resistor (1K Ohm)
> that limits the current in the quartz (I have seen other values as well).
> I could use an external single not gate to reduce the chance of
> parasitic pickup but I would like to keep the circuit simple now
> and drift is more annoying than jitter, since a PLL will generate
> higher frequencies and this will be filtered.
>
> In VHDL this amounts to something like
>
>  OSC_out <= not( OSC_in ) and OSC_EN;
>  PLL_in <= OSC_in;
>
> * OSC_out would be in low drive configuration (like 2mA)
> with a series resistor.
>
> * OSC_in would be tied to a pin that connects directly to the PLL
>   and/or the internal clock network.
>
>
> I also need to select one quartz among 2 as a source for the
> base clock. I would like to connect the 2 quartz with a common OSC_in pin,
> while each quartz has a dedicated OSC_outX pin.
> This is the simplest idea I can find, with a relatively benign
> transition mechanism : only the transition signal has to be
> synchronised (a couple of D latches), instead of having 2 separate
> clocks that must run simultaneously.
> It also avoids a 4-register "glitch-free switch"
> (see 
> http://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitchfree.html )
> and the transition does not create a dramatic phase change.
> I even wonder what would happen if the 2 quartz are
> temporarily used in parallel (so the new quartz will start up a few
> cycles before transition). Note that frequency changes should
> not occur often and the frequencies are only 10% apart.
>
> OSC_out1 <= not( OSC_in ) if ( OSC_en1 == '1' ) else 'Z'
> OSC_out2 <= not( OSC_in ) if ( OSC_en2 == '1' ) else 'Z'
>
> ===> OSC_en1 and OSC_en2 could overlap during a few cycles
>
> Did I miss something ? Do I forget any trap with quartz oscillators
> and FPGAs ? Does the routing in the FPGA fabric play a big role
> (considering a frequency in the 10MHz range) ? How can I be sure
> that the oscillator will start up and switch correctly ?
> How many cycles should the frequency overlap last ?
> Is there a better method ?
> Has anybody done this, and what are the results ?
>
> Thank you for sharing your thoughts,
> yg
>
> -- 
> http://ygdes.com / http://yasep.org

What exact frequencies do you need?

Canned oscillators are made to order by several crystal vendors.

Or, use external single unbuffered CMOS inverter gates e.g. SN74AHC1GU04.

You forgot to mention the feedback resistor which biases the gate into its 
linear region.  This works best with a single gate, not multiple stages as 
you would inevitably have going on and off an FPGA.  There's too much gain. 
It just can't hold them all at 0.5*VDD.  Even if it starts, it may not 
oscillate on the crystal frequency!

You did mention the series current limiting resistor, which is a good idea 
BTW and 1k is a good ballpark value for this.  The feedback resistor can be 
220k - 1M.  The capacitors are chosen to suit the crystal.



Article: 139885
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: whygee <whygee@yg.yg>
Date: Sat, 18 Apr 2009 11:42:21 +0200
Links: << >>  << T >>  << A >>
Hello again.

Here are some other answers that overlap with other posts.

-jg wrote:
> As others have said, unreliable and risky.,
I was not sure but Peter Alfke gave good arguments why.
I forgot about the gain/phase things...

I have also experienced a reverse situation with a PIC,
which did not work with a canned oscillator, but everything
was fine with a cristal... I still wonder why.

> If you want Xtal operation, use something like TinyLogic 74LVC1GX04
> crystal oscillator or, use 74LVC2GU04
I'm checking this too.

I've also found a working example's schematic using a couple of 74HC14 gates,
two 1M resistors and the usual couple of capacitors...
and I wonder again why a couple of FPGA pins wouldn't work :-/

> Oscillators have a startup time,
I know that this time depends on the capacitors too.

> so you may prefer to run them all the
> time, and switch inside the FPGA.
This means continuous power draw...
even a few mA can matter, not for the proto but in the end... :-/
I'll probably switch to the Igloo family later, too.

It looks like i'll have to choose one fixed frequency
and give up the others, or i'll have to end up with 3 or 4
Xtal operating  simultaneously...
Fortunately, FPGAs have integrated PLLs today.

> -jg
yg

-- 
http://ygdes.com / http://yasep.org

Article: 139886
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Sat, 18 Apr 2009 11:44:42 +0100
Links: << >>  << T >>  << A >>
On Fri, 17 Apr 2009 15:29:24 -0700 (PDT), jleslie48 <jon@jonathanleslie.com>
wrote:

>On Apr 17, 10:55 am, jleslie48 <j...@jonathanleslie.com> wrote:
>> here's the pinout of a board I'm using:

>Ok, its not that simple.   I've been messing with this all day.  I
>can't find a pattern
>that is repeatable.

>No amount of  of re-run all fixed the problem.  I made a new project,
>dragged copies of my sources over, and re-built the project, and that
>finally destroyed all references to the PIN13  However since then,
>Even if I try and drive pin 15 at 4hz, it fails.

There has to be something else going on...

One question: where are you getting a 4Hz clock?

Does it have a reasonable rise/fall time or such a slow ramp that the Xilinx
input buffers are oscillating like crazy as it passes through the transition
region?

You might be better using a 100MHz clock and a 4Hz enable signal...

- Brian


Article: 139887
Subject: Re: FPGA Buying
From: John Adair <g1@enterpoint.co.uk>
Date: Sat, 18 Apr 2009 03:51:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
Giuseppe

There is lots of choice out there depending on what you want to do. A
programing kit may be just that and not actually have a board with it.
Items refered as starter Kits very often have all hardware items
necessary and sometimes software as well. The main items to check are
(1) A board that has the interfaces and logic size you might need. (2)
A programming cable. If it Xilinx or an Altera board you can get free
versions of the software that support a limited range of devices.
Usually the devices not supported are the more expensive or bigger
parts. For xilinx http://www.xilinx.com/publications/prod_mktg/pn0010867.pd=
f
will tell you what devices are supported in the free Webpack version
of the ISE tool.

>From our range Drigmorn1 http://www.enterpoint.co.uk/component_replacements=
/drigmorn1.html
and Polmaddie1 http://www.enterpoint.co.uk/cpld_boards/polmaddie1.html
are simple cheap boards to start with. Most of products come with
programming cables with the exception of OEM/industrial type products
with Craignell, Darnaw and Hollybush where it is an option. If you
want one of our larger boards our UAP program offers discounts to
students.

John Adair
Enterpoint Ltd.


On 17 Apr, 17:54, "Ged" <ciro.ross...@alice.it> wrote:
> Hallo! Ok, I will not buy XSA-50 used from my professor. I am a very newb=
ie
> in this world, so I would like some advice on wich board I can buy. Wich =
is
> the difference between a board and a programming kit? Wich the best choic=
e
> for a newbie that want to start? Thank you very much!
>
> Best regards,
> =A0 =A0 =A0 =A0 =A0 =A0 Giuseppe Rossini


Article: 139888
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: John Adair <g1@enterpoint.co.uk>
Date: Sat, 18 Apr 2009 04:05:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On cost the new MEMS oscillators very often compete well with
crystals. If you are worried about the power why not control the
oscillator power with a mosfet and simply turn it off when not in use.
There a lot of the newer MEMS oscillators that don't use mush power
and are physically very small. Spot the 25MHz MEMs oscillator on here
http://www.enterpoint.co.uk/component_replacements/craignell2.html and
that's not the smallest one we are using.

John Adair
Enterpoint Ltd.

On 18 Apr, 10:42, whygee <why...@yg.yg> wrote:
> Hello again.
>
> Here are some other answers that overlap with other posts.
>
> -jg wrote:
> > As others have said, unreliable and risky.,
>
> I was not sure but Peter Alfke gave good arguments why.
> I forgot about the gain/phase things...
>
> I have also experienced a reverse situation with a PIC,
> which did not work with a canned oscillator, but everything
> was fine with a cristal... I still wonder why.
>
> > If you want Xtal operation, use something like TinyLogic 74LVC1GX04
> > crystal oscillator or, use 74LVC2GU04
>
> I'm checking this too.
>
> I've also found a working example's schematic using a couple of 74HC14 ga=
tes,
> two 1M resistors and the usual couple of capacitors...
> and I wonder again why a couple of FPGA pins wouldn't work :-/
>
> > Oscillators have a startup time,
>
> I know that this time depends on the capacitors too.
>
> > so you may prefer to run them all the
> > time, and switch inside the FPGA.
>
> This means continuous power draw...
> even a few mA can matter, not for the proto but in the end... :-/
> I'll probably switch to the Igloo family later, too.
>
> It looks like i'll have to choose one fixed frequency
> and give up the others, or i'll have to end up with 3 or 4
> Xtal operating =A0simultaneously...
> Fortunately, FPGAs have integrated PLLs today.
>
> > -jg
>
> yg
>
> --http://ygdes.com/http://yasep.org


Article: 139889
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: whygee <whygee@yg.yg>
Date: Sat, 18 Apr 2009 15:16:04 +0200
Links: << >>  << T >>  << A >>
Hello,

John Adair wrote:
> On cost the new MEMS oscillators very often compete well with crystals.=

MEMS oscillators are not as widely available as quartz :-/

> If you are worried about the power why not control the
> oscillator power with a mosfet and simply turn it off when not in use.
In fact i'll keep it constantly on,
and the PLL will derive other / higher frequencies.
for the rest of the system.

> There a lot of the newer MEMS oscillators that don't use mush power
> and are physically very small. Spot the 25MHz MEMs oscillator on here
> http://www.enterpoint.co.uk/component_replacements/craignell2.html and
> that's not the smallest one we are using.

Nice board. My issue though is : is your oscillator available
in 11.2896MHz frequency, and at what cost ? The solution I have
found costs around 0.6=80 in small (10-100) quantities.
The can is a bit larger (H49 size) than today's miniature
standards but it's not an issue here.

> John Adair
> Enterpoint Ltd.
yg

--=20
http://ygdes.com / http://yasep.org

Article: 139890
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: "David Spencer" <davidmspencer@verizon.net>
Date: Sat, 18 Apr 2009 15:13:24 GMT
Links: << >>  << T >>  << A >>
> Nice board. My issue though is : is your oscillator available
> in 11.2896MHz frequency, and at what cost ? The solution I have
> found costs around 0.6 in small (10-100) quantities.
> The can is a bit larger (H49 size) than today's miniature
> standards but it's not an issue here.

It took me less than 30 seconds on the web to find an oscillator at that 
frequency: 
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=ASML-11.2896MHZ-ET-ND




Article: 139891
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: jleslie48 <jon@jonathanleslie.com>
Date: Sat, 18 Apr 2009 09:56:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 6:44 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Fri, 17 Apr 2009 15:29:24 -0700 (PDT), jleslie48 <j...@jonathanleslie.com>
> wrote:
>
> >On Apr 17, 10:55 am, jleslie48 <j...@jonathanleslie.com> wrote:
> >> here's the pinout of a board I'm using:
> >Ok, its not that simple.   I've been messing with this all day.  I
> >can't find a pattern
> >that is repeatable.
> >No amount of  of re-run all fixed the problem.  I made a new project,
> >dragged copies of my sources over, and re-built the project, and that
> >finally destroyed all references to the PIN13  However since then,
> >Even if I try and drive pin 15 at 4hz, it fails.
>
> There has to be something else going on...
>
> One question: where are you getting a 4Hz clock?
>
> Does it have a reasonable rise/fall time or such a slow ramp that the Xilinx
> input buffers are oscillating like crazy as it passes through the transition
> region?
>
> You might be better using a 100MHz clock and a 4Hz enable signal...
>
> - Brian

the system has a 40Mhz oscillator and I set a countdown counter to
10,000,000,
subtract 1 every oscillator clock and
at 0 I reset the counter to10,000,000 and:

clk_4hz <= not clk_4hz;

something like that, I don't have the exact code in front of me.

bascially I use this as a heartbeat indicator for the FPGA,  I use
this heartbeat to drive an
led so I know the program is running;  I've been doing it for years on
systems.  I also will
enhance the blink code occasionally to indicate software versons.
This way if a field test engineer
is having an issue, Over the phone I can have him check the blink
pattern (ex dot,dot,dot, off, dot,dot,dot ...)
and I can know if he has the right version of code or not by making
sure that I change the blink code on each
version of the code.

Meantime, I wrote some code that worked great and put out my 2mhz
signal just fine.  I then tried to copy the
blink code to a pin that is connected to a header so I put the blink
code on the front panel of the project box, and
all of a sudden I stuck on this ridiculous problem.  GRRRRRR.....

I also will need to duplicate the 2mhz signal to as many as 4 output
pins, this kind of stuff should be a no-brainer but I must have some
underlying issue of no-no's under the surface.  I'm willing to bet the
FPGA lockup on adding the pin connection is just because by adding
that bit of logic things get moved around during the SIG (synthesis,
implement, generate) just enough so that my mistake ends up causing a
lock up.  I did have the driver on pin15 at 1/4 second working at one
time, but then I tried to add pin 13, it died, and then when I removed
the logic for pin 13, pin 15 was broken as well.

This ISE 10.1 is very buggy.  I have a whole list of WTF???  and
situations where I just crashed it.  I've only installed service pack
3, and I know there are some other patches that go, but until someone
says "oh yeah!!!  I had that problem if you update ISE 10.1 with xyz
then the problem is fixed!!!!"   I'm reluctant to introduce the new
variable of a software patch.






Article: 139892
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: whygee <whygee@yg.yg>
Date: Sat, 18 Apr 2009 19:02:03 +0200
Links: << >>  << T >>  << A >>
hi !

David Spencer wrote:
> It took me less than 30 seconds on the web to find an oscillator at that frequency: 
> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=ASML-11.2896MHZ-ET-ND

thank you.
However, I see 2 things :
  - no stock available
  - quantity by 1000 which is not "prototype-friendly"
Ok, I know, this can change and I can look elsewhere etc.

I think that i'll quit this thread here since
my initial question has been answered previously,
and it's now an uninteresting matter of component sourcing...

regards,
yg

-- 
http://ygdes.com / http://yasep.org

Article: 139893
Subject: Why is XST optimizing away my registers and how do I stop it?
From: mooo <randomname650@gmail.com>
Date: Sat, 18 Apr 2009 10:52:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have a simple verilog program that increments a 32 bit counter,
converts the number to an ASCII string using $sformat and then pushes
the string to the host machine 1 byte at a time using an FTDI FT245RL.

Unfortunately Xilinx XST keeps optimizing away the string register
vector. I've tried mucking around with various initialization and
access routines with no success. I can't seem to turn off
optimization, and all of the examples I find online differ very little
from my initialization routines. What am I doing wrong?  I'm using ISE
webpack 10.1, latest patches.

module counter(CK12, TXE_, WR, RD_, LED, USBD);

   input CK12;
   input TXE_;
   output WR;
   output RD_;
   output [7:0] LED;
   inout [7:0] USBD;

   reg [31:0] count = 0;

   reg [7:0] k;
   reg wrf  = 0;
   reg rd   = 1;
   reg [7:0] lbyte = 8'b00000000;

   reg td                  = 1;
   parameter MEM_SIZE  = 88;
   parameter STR_SIZE  = 11;
   reg [MEM_SIZE - 1:0] str;
   reg [7:0] strpos = 8'b00000000;

   initial
     begin
        for (k = 0; k < MEM_SIZE; k = k + 1)
          begin
                 str[k]    = 0;
          end
     end

   always @(posedge CK12)
     begin
        if (TXE_ == 0 && wrf == 1)
          begin
                 count    = count + 1;
                 wrf         = 0;
          end


        else if (wrf == 0)  // If we've already lowered the strobe,
latch the data
          begin
                 if(td)
                   begin
                          $sformat(str, "%0000000000d\n", count);
                          strpos = 0;
                          td     = 0;
                   end

                 str      = str << 8;
                 wrf             = 1;
                 strpos          = strpos + 1;

                 if(strpos == STR_SIZE)
                   td            = 1;

          end
     end

   assign RD_                     = rd;
   assign WR                      = wrf;
   assign USBD                = str[87:80];
   assign LED                     = count[31:24];

endmodule



Loading device for application Rf_Device from file '3s100e.nph' in
environment /opt/Xilinx/10.1/ISE. WARNING:Xst:1293 - FF/Latch str_0
has a constant value of 0 in block . This FF/Latch will be trimmed
during the optimization process.

WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_1 has
a constant value of 0 in block . This FF/Latch will be trimmed during
the optimization process.

WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_2 has
a constant value of 0 in block . This FF/Latch will be trimmed during
the optimization process.

Article: 139894
Subject: Re: Why is XST optimizing away my registers and how do I stop it?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Sat, 18 Apr 2009 11:14:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 8:52=A0pm, mooo <randomname...@gmail.com> wrote:
> I have a simple verilog program that increments a 32 bit counter,
> converts the number to an ASCII string using $sformat and then pushes
> the string to the host machine 1 byte at a time using an FTDI FT245RL.
>
> Unfortunately Xilinx XST keeps optimizing away the string register
> vector. I've tried mucking around with various initialization and
> access routines with no success. I can't seem to turn off
> optimization, and all of the examples I find online differ very little
> from my initialization routines. What am I doing wrong? =A0I'm using ISE
> webpack 10.1, latest patches.
>
> module counter(CK12, TXE_, WR, RD_, LED, USBD);
>
> =A0 =A0input CK12;
> =A0 =A0input TXE_;
> =A0 =A0output WR;
> =A0 =A0output RD_;
> =A0 =A0output [7:0] LED;
> =A0 =A0inout [7:0] USBD;
>
> =A0 =A0reg [31:0] count =3D 0;
>
> =A0 =A0reg [7:0] k;
> =A0 =A0reg wrf =A0=3D 0;
> =A0 =A0reg rd =A0 =3D 1;
> =A0 =A0reg [7:0] lbyte =3D 8'b00000000;
>
> =A0 =A0reg td =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D 1;
> =A0 =A0parameter MEM_SIZE =A0=3D 88;
> =A0 =A0parameter STR_SIZE =A0=3D 11;
> =A0 =A0reg [MEM_SIZE - 1:0] str;
> =A0 =A0reg [7:0] strpos =3D 8'b00000000;
>
> =A0 =A0initial
> =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 for (k =3D 0; k < MEM_SIZE; k =3D k + 1)
> =A0 =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0str[k] =A0 =A0=3D 0;
> =A0 =A0 =A0 =A0 =A0 end
> =A0 =A0 =A0end
>
> =A0 =A0always @(posedge CK12)
> =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 if (TXE_ =3D=3D 0 && wrf =3D=3D 1)
> =A0 =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0count =A0 =A0=3D count + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0wrf =A0 =A0 =A0 =A0 =3D 0;
> =A0 =A0 =A0 =A0 =A0 end
>
> =A0 =A0 =A0 =A0 else if (wrf =3D=3D 0) =A0// If we've already lowered the=
 strobe,
> latch the data
> =A0 =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(td)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 $sformat(str, "%00000=
00000d\n", count);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 strpos =3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 td =A0 =A0 =3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0str =A0 =A0 =A0=3D str << 8;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0wrf =A0 =A0 =A0 =A0 =A0 =A0 =3D 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0strpos =A0 =A0 =A0 =A0 =A0=3D strpos +=
 1;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(strpos =3D=3D STR_SIZE)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0td =A0 =A0 =A0 =A0 =A0 =A0=3D 1;
>
> =A0 =A0 =A0 =A0 =A0 end
> =A0 =A0 =A0end
>
> =A0 =A0assign RD_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D rd;
> =A0 =A0assign WR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D wrf;
> =A0 =A0assign USBD =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D str[87:80];
> =A0 =A0assign LED =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D count[31:24=
];
>
> endmodule
>
> Loading device for application Rf_Device from file '3s100e.nph' in
> environment /opt/Xilinx/10.1/ISE. WARNING:Xst:1293 - FF/Latch str_0
> has a constant value of 0 in block . This FF/Latch will be trimmed
> during the optimization process.
>
> WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_1 has
> a constant value of 0 in block . This FF/Latch will be trimmed during
> the optimization process.
>
> WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_2 has
> a constant value of 0 in block . This FF/Latch will be trimmed during
> the optimization process.

what do you think XST should synthesize for $sformat ????

and where did you see synthesizeable samples with $sformat ???



Antti

Article: 139895
Subject: Re: Why is XST optimizing away my registers and how do I stop it?
From: mooo <randomname650@gmail.com>
Date: Sat, 18 Apr 2009 11:26:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
I don't know, this is my third verilog program and I'm just tooling
around on my lonesome in my spare time.  I was googling around trying
to figure out how to convert a binary number to an ASCII string and
that's what I came up with.  How does one tell whether or not
something is synthesizeable?  I tried looking up what is or isn't
supported but wasn't able to find any such document.

> what do you think XST should synthesize for $sformat ????
>
> and where did you see synthesizeable samples with $sformat ???
>
> Antti


Article: 139896
Subject: Re: Why is XST optimizing away my registers and how do I stop it?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sat, 18 Apr 2009 18:31:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti.Lukats@googlemail.com <Antti.Lukats@googlemail.com> wrote:
> On Apr 18, 8:52?pm, mooo <randomname...@gmail.com> wrote:
>> I have a simple verilog program that increments a 32 bit counter,

This is the third post today with the phrase "verilog program"
in it.  Verilog is not a programming language, it is a hardware
description language.  If you think of it as programming
(at least in the FPGA case) you will get confused.

>> converts the number to an ASCII string using $sformat and then pushes
>> the string to the host machine 1 byte at a time using an FTDI FT245RL.
 
> what do you think XST should synthesize for $sformat ????

I agree, though it should print a message.

(It can't be that hard to do, but it will be big and slow.)

-- glen

Article: 139897
Subject: source for Spartan 3E chips
From: Alex Freed <alex_news@mirrow.com>
Date: Sat, 18 Apr 2009 14:52:06 -0700
Links: << >>  << T >>  << A >>

All,

I need 30 to 50 XC3S250E chips. The obvious source is
DigiKey but they only have quantity one price.
Is there a better place to buy?

-Alex.

Article: 139898
Subject: Re: Dual-frequency quartz oscillator with a FPGA ?
From: gabor <gabor@alacron.com>
Date: Sat, 18 Apr 2009 15:20:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 11:13=A0am, "David Spencer" <davidmspen...@verizon.net>
wrote:
> > Nice board. My issue though is : is your oscillator available
> > in 11.2896MHz frequency, and at what cost ? The solution I have
> > found costs around 0.6=80 in small (10-100) quantities.
> > The can is a bit larger (H49 size) than today's miniature
> > standards but it's not an issue here.
>
> It took me less than 30 seconds on the web to find an oscillator at that
> frequency:http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&nam=
e=3DASML...

If you want MEMS, go to the Ecliptek page
Here's one with factory stock:

http://www.ecliptek.com/stocksearch/Stock.aspx?Partnumber=3DEMK33G2H-11.289=
6M

I've used the 2 x 2.5mm (smallest) version of these and they
work very well and have better vibration tolerance than most
crystal oscillators.

Regards,
Gabor

Article: 139899
Subject: Re: Why is XST optimizing away my registers and how do I stop it?
From: gabor <gabor@alacron.com>
Date: Sat, 18 Apr 2009 15:29:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 18, 2:26=A0pm, mooo <randomname...@gmail.com> wrote:
> I don't know, this is my third verilog program and I'm just tooling
> around on my lonesome in my spare time. =A0I was googling around trying
> to figure out how to convert a binary number to an ASCII string and
> that's what I came up with. =A0How does one tell whether or not
> something is synthesizeable? =A0I tried looking up what is or isn't
> supported but wasn't able to find any such document.
>
> > what do you think XST should synthesize for $sformat ????
>
> > and where did you see synthesizeable samples with $sformat ???
>
> > Antti

There are a few good books on Verilog with detailed reference
to what is or isn't synthesizable.  Generally though as soon
as you see a dollar-sign as in $sformat you are out of
synthesizable range.  There are some exceptions like
$readmemh which can be used to initialize synthesizable
ROMs (for some synthesis tools).  The main differrence between
this and what you're trying to do is that the main function
happens during synthesis for the $readmemh case but
must be implemented in hardware for $sformat in your
case.  There may be some cases where you could
use $sformat on a constant and have something
synthesize, for example if you were trying to embed
today's date in a ROM.  In any case the point of the
system functions ($...) is that they run on your
host system, not the synthesized hardware.

There may be available code to do binary to string translation.
Doing it yourself would be a great learning exercise, though.

Regards,
Gabor



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