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Messages from 139975

Article: 139975
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 21 Apr 2009 10:48:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 10:08 am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Apr 21, 3:29 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
>
>
> > On Apr 21, 3:49 am, "Antti.Luk...@googlemail.com"
>
> > <Antti.Luk...@googlemail.com> wrote:
> > > On Apr 21, 10:31 am, djj08230 <djj08...@gmail.com> wrote:
>
> > > > On Apr 20, 7:43 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status
> > > > > register, CRC Error bit is NOT 0.
>
> > > > > a subsequent call to 'get device id' yields:
>
> > > > > // *** BATCH CMD : ReadIdcode -p 1
> > > > > INFO:iMPACT:583 - '1': The idcode read from the device does not match
> > > > > the idcode in the bsdl File.
> > > > > INFO:iMPACT:1578 - '1':  Device IDCODE :
> > > > > 00001111111111111111111111111111
> > > > > INFO:iMPACT:1579 - '1': Expected IDCODE:
> > > > > 00000001110000100010000010010011
>
> > > > > and a big red 'ReadIDcode failed' block pops up in instead of the nice
> > > > > blue block saying 'succeeded'
>
> > > > This may not be related to your VHDL at all.
> > > > When using a Spartan3 (not E) I recall experiencing a similar
> > > > behaviour. Configuration seemed not to be reliable when configuring
> > > > the FPGA directly and bypassing the serial FLASH.
> > > > Usually I had to power cycle a few times before being able to
> > > > succedfully configure the FPGA. I never got an explanation to this
> > > > behavior, it could be the board I was using, the tools or whatever. In
> > > > my case programing the serial flash and then rebooting the board got a
> > > > 100% success.
> > > > Another point worth checking is the programming cable you are using. I
> > > > used to get bad results with home made and cheap compatible programmig
> > > > cables. All problems seemed to dissapear when using official USB
> > > > Xilinx cable.
>
> > > > Josep- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > oh,
>
> > > I fogot to mention this
>
> > > YOU MUST ERASE platform flash for reliable JTAG configuration
>
> > > if you dont you may have random errors..
>
> > > Antti
>
> > Yes, I'm beginning to believe that this an error in the jtag loading
> > procedure and not my code.
>
> > Xilinx support wants me to try the following:
>
> > iMPACT and JTAG:
>
> >    A1. Provide an ordered list of devices in the JTAG chain
> >    A2. Note the cable speed (MHz), and try running the system at the
> > slowest cable speed possible
> >    A3. Collect the _impact.log in your project directory after
> > performing the failing operation
> >    A4. Read the Status Register after failing operations on an FPGA
> >    A5. Use the latest version of the software available from the
> > Download Center
>
> > Configuration via PROM:
>
> >    B1. What is the status of INIT and DONE
> >    B2. What configuration mode is being used
> >    B3. Will source files work via iMPACT
> >    B4. After the failed configuration attempt, read the Status
> > Register of the FPGA via iMPACT
> >    B5. Get scope shots of power supplies and control pins during
> > configuration, if possible
>
> > ------------------------------------------------------------------------
>
> > How do I accomplish A1, A2, A4, B1, B2, B4?
> > I can't find anything in this package...
> > Also the system is non-responsive after the CRC error, how can I (B4)
> > "read the Status Register of the FPGA via iMPACT"
> > or is there something that still might be responsive after the "lock
> > up"- Hide quoted text -
>
> > - Show quoted text -
>
> you cant scan JTAG chain after CRC error?
>
> if that so you have major hardware issue, get another board (another
> type of board!)
>
> the config prom can cause one time failure of jtag conf, but chain
> should remain scannable
>
> Antti

ok yeah, once the crc error happens its dead, I get:


----------------------------------------------------------------------------------------------------------
WARNING:iMPACT:2217 - Error shows in the status register, CRC Error
bit is NOT 0.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 1111 1111 1111 1111 1111 1111 1111 1111
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.
Attempting to identify devices in the boundary-scan chain
configuration...// *** BATCH CMD : Identify
PROGRESS_START - Starting Operation.
Identifying chain contents ....done.
ERROR:iMPACT:585 - A problem may exist in the hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	 that the power supply is adequate and delivering the correct
voltage.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
// *** BATCH CMD : identifyMPM

----------------------------------------------------------------------------------------------------------------

I have a second board, and it does the same thing, and remember all I
have to do to generate the problem is to drive pin15, and try and load
the FPGA thru the jtag header.

If I don't touch a cable, and simply comment out the driving of pin15
then all is well.

This led me to believe that the problem was with the pin usage,
however, if I take that same .bit program that drives PIN15 and kills
the FPGA, make a .MCS burn image out of it, load it into the SP flash
using the SPI header using the same cables as before, the program runs
fine, and I am even properly driving PIN15.

So it appears that driving PIN15 is not an issue at all when the
program loads from the SP flash, and I'm leaning to the conclusion
that the CRC error is a function of the impact 10.1 having an issue,
making higgley-piggley out of my program and locking up the FPGA.

Xilinx has no documentation of any of this, and their support, well
let's just leave it as leaves a lot to be desired.


Article: 139976
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 21 Apr 2009 10:53:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 1:48 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Apr 21, 10:08 am, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Apr 21, 3:29 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > On Apr 21, 3:49 am, "Antti.Luk...@googlemail.com"
>
> > > <Antti.Luk...@googlemail.com> wrote:
> > > > On Apr 21, 10:31 am, djj08230 <djj08...@gmail.com> wrote:
>
> > > > > On Apr 20, 7:43 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
> > > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status
> > > > > > register, CRC Error bit is NOT 0.
>
> > > > > > a subsequent call to 'get device id' yields:
>
> > > > > > // *** BATCH CMD : ReadIdcode -p 1
> > > > > > INFO:iMPACT:583 - '1': The idcode read from the device does not match
> > > > > > the idcode in the bsdl File.
> > > > > > INFO:iMPACT:1578 - '1':  Device IDCODE :
> > > > > > 00001111111111111111111111111111
> > > > > > INFO:iMPACT:1579 - '1': Expected IDCODE:
> > > > > > 00000001110000100010000010010011
>
> > > > > > and a big red 'ReadIDcode failed' block pops up in instead of the nice
> > > > > > blue block saying 'succeeded'
>
> > > > > This may not be related to your VHDL at all.
> > > > > When using a Spartan3 (not E) I recall experiencing a similar
> > > > > behaviour. Configuration seemed not to be reliable when configuring
> > > > > the FPGA directly and bypassing the serial FLASH.
> > > > > Usually I had to power cycle a few times before being able to
> > > > > succedfully configure the FPGA. I never got an explanation to this
> > > > > behavior, it could be the board I was using, the tools or whatever. In
> > > > > my case programing the serial flash and then rebooting the board got a
> > > > > 100% success.
> > > > > Another point worth checking is the programming cable you are using. I
> > > > > used to get bad results with home made and cheap compatible programmig
> > > > > cables. All problems seemed to dissapear when using official USB
> > > > > Xilinx cable.
>
> > > > > Josep- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > oh,
>
> > > > I fogot to mention this
>
> > > > YOU MUST ERASE platform flash for reliable JTAG configuration
>
> > > > if you dont you may have random errors..
>
> > > > Antti
>
> > > Yes, I'm beginning to believe that this an error in the jtag loading
> > > procedure and not my code.
>
> > > Xilinx support wants me to try the following:
>
> > > iMPACT and JTAG:
>
> > >    A1. Provide an ordered list of devices in the JTAG chain
> > >    A2. Note the cable speed (MHz), and try running the system at the
> > > slowest cable speed possible
> > >    A3. Collect the _impact.log in your project directory after
> > > performing the failing operation
> > >    A4. Read the Status Register after failing operations on an FPGA
> > >    A5. Use the latest version of the software available from the
> > > Download Center
>
> > > Configuration via PROM:
>
> > >    B1. What is the status of INIT and DONE
> > >    B2. What configuration mode is being used
> > >    B3. Will source files work via iMPACT
> > >    B4. After the failed configuration attempt, read the Status
> > > Register of the FPGA via iMPACT
> > >    B5. Get scope shots of power supplies and control pins during
> > > configuration, if possible
>
> > > ------------------------------------------------------------------------
>
> > > How do I accomplish A1, A2, A4, B1, B2, B4?
> > > I can't find anything in this package...
> > > Also the system is non-responsive after the CRC error, how can I (B4)
> > > "read the Status Register of the FPGA via iMPACT"
> > > or is there something that still might be responsive after the "lock
> > > up"- Hide quoted text -
>
> > > - Show quoted text -
>
> > you cant scan JTAG chain after CRC error?
>
> > if that so you have major hardware issue, get another board (another
> > type of board!)
>
> > the config prom can cause one time failure of jtag conf, but chain
> > should remain scannable
>
> > Antti
>
> ok yeah, once the crc error happens its dead, I get:
>
> ----------------------------------------------------------------------------------------------------------
> WARNING:iMPACT:2217 - Error shows in the status register, CRC Error
> bit is NOT 0.
> INFO:iMPACT:2219 - Status register values:
> INFO:iMPACT - 1111 1111 1111 1111 1111 1111 1111 1111
> INFO:iMPACT:579 - '1': Completed downloading bit file to device.
> INFO:iMPACT - '1': Checking done pin....done.
> '1': Programmed successfully.
> PROGRESS_END - End Operation.
> Elapsed time =      1 sec.
> Attempting to identify devices in the boundary-scan chain
> configuration...// *** BATCH CMD : Identify
> PROGRESS_START - Starting Operation.
> Identifying chain contents ....done.
> ERROR:iMPACT:585 - A problem may exist in the hardware configuration.
>         Check that the cable, scan chain, and power connections are intact,
>         that the specified scan chain configuration matches the actual
> hardware, and
>          that the power supply is adequate and delivering the correct
> voltage.
> PROGRESS_END - End Operation.
> Elapsed time =      0 sec.
> // *** BATCH CMD : identifyMPM
>
> ----------------------------------------------------------------------------------------------------------------
>
> I have a second board, and it does the same thing, and remember all I
> have to do to generate the problem is to drive pin15, and try and load
> the FPGA thru the jtag header.
>
> If I don't touch a cable, and simply comment out the driving of pin15
> then all is well.
>
> This led me to believe that the problem was with the pin usage,
> however, if I take that same .bit program that drives PIN15 and kills
> the FPGA, make a .MCS burn image out of it, load it into the SP flash
> using the SPI header using the same cables as before, the program runs
> fine, and I am even properly driving PIN15.
>
> So it appears that driving PIN15 is not an issue at all when the
> program loads from the SP flash, and I'm leaning to the conclusion
> that the CRC error is a function of the impact 10.1 having an issue,
> making higgley-piggley out of my program and locking up the FPGA.
>
> Xilinx has no documentation of any of this, and their support, well
> let's just leave it as leaves a lot to be desired.

NOW, I took a look over at Xilinx (god I hate their website) and I
noticed in
the download section:

Update Type: BSDL Models

Device Family: Spartan-3E

File Type: ZIP (384 KB)

Release Date: 05/29/2008

Release Notes:

Spartan-3E BSDL Files
------------------------------------------------------------------------

This is a "Device Models for Boundary Scan operations"
download and has .BSD files in it. Does this have anything that might
solve this issue?


Article: 139977
Subject: Re: Atari VCS 2600 FPGA Cartridge
From: Mike Harrison <mike@whitewing.co.uk>
Date: Tue, 21 Apr 2009 19:01:20 +0100
Links: << >>  << T >>  << A >>
On Tue, 21 Apr 2009 09:22:14 -0700 (PDT), Darcio Prestes <darcioprestes@gmail.com> wrote:

>On Apr 20, 6:20áam, Mike Harrison <m...@whitewing.co.uk> wrote:
>> On Sun, 19 Apr 2009 22:33:00 +0200, Frank Buss <f...@frank-buss.de> wrote:
>> >Darcio Prestes wrote:
>>
>> >> Hey programmable logic seniors! I'm planning to build an Atari VCS
>> >> 2600 game cartridge in order to play with my "brand new" console
>> >> acquired from ebay. I would like to replace the old fashioned 27C
>> >> series EPROM by a programmable device thus cutting board space and
>> >> (main reason) merging the bankswitching logic and rom file in a single
>> >> device. My requirements are 32k x 8 (64k is a plus) of non volatile
>> >> memory and some space to house a couple of FFs and logic gates (simple
>> >> equations). My question is: which manufacturer, family and/or device
>> >> should I look for? Thanks for sharing your valuable experience with my
>> >> hobby project.
>>
>> >Wikipedia says that the VCS 2600 has a 6507 with 1.19 MHz. So if the bus is
>> >not faster, the easiest solution would be just a microcontroller with
>> >sufficient flash storage, like the STM32 series or the LPC21xx series.
>> >Should be fast enough in a small assembler loop to decode an address
>> >requests, read the flash location and change the data pins to output.
>>
>> With ARM MCUs with fast IO like the NXP LPC series, you can use FIQs on the chip select to give very
>> fast response to external signals - I've read data from an image sensor at 4MHz like this in the
>> past.
>> The only problem is that to get enough on-chip RAM you end up paying for a lot of flash you don't
>> need - and external SRAM usually works out cheaper.
>>
>> However a CPLD plus SRAM may end up being the cheapest overall solution.
>
>To Frank:
>It's true. A fast enough uC can do the job of handling bankswitching
>of games that don't use extra hardware like extra RAM. "Weird"
>cartridge emulation has yet to be tested but in theory it's feasible.
>We just need speed. To given RC reset constant we have ~50 ms to set
>the uC up and running. Yes, it should be enough time.
>
>To Nico:
>The 6507 processor used in VCS2600 can address up to 8 kb. The ROM
>(games) is mapped into the higher 4 kb and console's internal RAM and
>peripherals are at lower 4 kb. This is controled by A12 address pin.
>The cartridge just house the ROM chip. All control and timming is done
>by the console itself.
>The LPC family is fine because the address bus can be applied direct
>to its pins due the 5V tolerance. Level translators would be used only
>in data bus. In this case we can use the device suggested by Yann.
>
>To Gregory:
>What we need to consider is the 6507 processor read timming. The
>datasheet in my hands was scanned in low-res and thus hard to read it.
>As far as I can interpret it, we have ~600 ns to put data on bus after
>an address change and keep it valid for ~100 ns.

That should be just about doable on the LPC ARM - the fast IO modes on the NXP parts can make a big
difference, but would carefully crafted assembler FIQ code ( running in RAM for max speed) , and
make good use of dedicated FIQ register bank to minimise context switch. Fortunately ARM is a very
good target for writing assembler, and you can often do a lot in one instruction. 

>To Mike:
>If we decide to use a uC, I would go for a LPC2142 (ARM7 - 64 kb FLASH
>- 16 kb RAM - 60 MHz). At digikey we get micro_controller +
>level_translator + voltage_regulator for ~$ 10.00 USD.

LPC213x is slightly cheaper - only difference is it doesn't have USB. LPC series is 5V tolerant so
may not need level translation. If the input side of the VCS uses TTL levels, then you can probably
get away with driving with 3.3v. CMOS is marginal. 

>Can we get a cheaper CPLD solution?

Probably in chip-count terms, if you can keep it under 72 macrocells the xilinx xc9572 is very cheap
- above this things get more expensive. 
However a MCU will give a lot more flexibility, and doesn't need any special hardware to program -
LPCs can be programmed via the UART with the on-chip bootloader. . 

 

Article: 139978
Subject: Re: ISE 10.1 installation troubles on windows Vista 32bit
From: LittleAlex <alex.louie@email.com>
Date: Tue, 21 Apr 2009 14:22:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 20, 7:32 am, Benjamin Couillard <benjamin.couill...@gmail.com>
wrote:

<snip>

> However, it should still work with Vista Home.
>


"Should" is the operative word.  Obviously, it does not.  I recommend
upgrading to WindowsXP or Linux.

FWIW, there are a large number of programmers in the north west corner
of the USA that run Ubuntu, and have Vista installed as a virtual
machine to authenticate to their corporate network.  None of these
developers use Vista for any function other this authentication.  If
they can't make Vista work, what makes you think that you can?

I have had much success installing modern versions of ISE in Ubuntu
and Fedora.  All I have to do is install "libstdc++5"; that's it.  (I
have NOT had good luck with SUSE.  The X-Server is different enough
that the Xilinx GUI can't talk to it.)

AL

Article: 139979
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: Brian Davis <brimdavis@aol.com>
Date: Tue, 21 Apr 2009 17:24:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
jleslie48 wrote:
>
> So it appears that driving PIN15 is not an issue at all when the
> program loads from the SP flash, and I'm leaning to the conclusion
> that the CRC error is a function of the impact 10.1 having an issue,
> making higgley-piggley out of my program and locking up the FPGA.
>
>Xilinx has no documentation of any of this, and their support, well
>let's just leave it as leaves a lot to be desired.
>

 The conflict between SPI-mode configuration and JTAG configuration
in various Spartan-3's is well known and documented in several places
by Xilinx (see below), as well as being a fairly regular topic here.

 The only workarounds I know of are to either erase the flash
(as Antti suggested), disconnect/disable the flash, or to set
the configuration mode on the chip to JTAG when programming
the FPGA directly.

After a quick look at the Drigmorn1 board schematic, it does not
appear that the configuration mode can be changed, as the mode pins
are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download
method is probably your best bet if you want to program the FPGA
directly without loading up the SPI flash.

Brian

Xilinx Documentation:

XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flash
http://www.xilinx.com/support/documentation/application_notes/xapp951.pdf
figure3, footnote 6 :
"
" 6. For dual configuration mode usage, it is recommended to have the
" option to hold the M2 signal High for JTAG configuration mode.
"

Answer Records:

http://www.xilinx.com/support/answers/9013.htm
http://www.xilinx.com/support/answers/22142.htm
http://www.xilinx.com/support/answers/22255.htm
http://www.xilinx.com/support/answers/16829.htm



Article: 139980
Subject: Re: source for Spartan 3E chips
From: rayzengyan@gmail.com
Date: Tue, 21 Apr 2009 19:26:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 19, 5:52=A0am, Alex Freed <alex_n...@mirrow.com> wrote:
> All,
>
> I need 30 to 50 XC3S250E chips. The obvious source is
> DigiKey but they only have quantity one price.
> Is there a better place to buy?
>
> -Alex.

Which part do you want exactly? XC3S250E-4PQG208C XC3S250E-4FTG256C
OR  XC3S250E-4VQG100C ?

Ray

Article: 139981
Subject: Re: ISE 10.1 installation troubles on windows Vista 32bit
From: Bert_Paris <do_not_spam@me.com>
Date: Wed, 22 Apr 2009 08:50:00 +0200
Links: << >>  << T >>  << A >>
LittleAlex avait ÚnoncÚ :
> On Apr 20, 7:32 am, Benjamin Couillard <benjamin.couill...@gmail.com>
> wrote:
>
> <snip>
>
>> However, it should still work with Vista Home.
>> 
>
>
> "Should" is the operative word.  Obviously, it does not.  I recommend
> upgrading to WindowsXP or Linux.

What you say isn't going to be of much help for the OP.
And "downgrading" to XP isn't an option with the OP's version of Vista.
You don't reformat your computer and change your OS because of one 
application that should work (according to the provider) and doesn't. 
Otherwise, I guess all ISE users would spend their time installing 
Operating Systems instead of designing FPGAs.

>
> FWIW, there are a large number of programmers in the north west corner
> of the USA that run Ubuntu, and have Vista installed as a virtual
> machine to authenticate to their corporate network.  None of these
> developers use Vista for any function other this authentication.

FWIW, people from all over the world run Ubuntu. We use Xubuntu for our 
training room.

> If they can't make Vista work, what makes you think that you can?

Probably because Xilinx says it works, and because it is second in the 
list of supported OS ?
http://www.xilinx.com/ise/logic_design_prod/foundation.htm

> I have had much success installing modern versions of ISE in Ubuntu
> and Fedora.  All I have to do is install "libstdc++5"; that's it.  (I
> have NOT had good luck with SUSE.  The X-Server is different enough
> that the Xilinx GUI can't talk to it.)

We use Ubuntu (& XP) and not SUSE, but your statement is surprising 
since Xilinx officially supports SUSE Linux Enterprise 10 (32 & 64 
bits), and does not officially support Ubuntu ! :-)

My 0.01$

Bert



Article: 139982
Subject: Re: source for Spartan 3E chips
From: Alex Freed <alex_news@mirrow.com>
Date: Wed, 22 Apr 2009 01:22:28 -0700
Links: << >>  << T >>  << A >>
rayzengyan@gmail.com wrote:
>> I need 30 to 50 XC3S250E chips. The obvious source is
>> DigiKey but they only have quantity one price.
>> Is there a better place to buy?
>>
> 
> Which part do you want exactly? XC3S250E-4PQG208C XC3S250E-4FTG256C
> OR  XC3S250E-4VQG100C ?
> 

I need XC3S250E-PQG208

-Alex.


Article: 139983
Subject: ISE 11.1 still no MP support :(
From: luudee <rudolf.usselmann@gmail.com>
Date: Wed, 22 Apr 2009 01:35:30 -0700 (PDT)
Links: << >>  << T >>  << A >>

ISE 11.1 still no MP support :(

Just installed and run ISE 11.1. To my disappointment, there
is still no MP Support, and compile time are equivalent to 10.x.x ...

Anybody knows if Xilinx will ever add MP support ?

But the gui is a bit nicer ....

Cheers,
rudi

Article: 139984
Subject: problem with high speed data transfer
From: 'use_real_email'
Date: Wed, 22 Apr 2009 04:31:36 -0700
Links: << >>  << T >>  << A >>

I'm trying to work on communication between two board A and B equiped
with FPGA,440 bits data must be transfered from A to B in 3 us,
there are three lines for communication.In addition,there are 8 A
boards must communicated with B simutaneously, I use DS coding to
transmit,
which works at 200MHZ for communication of one A and B,but when it
comes to communication of  8 A and B,it doesn't work even at
100MHZ,probably 
it's because crosstalk.I don't know how to solve this problem?Anybody
has solution?Perhaps I can change the way of communication,but what else

communication protocol can I use? I don't have many experiences about
design of FPGA,can anybody help me to work this problem out,any
suggestion
is appreciated.
PS,board A contains virtex2,board B contains virtex4,so SERDES is not
suitable here.
board A has only virtex2,nothing else processor.
board B has only virtex4,nothing else processor.


-- 
mingyuexin
------------------------------------------------------------------------
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View this thread: http://www.fpgacentral.com/group/showthread.php?t=89596


Article: 139985
Subject: Re: problem with high speed data transfer
From: gabor <gabor@alacron.com>
Date: Wed, 22 Apr 2009 12:11:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 22, 7:31=A0am, 'use_real_email' wrote:
> I'm trying to work on communication between two board A and B equiped
> with FPGA,440 bits data must be transfered from A to B in 3 us,
> there are three lines for communication.In addition,there are 8 A
> boards must communicated with B simutaneously, I use DS coding to
> transmit,
> which works at 200MHZ for communication of one A and B,but when it
> comes to communication of =A08 A and B,it doesn't work even at
> 100MHZ,probably
> it's because crosstalk.I don't know how to solve this problem?Anybody
> has solution?Perhaps I can change the way of communication,but what else
>
> communication protocol can I use? I don't have many experiences about
> design of FPGA,can anybody help me to work this problem out,any
> suggestion
> is appreciated.
> PS,board A contains virtex2,board B contains virtex4,so SERDES is not
> suitable here.
> board A has only virtex2,nothing else processor.
> board B has only virtex4,nothing else processor.
>
> --
> mingyuexin
> ------------------------------------------------------------------------
> mingyuexin's Profile:http://www.fpgacentral.com/group/member.php?userid=
=3D72
> View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D8959=
6

What about data from B to A?  is the communication bidirectional?
If not can you use LVDS for the interconnect?  If Virtex2 is the
source, you can use DDR flops to drive the interface.  At the Virtex4
end you can use ISERDES if you want, but 200 Mbps shouldn't require
it.

What makes you think the problem is crosstalk?  Do you have adequate
grounding on the cables?  Are you using DCI or series resistors at the
driver to reduce overshoot?  Can ou get a single link to work
reliably?

Sorry I have more questions than answers,
Gabor

Article: 139986
Subject: Re: source for Spartan 3E chips
From: gabor <gabor@alacron.com>
Date: Wed, 22 Apr 2009 12:14:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 22, 4:22=A0am, Alex Freed <alex_n...@mirrow.com> wrote:
> rayzeng...@gmail.com wrote:
> >> I need 30 to 50 XC3S250E chips. The obvious source is
> >> DigiKey but they only have quantity one price.
> >> Is there a better place to buy?
>
> > Which part do you want exactly? XC3S250E-4PQG208C XC3S250E-4FTG256C
> > OR =A0XC3S250E-4VQG100C ?
>
> I need XC3S250E-PQG208
>
> -Alex.

At least in the U.S., you can generally get the best price
at one of the major franchised distributors like Avnet.  If
you "register" your design with a distributor they can offer
a better price because Xilinx gives them a better price break
for the "design win".  We use Avnet and get much better pricing
than that listed on their website.

Regards,
Gabor

Article: 139987
Subject: Re: ISE 11.1 still no MP support :(
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 22 Apr 2009 19:24:35 GMT
Links: << >>  << T >>  << A >>
On Wed, 22 Apr 2009 01:35:30 -0700, luudee wrote:

> ISE 11.1 still no MP support :(
> 
> Just installed and run ISE 11.1. To my disappointment, there is still no
> MP Support, and compile time are equivalent to 10.x.x ...
> 
> Anybody knows if Xilinx will ever add MP support ?
> 
> But the gui is a bit nicer ....
> 
> Cheers,
> rudi

The -m switch has been in par for years.

Article: 139988
Subject: Re: ISE 11.1 still no MP support :(
From: rickman <gnuarm@gmail.com>
Date: Wed, 22 Apr 2009 13:03:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 22, 3:24=A0pm, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:
> On Wed, 22 Apr 2009 01:35:30 -0700, luudee wrote:
> > ISE 11.1 still no MP support :(
>
> > Just installed and run ISE 11.1. To my disappointment, there is still n=
o
> > MP Support, and compile time are equivalent to 10.x.x ...
>
> > Anybody knows if Xilinx will ever add MP support ?
>
> > But the gui is a bit nicer ....
>
> > Cheers,
> > rudi
>
> The -m switch has been in par for years.

I'll bite, what's MP?

Rick

Article: 139989
Subject: Re: ISE 11.1 still no MP support :(
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 22 Apr 2009 20:07:45 GMT
Links: << >>  << T >>  << A >>
On Wed, 22 Apr 2009 13:03:06 -0700, rickman wrote:

> On Apr 22, 3:24 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote:
>> On Wed, 22 Apr 2009 01:35:30 -0700, luudee wrote:
>> > ISE 11.1 still no MP support :(
>>
>> > Just installed and run ISE 11.1. To my disappointment, there is still
>> > no MP Support, and compile time are equivalent to 10.x.x ...
>>
>> > Anybody knows if Xilinx will ever add MP support ?
>>
>> > But the gui is a bit nicer ....
>>
>> > Cheers,
>> > rudi
>>
>> The -m switch has been in par for years.
> 
> I'll bite, what's MP?
> 
> Rick

par -h virtex5

-m =  Multi task par run. File <node list file> ",
         contains a list of node names on which to run the jobs.
         (This option is available for supported SOLARIS and LINUX operating
          systems only).

Article: 139990
Subject: Differences in PAR results when running standalone vs. from ISE
From: "MM" <mbmsv@yahoo.com>
Date: Wed, 22 Apr 2009 16:32:04 -0400
Links: << >>  << T >>  << A >>
I've noticed that I can't reproduce PAR results that I got running MPPR when 
running PAR from under GUI with exactly the same settings. The only 
difference seems to be the notorious -ise switch. Can someone shed some 
light on whether it is possible at all? Basically the idea is that I find a 
cost table value by running MPPR standalone, then I plug the same value in 
the GUI, make sure that all other settings are the same as during MPPR and 
hope to see the same result, but it doesn't work that way for some reason. 
This is all in ISE8.2.03i. Please don't ask me why I am using GUI at all!

Thanks,
/Mikhail



Article: 139991
Subject: MIG DDR2 controller functional model available
From: jprovidenza@yahoo.com
Date: Wed, 22 Apr 2009 14:27:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
For faster simulations of my design, I developed a Verilog functional
model of
the Xilinx MIG DDR2 memory controller user application interface.
Since
it is intended to for testing "user" logic, it does not implement a
real controller
(the DDR2 pins don't wiggle).  Instead, the model uses an internal
sparse memory array
to store data instead of using an actual (slow) DDR2 memory model.
Rows of memory
are allocated as needed up to a maximum number of rows set by an
internal parameter.

Peek & Poke are also implemented to allow preloading or verifying
memory by a testbed.

I have not thoroughly tested the model yet, but it is passing my basic
tests.

You can access the model at
         http://probo.com/mig_ddr2_bfm.php

Hopefully, the code is well enough commented to get you going!

Comments & feedback are welcome.

John Providenza

Article: 139992
Subject: Re: MIG DDR2 controller functional model available
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 22 Apr 2009 14:41:56 -0700
Links: << >>  << T >>  << A >>
jprovidenza@yahoo.com wrote:

> Hopefully, the code is well enough commented to get you going!

Thanks for the example.

> Comments & feedback are welcome.

64 Wed Apr 22 > vlog mig_ddr2_model.v

Model Technology ModelSim SE vlog 6.2a Compiler 2006.06 Jun 16 2006
-- Compiling module mig_ddr2_model
** Error: mig_ddr2_model.v(711): Task call in function is illegal.


     -- Mike Treseler

Article: 139993
Subject: Re: MIG DDR2 controller functional model available
From: jprovidenza@yahoo.com
Date: Wed, 22 Apr 2009 14:47:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 22, 2:41=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> jprovide...@yahoo.com wrote:
> > Hopefully, the code is well enough commented to get you going!
>
> Thanks for the example.
>
> > Comments & feedback are welcome.
>
> 64 Wed Apr 22 > vlog mig_ddr2_model.v
>
> Model Technology ModelSim SE vlog 6.2a Compiler 2006.06 Jun 16 2006
> -- Compiling module mig_ddr2_model
> ** Error: mig_ddr2_model.v(711): Task call in function is illegal.
>
> =A0 =A0 =A0-- Mike Treseler

Mike -

You're correct - my simulator let the task within a function compile.
I'll update the code
on our web site in a bit.

John P

Article: 139994
Subject: Re: MIG DDR2 controller functional model available
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 22 Apr 2009 16:34:56 -0700
Links: << >>  << T >>  << A >>
jprovidenza@yahoo.com wrote:

> Mike -
> 
> You're correct - my simulator let the task within a function compile.
> I'll update the code
> on our web site in a bit.


Compiles OK now on modelsim.

         -- Mike Treseler

Article: 139995
Subject: Re: ISE 10.1 installation troubles on windows Vista 32bit
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 23 Apr 2009 00:44:25 +0100
Links: << >>  << T >>  << A >>
On Wed, 22 Apr 2009 08:50:00 +0200, Bert_Paris <do_not_spam@me.com> wrote:

>LittleAlex avait ÚnoncÚ :
>> On Apr 20, 7:32 am, Benjamin Couillard <benjamin.couill...@gmail.com>

>
>> I have had much success installing modern versions of ISE in Ubuntu
>> and Fedora.  All I have to do is install "libstdc++5"; that's it.  (I
>> have NOT had good luck with SUSE.  The X-Server is different enough
>> that the Xilinx GUI can't talk to it.)
>
>We use Ubuntu (& XP) and not SUSE, but your statement is surprising 
>since Xilinx officially supports SUSE Linux Enterprise 10 (32 & 64 
>bits), and does not officially support Ubuntu ! :-)

And I've not had any real trouble* with OpenSuse 11 which isn't supported
either.

Is there a pattern emerging here? :-)

(* other than having to do odd things with the DISPLAY  variable and having to
install one libXm.so library from the Suse repository)

What sold me on Suse11 was the OS installation process offered to install 32-bit
compat libraries for the 64-bit OS. These work well enough that I could happily
run Webpack on 64 bit, which is DEFINITELY not supported (I just modified the OS
test in the Webpack setup.sh script so it reported 64 bit as unsupported but
went on to install anyway) 

There are presumably compat libs for Ubuntu et al, but this was the first time
I'd seen them as an install time option. Sometimes it's the little things that
make one distro feel right and work smoothly.

- Brian

Article: 139996
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: jleslie48 <jon@jonathanleslie.com>
Date: Wed, 22 Apr 2009 17:22:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote:
> jleslie48 wrote:
>
> > So it appears that driving PIN15 is not an issue at all when the
> > program loads from the SP flash, and I'm leaning to the conclusion
> > that the CRC error is a function of the impact 10.1 having an issue,
> > making higgley-piggley out of my program and locking up the FPGA.
>
> >Xilinx has no documentation of any of this, and their support, well
> >let's just leave it as leaves a lot to be desired.
>
>  The conflict between SPI-mode configuration and JTAG configuration
> in various Spartan-3's is well known and documented in several places
> by Xilinx (see below), as well as being a fairly regular topic here.
>
>  The only workarounds I know of are to either erase the flash
> (as Antti suggested), disconnect/disable the flash, or to set
> the configuration mode on the chip to JTAG when programming
> the FPGA directly.
>
> After a quick look at the Drigmorn1 board schematic, it does not
> appear that the configuration mode can be changed, as the mode pins
> are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download
> method is probably your best bet if you want to program the FPGA
> directly without loading up the SPI flash.
>
> Brian
>
> Xilinx Documentation:
>
> XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://www.xilinx.com/support/documentation/application_notes/xapp951...
> figure3, footnote 6 :
> "
> " 6. For dual configuration mode usage, it is recommended to have the
> " option to hold the M2 signal High for JTAG configuration mode.
> "
>
> Answer Records:
>
> http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/support/answers/22142.htmhttp://www.xilinx.com/support/answers/22255.htmhttp://www.xilinx.com/support/answers/16829.htm

Brian,

Thank you very much.  It wasn't untll the end that I connected the
JTAG load problem with my previous SPI load, mostly because after I
loaded the SPI, I successfully changed the code using the JTAG to FPGA
without any issue.  It was only when I added signals to pins did the
error message pop up.

One would think Xilinx would have that listed in the possible causes
of the 2217 error and that a search of Xilinx for "iMpact:2217 crc
error bit not 0" (the actual error message that pops up) would be
acknowledged.

For the amount of money I paid for this development suite and support
I cannot believe the level and frequency of bugs in the software and
lack of support I get from these folks.


Article: 139997
Subject: TODAY, April 27th, says Xilinx
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 23 Apr 2009 00:25:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
ROTFL, now Xilinx is even managed to change the DATE of TODAY!

see here

http://www.xilinx.com/support/documentation/white_papers/wp308.pdf

this document, available today (my PC tell me 23rd April, and I belive
that to be rather accurate as I turned 44 day before yesterday) says:

WP308 (v1.0) April 27, 2009

so is today 23 or 27?

from WP308 I can guess, that ISE 11.1 official release date is
27April!

Way to go, I was expecting Spartan 6 support in June only, but this
time Xilinx is doing something sooner than expected?

hm.. well we have to wait til monday to really see this!

Antti

PS next Antti-Brain will have section for ISE 11.1 and 6/6 FPGA's



Article: 139998
Subject: Re: fpga locks up with slow signal, spartan chip, pin type issues.
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 23 Apr 2009 00:31:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 23, 3:22=A0am, jleslie48 <j...@jonathanleslie.com> wrote:
> On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote:
>
>
>
>
>
> > jleslie48 wrote:
>
> > > So it appears that driving PIN15 is not an issue at all when the
> > > program loads from the SP flash, and I'm leaning to the conclusion
> > > that the CRC error is a function of the impact 10.1 having an issue,
> > > making higgley-piggley out of my program and locking up the FPGA.
>
> > >Xilinx has no documentation of any of this, and their support, well
> > >let's just leave it as leaves a lot to be desired.
>
> > =A0The conflict between SPI-mode configuration and JTAG configuration
> > in various Spartan-3's is well known and documented in several places
> > by Xilinx (see below), as well as being a fairly regular topic here.
>
> > =A0The only workarounds I know of are to either erase the flash
> > (as Antti suggested), disconnect/disable the flash, or to set
> > the configuration mode on the chip to JTAG when programming
> > the FPGA directly.
>
> > After a quick look at the Drigmorn1 board schematic, it does not
> > appear that the configuration mode can be changed, as the mode pins
> > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download
> > method is probably your best bet if you want to program the FPGA
> > directly without loading up the SPI flash.
>
> > Brian
>
> > Xilinx Documentation:
>
> > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://www.x=
ilinx.com/support/documentation/application_notes/xapp951...
> > figure3, footnote 6 :
> > "
> > " 6. For dual configuration mode usage, it is recommended to have the
> > " option to hold the M2 signal High for JTAG configuration mode.
> > "
>
> > Answer Records:
>
> >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/s...
>
> Brian,
>
> Thank you very much. =A0It wasn't untll the end that I connected the
> JTAG load problem with my previous SPI load, mostly because after I
> loaded the SPI, I successfully changed the code using the JTAG to FPGA
> without any issue. =A0It was only when I added signals to pins did the
> error message pop up.
>
> One would think Xilinx would have that listed in the possible causes
> of the 2217 error and that a search of Xilinx for "iMpact:2217 crc
> error bit not 0" (the actual error message that pops up) would be
> acknowledged.
>
> For the amount of money I paid for this development suite and support
> I cannot believe the level and frequency of bugs in the software and
> lack of support I get from these folks.- Hide quoted text -
>
> - Show quoted text -

impact s****
always has...

there are things to KNOW
JTAG configuration mode does OVERRIDE other modes
but it not always works with impact

this may depend 2 bitfiles bit difference you are trying to load
or the speed of the PC, or the type of cable you use..

so while it should be ALWAYS be possible to configure
over jtag without concern of the MODE pins settings
with impact this isnt true

i once designed a workaround that used boundary scan
to place the SPI flash into deep powerdown mode
to allow the configuration to be done properly..

Antti


















Article: 139999
Subject: Re: TODAY, April 27th, says Xilinx
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 23 Apr 2009 01:08:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 23, 10:25=A0am, Antti <Antti.Luk...@googlemail.com> wrote:
> ROTFL, now Xilinx is even managed to change the DATE of TODAY!
>
> see here
>
> http://www.xilinx.com/support/documentation/white_papers/wp308.pdf
>
> this document, available today (my PC tell me 23rd April, and I belive
> that to be rather accurate as I turned 44 day before yesterday) says:
>
> WP308 (v1.0) April 27, 2009
>
> so is today 23 or 27?
>
> from WP308 I can guess, that ISE 11.1 official release date is
> 27April!
>
> Way to go, I was expecting Spartan 6 support in June only, but this
> time Xilinx is doing something sooner than expected?
>
> hm.. well we have to wait til monday to really see this!
>
> Antti
>
> PS next Antti-Brain will have section for ISE 11.1 and 6/6 FPGA's

ohh...

Spartan-Virtex 6 support will be added in ISE 11.2 only

so we need wait the next release, not this one :(





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