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On 20 avr, 13:17, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > > Hi, I've downloaded ISE 10.1 =A0and I'm now trying to install it on my > > PC. Every time I click on setup.exe, the program crashes and I get an > > error message from Windows. > > It would help to tell what the message says. > > -- glen "setup.exe has stopped working" (I translated the message). That's all it says.Article: 139951
> > > Here's the program that drives the LED, and pins 17, 18. This one > > works fine: > > >http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... > > > and heres the one where all I did was add PIN15_LED, but it locks up > > the FPGA: > > >http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... > Just a hunch. Spartan 3E has some pins that are input only. I recall hitting this some time ago. The tools wouldn't give a warning. I may be completely wrong, but I think my problem was when using a GCLK as output. JosepArticle: 139952
On Apr 18, 2:26=A0pm, mooo <randomname...@gmail.com> wrote: > I don't know, this is my third verilog program and I'm just tooling > around on my lonesome in my spare time. =A0I was googling around trying > to figure out how to convert a binary number to an ASCII string and > that's what I came up with. =A0How does one tell whether or not > something is synthesizeable? =A0I tried looking up what is or isn't > supported but wasn't able to find any such document. > > > what do you think XST should synthesize for $sformat ???? > > > and where did you see synthesizeable samples with $sformat ??? Figuring out what is synthesizable is actually pretty easy. Any book or even the tool vendor's help file will show you samples of code to generate registers or basic logic. If you stick with those styles, your code should always be synthesizable. So rather than to "code" your problem in an HDL, try "designing" your hardware to solve the problem and then use the code templates to "describe" your hardware. Otherwise it would be HCL (hardware coding language). RickArticle: 139953
gabor wrote: <snip> Well... you're right. I'm too architecturally biased... > The normal procedure is > to instantiate a short shift register with an initial > value of all 1's (or all 0's for active low logic) and > then shifting in 0's when the chip starts up. The output > of the shift register will therefore start up the > rest of the chip a few clocks after configuration > is complete without the need for an external reset > signal. Funny... Long ago, I was in a digital design class in a university. The teacher was (is ?) a "all state-machine"-guy. On the first day of the class, he asked the class how to design a circuit that would receive a serial bitstream and toggle a bit when it's finished. I started to describe a system similar to what you just wrote, and he almost had a fit (well, he was blunt and dismissive). He went on to describe "his perfect way of doing this" with high-level stuffs and (for me) some bloat. For him, "one hot" systems are evil... I presume that his bias for state machine could come from his extensive use of PALs (22V10 and the likes) and I was already well into the FPGA and full-custom world... Sea-of-gates have (to me) different constraints. Anyway, I don't remember a case where I had to use a "state machine formalism". And I try to avoid these cases anyway because it relies too much on the tools ... I've already worked with FSM crunching software but a nice little clean design looks much better to me :-/ (oops now I realise that it could start a flamewar) > Regards, > Gabor yg -- http://ygdes.com / http://yasep.orgArticle: 139954
Looking at this report, it says you are using a CP132 chip scale, BGA package, but your pin numbers in the comments are not BGA type numbers. Where did you get the pin numbers 1....N? The way you are listing them it looks more like a connector. What are the pin numbers on the FPGA? Is there any circuitry on the card between the FPGA and the connector? Or am I all wrong about this being a connector? Rick On Apr 17, 10:55 am, jleslie48 <j...@jonathanleslie.com> wrote: > here's the pinout of a board I'm using: > > # chipset: > # xc3s500e-4cp132 > # > # 3s500E > # xxxxx-xxxx > # korea > # C6-DGQ 4C > # > # apparently the c6 defines the packages as CPG132 as per > # xilinx document ds312.pdf > > # 1 --|DGND 5V IN |-- 40 > # 2 --|DGND DGND |-- 39 > # 3 --|PIN3 dual PIN38 |-- 38 dual/gclk > # 4 --|PIN4 dual PIN37 |-- 37 dual > # 5 --|PIN5 rhclk/dual PIN36 |-- 36 I/O > # 6 --|PIN6 rhclk/dual PIN35 |-- 35 dual/gclk > # 7 --|PIN7 rhclk/dual PIN34 |-- 34 lhclk > # 8 --|PIN8 rhclk/dual PIN33 |-- 33 lhclk > # 9 --|PIN9 rhclk/dual PIN32 |-- 32 I/O > # 10 --|PIN10 I/0 PIN31 |-- 31 lhclk > # 11 --|PIN11 dual PIN30 |-- 30 I/O > # 12 --|PIN12 dual PIN29 |-- 29 lhclk > # 13 --|PIN13 lhclk PIN28 |-- 28 lhclk > # 14 --|PIN14 rhclk/dual PIN27 |-- 27 I/O > # 15 --|PIN15 dual PIN26 |-- 26 I/O > # 16 --|PIN16 gclk PIN25 |-- 25 I/O > # 17 --|PIN17 gclk PIN24 |-- 24 vref > # 18 --|PIN18 lhclk PIN23 |-- 23 I/O > # 19 --|DGND DGND |-- 22 > # 20 --|DGND DGND |-- 21 > > I checked against the Xilinx documentation for the type associated > with the pins so I mapped them out using xilinx ds312.pdf and came up > with this type configuration for CP132 Ball. > > It seems what I put out on the output pins is relevant. Pin15 has a > 1/4 second blink code, while pins 17 and 18 have a 2mhz signal going > out and all is OK. > If I swap pins 15 and 18, I lock up. IF I drive Pin 13 with the > 2mhz signal, no problem also. > > Simply put, if I drive PIN13 or PIN18 (the lhclk types) at 2mhz, no > problem, but if I drive them at 4hz, they lock up the fpga. > > Any insight or suggested reading/ places to look in the multitude of > summary reports that ISE generates? I found it strange that nothing > strange appears in the build process or in testbench, but when I > download the program, the FPGA locks up and only a power down and up > resets it.Article: 139955
On Apr 20, 3:37 pm, djj08230 <djj08...@gmail.com> wrote: > > > Here's the program that drives the LED, and pins 17, 18. This one > > > works fine: > > > >http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... > > > > and heres the one where all I did was add PIN15_LED, but it locks up > > > the FPGA: > > > >http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screen... > > Just a hunch. Spartan 3E has some pins that are input only. I recall > hitting this some time ago. The tools wouldn't give a warning. I may > be completely wrong, but I think my problem was when using a GCLK as > output. > > Josep yeah, you're the second person to tell me that, meantime the one of the few pins (17) that IS working correctly is a GCLK... good thought though.Article: 139956
On Mar 30, 8:51=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Mar 31, 3:05=A0am, alonzo <rh...@yahoo.com> wrote: > > > > > On Mar 30, 4:44=A0pm, LittleAlex <alex.lo...@email.com> wrote: > > > > On Mar 30, 4:42 pm, alonzo <rh...@yahoo.com> wrote: > > > > > Hi all, > > > > Is there a way to initialize BRAM contents (of memories created usi= ng > > > > CoreGen) into a new bit file without having to recompile the whole > > > > thing? I understand that was possible using data2mem with older > > > > versions, e.g ISE 8.2. AR#18637 says it doesn't work for newer > > > > versions. Does somebody know a work around? > > > > Alonzo. > > > > There are tools installed with the EDK that do that. > > > > AL > > > Yes. I know about bitinit. But it is not transparent. It works with > > cores that EDK provides and requires a MHS file. My project is a > > simple ISE project that instantiate a couple BRAMs. I don't think it > > would help. Do you know about any other tool? > > alnz. > > Xilinx AR's are really ROTFL stuff, from the AR you referred > > Note: Using data2mem on CORE Generator memories in 9.1i or later works > only sporadically. > > So Xilinx 9.1 and later are now "Sporadic software" ! > > ok, but that only relaced to coregen, and you have no need to used > coregen > > just use the brams in ISE create a BMM file and use data2mem > it defenetly works in 10.1 too > > http://www.xilinx.com/itp/xilinx10/books/docs/d2m/d2m.pdf > > make BMM, use MEM file and all works :) > Antti Seems to work. Thank you. alnz.Article: 139957
On Apr 20, 4:13 pm, rickman <gnu...@gmail.com> wrote: the report I listed is from the ucf file that came with the card. Here is the entire ucf file: ----------------------------------------------- # 090403 JL first usage of the drigmorn1 card. # functionality from the raggedstone1 is pulled over here and # used in the drogmorn1. # chipset: # xc3s500e-4cp132 # # 3s500E # xxxxx-xxxx # korea # C6-DGQ 4C # # apparently the c6 defines the packages as CPG132 as per # xilinx document ds312.pdf # # 090403 JL ok, commented out everything, and then put back what I wanted, renaming # as I went along. pins 11, 12 for input buttons, 17, 18 for bae signal, # and the rs232 port for the Huart. # # #DRIGMORN PACKAGE IS CP132/CPG132 # ##################################### #CLOCK ##################################### #--NET "CLOCK_40MHZ" LOC = "M6"; NET "system_clock" LOC = "M6"; ##################################### #RS232 PINS ##################################### #--NET "RTS" LOC = "A9"; #OUTPUT FROM RS232 CHIP #--NET "TXD" LOC = "B9"; #OUTPUT FROM RS232 CHIP NET "Huart_tx_line" LOC = "B9"; #OUTPUT FROM RS232 CHIP #--NET "CTS" LOC = "M12" | PULLUP; #INPUT FROM RS232 CHIP #--NET "RXD" LOC = "A7" | PULLUP; #INPUT FROM RS232 CHIP NET "Huart_rx_line" LOC = "A7" | PULLUP; #INPUT FROM RS232 CHIP ##################################### #LED PINS ##################################### #--NET "LED1" LOC = "C14"; #'1' = ON NET "led_2" LOC = "C14"; #'1' = ON #--NET "LED2_N" LOC = "P6"; #'0' = ON NET "LED_3" LOC = "P6"; #'0' = ON #--NET "LED3_N" LOC = "P7"; #'0' = ON NET "led_4" LOC = "P7"; #'0' = ON ##################################### #MODULE I/O PINOUT ##################################### # # --------- # | RS232 | # -------------------------- # 1 --|DGND 5V IN |-- 40 # 2 --|DGND DGND |-- 39 # 3 --|PIN3 dual PIN38 |-- 38 dual/gclk # 4 --|PIN4 dual PIN37 |-- 37 dual # 5 --|PIN5 rhclk/dual PIN36 |-- 36 I/O # 6 --|PIN6 rhclk/dual PIN35 |-- 35 dual/gclk # 7 --|PIN7 rhclk/dual PIN34 |-- 34 lhclk # 8 --|PIN8 rhclk/dual PIN33 |-- 33 lhclk # 9 --|PIN9 rhclk/dual PIN32 |-- 32 I/O # 10 --|PIN10 I/0 PIN31 |-- 31 lhclk # 11 --|PIN11 dual PIN30 |-- 30 I/O # 12 --|PIN12 dual PIN29 |-- 29 lhclk # 13 --|PIN13 lhclk PIN28 |-- 28 lhclk # 14 --|PIN14 rhclk/dual PIN27 |-- 27 I/O # 15 --|PIN15 I/O PIN26 |-- 26 I/O # 16 --|PIN16 gclk PIN25 |-- 25 I/O # 17 --|PIN17 gclk PIN24 |-- 24 vref # 18 --|PIN18 lhclk PIN23 |-- 23 I/O # 19 --|DGND DGND |-- 22 # 20 --|DGND DGND |-- 21 # ---------------------------- # | 5V | # | IN | # ------ ##################################### #LHS PINS FROM TOP ##################################### #PIN1 = DGND #PIN2 = DGND #--NET "PIN3" LOC = "L14"; #"FPGA_IO27" #--NET "PIN4" LOC = "N14"; #"FPGA_IO25" #--NET "PIN5" LOC = "H12"; #"FPGA_IO24" #--NET "PIN6" LOC = "J12"; #"FPGA_IO23" #--NET "PIN7" LOC = "G13"; #"FPGA_IO20" #--NET "PIN8" LOC = "J14"; #"FPGA_IO21" #--NET "PIN9" LOC = "K14"; #"FPGA_IO22" #--NET "PIN10" LOC = "C12"; #"FPGA_IO16" #--NET "PIN11" LOC = "F12"; #"FPGA_IO17" NET "button_1" LOC = "F12" | PULLUP ; #"FPGA_IO17" #--NET "PIN12" LOC = "F14"; #"FPGA_IO18" NET "button_2" LOC = "F14" | PULLUP ; #"FPGA_IO18" #--NET "PIN13" LOC = "F2"; #"FPGA_IO19" #--NET "PIN14" LOC = "G14"; #"FPGA_IO15" #--NET "PIN15" LOC = "A13"; #"FPGA_IO14" #--NET "PIN15_led" LOC = "A13"; #"FPGA_IO14" #--NET "PIN16" LOC = "A10"; #"FPGA_IO13" #--NET "PIN17" LOC = "C9"; #"FPGA_IO12" NET "a2mhz_huart_tx_line" LOC = "C9"; #"FPGA_IO12" #--NET "PIN18" LOC = "G3"; #"FPGA_IO11" NET "a2mhz_huart_ck_line" LOC = "g3"; #"FPGA_IO11" #PIN19 = DGND #PIN20 = DGND ##################################### #RHS PINS FROM TOP ##################################### #PIN40 = 5V #PIN39 = DGND #--NET "PIN38" LOC = "M5"; #"FPGA_IO32" #--NET "PIN37" LOC = "P4"; #"FPGA_IO33" #--NET "PIN36" LOC = "L3"; #"FPGA_IO26" #--NET "PIN35" LOC = "M4"; #"FPGA_IO38" #--NET "PIN34" LOC = "F1"; #"FPGA_IO34" #--NET "PIN33" LOC = "H1"; #"FPGA_IO37" #--NET "PIN32" LOC = "J3"; #"FPGA_IO36" #--NET "PIN31" LOC = "H3"; #"FPGA_IO35" #--NET "PIN30" LOC = "A3"; #"FPGA_IO3" #--NET "PIN29" LOC = "F3"; #"FPGA_IO2" #--NET "PIN28" LOC = "G1"; #"FPGA_IO1" #--NET "PIN27" LOC = "B1"; #"FPGA_IO0" #--NET "PIN26" LOC = "C5"; #"FPGA_IO4" #--NET "PIN25" LOC = "C3"; #"FPGA_IO5" #--NET "PIN24" LOC = "C6"; #"FPGA_IO6" #--NET "PIN23" LOC = "B5"; #"FPGA_IO7" #PIN22 = DGND #PIN21 = DGND ------------------------------------------------ > Looking at this report, it says you are using a CP132 chip scale, BGA > package, but your pin numbers in the comments are not BGA type > numbers. Where did you get the pin numbers 1....N? The way you are > listing them it looks more like a connector. What are the pin numbers > on the FPGA? Is there any circuitry on the card between the FPGA and > the connector? Or am I all wrong about this being a connector? > > Rick > > On Apr 17, 10:55 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > here's the pinout of a board I'm using: > > > # chipset: > > # xc3s500e-4cp132 > > # > > # 3s500E > > # xxxxx-xxxx > > # korea > > # C6-DGQ 4C > > # > > # apparently the c6 defines the packages as CPG132 as per > > # xilinx document ds312.pdf > > > # 1 --|DGND 5V IN |-- 40 > > # 2 --|DGND DGND |-- 39 > > # 3 --|PIN3 dual PIN38 |-- 38 dual/gclk > > # 4 --|PIN4 dual PIN37 |-- 37 dual > > # 5 --|PIN5 rhclk/dual PIN36 |-- 36 I/O > > # 6 --|PIN6 rhclk/dual PIN35 |-- 35 dual/gclk > > # 7 --|PIN7 rhclk/dual PIN34 |-- 34 lhclk > > # 8 --|PIN8 rhclk/dual PIN33 |-- 33 lhclk > > # 9 --|PIN9 rhclk/dual PIN32 |-- 32 I/O > > # 10 --|PIN10 I/0 PIN31 |-- 31 lhclk > > # 11 --|PIN11 dual PIN30 |-- 30 I/O > > # 12 --|PIN12 dual PIN29 |-- 29 lhclk > > # 13 --|PIN13 lhclk PIN28 |-- 28 lhclk > > # 14 --|PIN14 rhclk/dual PIN27 |-- 27 I/O > > # 15 --|PIN15 dual PIN26 |-- 26 I/O > > # 16 --|PIN16 gclk PIN25 |-- 25 I/O > > # 17 --|PIN17 gclk PIN24 |-- 24 vref > > # 18 --|PIN18 lhclk PIN23 |-- 23 I/O > > # 19 --|DGND DGND |-- 22 > > # 20 --|DGND DGND |-- 21 > > > I checked against the Xilinx documentation for the type associated > > with the pins so I mapped them out using xilinx ds312.pdf and came up > > with this type configuration for CP132 Ball. > > > It seems what I put out on the output pins is relevant. Pin15 has a > > 1/4 second blink code, while pins 17 and 18 have a 2mhz signal going > > out and all is OK. > > If I swap pins 15 and 18, I lock up. IF I drive Pin 13 with the > > 2mhz signal, no problem also. > > > Simply put, if I drive PIN13 or PIN18 (the lhclk types) at 2mhz, no > > problem, but if I drive them at 4hz, they lock up the fpga. > > > Any insight or suggested reading/ places to look in the multitude of > > summary reports that ISE generates? I found it strange that nothing > > strange appears in the build process or in testbench, but when I > > download the program, the FPGA locks up and only a power down and up > > resets iArticle: 139958
Brian Drummond <brian_drummond@btconnect.com> wrote: > >Nice board. My issue though is : is your oscillator available > >in 11.2896MHz frequency, and at what cost ? > Heh, thought as much. > The other crystal is 12.288MHz then. Curiosity led me to this thread which perhaps might be of interest: http://www.diyaudio.com/forums/showthread/t-25921.html G.Article: 139959
'use_real_email' wrote: > Hello Friends > I am a new techie on FPGA > I am dumping simple programs <4 bit on Xilinx Spartan-3E kit with > xilinx ISE > can any one say me how to dumb a program >4bit on this kit > and please say me why micro biz is used > > Hi Ramesh, could you please re-explain? I do not understand your question. What exactly is less 4 or greater than 4 bit? You seem to have success if something (I didn't understand what) is less then four bit? It seems to fail if it is greater than 4 bits. What is the error message? What happens if you use exactly 4 bits? You talk about programs. Do you talk about picoblaze programs? bye NArticle: 139960
Gavin Scott wrote: > Curiosity led me to this thread which perhaps might be of interest: > http://www.diyaudio.com/forums/showthread/t-25921.html thanks, it's interesting ! > G. yg -- http://ygdes.com / http://yasep.orgArticle: 139961
On Mon, 20 Apr 2009 08:46:14 -0700 (PDT), jleslie48 <jon@jonathanleslie.com> wrote: >It just doesn't make any sense. > >the UCF file differs by one line, I added: > >NET "PIN15_led" LOC = "A13"; #"FPGA_IO14" Total wildcard, since it really doesn't make sense... Reinstate than line (in both source and UCF, but with a different name (like xxx15 for example..). Report whether it behaves any differently. Just occasionally you see odd behaviour from some toolset or other because you have used a name which is not legally a reserved word, but is treated as such by one tool... I wonder if this could be the case here? (I have a very poor opinion of the syntax of UCF files. I would love to see a BNF grammar for it but have a sneaking suspicion it would provoke nothing more useful than blank stares from the support crew... recently spent about half a day fighting constraints where XST appeared to convert half my names to lower case - but leave the rest - and some constraints but not others would be rejected by "Translate" until I capiTalIZed the UCF the way IT wanted...) - BrianArticle: 139962
On Apr 20, 7:49 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 20 Apr 2009 08:46:14 -0700 (PDT), jleslie48 <j...@jonathanleslie.com> > wrote: > > >It just doesn't make any sense. > > >the UCF file differs by one line, I added: > > >NET "PIN15_led" LOC = "A13"; #"FPGA_IO14" > > Total wildcard, since it really doesn't make sense... > Reinstate than line (in both source and UCF, but with a different name (like > xxx15 for example..). Report whether it behaves any differently. > > Just occasionally you see odd behaviour from some toolset or other because you > have used a name which is not legally a reserved word, but is treated as such by > one tool... > > I wonder if this could be the case here? > > (I have a very poor opinion of the syntax of UCF files. I would love to see a > BNF grammar for it but have a sneaking suspicion it would provoke nothing more > useful than blank stares from the support crew... recently spent about half a > day fighting constraints where XST appeared to convert half my names to lower > case - but leave the rest - and some cconstraints but not others would be > rejected by "Translate" until I capiTalIZed the UCF the way IT wanted...) > > - Brian I hear you. That's generally why I put the "_led" on the net line. just to change it. Someone else has also suggested that. I made them all CAPS. but nothing changed. I took the line out of the UCF in the hopes that maybe the pin I was using was inappropriate and by letting the toolset pick the pin it would resolve the issue. It didnt I'm beginning to think that the problem hinges on the CRC error. I think that is the key to the whole issue. I can't imagine any syntax situation causing a CRC error.Article: 139963
On Apr 20, 7:43=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > Please note the WARNING: iMPACT:2217 - Error shows in the status > register, CRC Error bit is NOT 0. > > a subsequent call to 'get device id' yields: > > // *** BATCH CMD : ReadIdcode -p 1 > INFO:iMPACT:583 - '1': The idcode read from the device does not match > the idcode in the bsdl File. > INFO:iMPACT:1578 - '1': =A0Device IDCODE : > 00001111111111111111111111111111 > INFO:iMPACT:1579 - '1': Expected IDCODE: > 00000001110000100010000010010011 > > and a big red 'ReadIDcode failed' block pops up in instead of the nice > blue block saying 'succeeded' This may not be related to your VHDL at all. When using a Spartan3 (not E) I recall experiencing a similar behaviour. Configuration seemed not to be reliable when configuring the FPGA directly and bypassing the serial FLASH. Usually I had to power cycle a few times before being able to succedfully configure the FPGA. I never got an explanation to this behavior, it could be the board I was using, the tools or whatever. In my case programing the serial flash and then rebooting the board got a 100% success. Another point worth checking is the programming cable you are using. I used to get bad results with home made and cheap compatible programmig cables. All problems seemed to dissapear when using official USB Xilinx cable. JosepArticle: 139964
On Apr 21, 10:31=A0am, djj08230 <djj08...@gmail.com> wrote: > On Apr 20, 7:43=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status > > register, CRC Error bit is NOT 0. > > > a subsequent call to 'get device id' yields: > > > // *** BATCH CMD : ReadIdcode -p 1 > > INFO:iMPACT:583 - '1': The idcode read from the device does not match > > the idcode in the bsdl File. > > INFO:iMPACT:1578 - '1': =A0Device IDCODE : > > 00001111111111111111111111111111 > > INFO:iMPACT:1579 - '1': Expected IDCODE: > > 00000001110000100010000010010011 > > > and a big red 'ReadIDcode failed' block pops up in instead of the nice > > blue block saying 'succeeded' > > This may not be related to your VHDL at all. > When using a Spartan3 (not E) I recall experiencing a similar > behaviour. Configuration seemed not to be reliable when configuring > the FPGA directly and bypassing the serial FLASH. > Usually I had to power cycle a few times before being able to > succedfully configure the FPGA. I never got an explanation to this > behavior, it could be the board I was using, the tools or whatever. In > my case programing the serial flash and then rebooting the board got a > 100% success. > Another point worth checking is the programming cable you are using. I > used to get bad results with home made and cheap compatible programmig > cables. All problems seemed to dissapear when using official USB > Xilinx cable. > > Josep- Hide quoted text - > > - Show quoted text - oh, I fogot to mention this YOU MUST ERASE platform flash for reliable JTAG configuration if you dont you may have random errors.. AnttiArticle: 139965
M2000 changed name to.... http://www.aboundlogic.com/ Hans www.ht-lab.comArticle: 139966
hi ! Antti.Lukats@googlemail.com wrote: > On Apr 21, 11:15 am, "HT-Lab" <han...@ht-lab.com> wrote: >> M2000 changed name to.... >> http://www.aboundlogic.com/ it's been a while now... >> Hanswww.ht-lab.com > wau > any more info about the revolution in programmable logic? Frankly, no idea yet... But as a former employee of a M2000-spinoff sold to Mentor Graphics I guess that there are some fun stuff behind this. It's not a garantee for success (hmmmm) but I'll be watching this unfold. I contacted their french office some time ago but they did not provide any info, I'll have to wait for a formal product announcement "later this year" IIRC :-/ > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 139967
On Apr 21, 11:15=A0am, "HT-Lab" <han...@ht-lab.com> wrote: > M2000 changed name to.... > > http://www.aboundlogic.com/ > > Hanswww.ht-lab.com wau any more info about the revolution in programmable logic? AnttiArticle: 139968
Hi Antti, Not much except that their technology is based on the M2000 for which you could get Precision libraries so they might have some silicon soon... Regards, Hans. www.ht-lab.com <Antti.Lukats@googlemail.com> wrote in message news:cc454379-98ee-4855-8597-d4ab8d8e7742@l1g2000yqk.googlegroups.com... On Apr 21, 11:15 am, "HT-Lab" <han...@ht-lab.com> wrote: > M2000 changed name to.... > > http://www.aboundlogic.com/ > > Hanswww.ht-lab.com wau any more info about the revolution in programmable logic? AnttiArticle: 139969
On Apr 18, 12:52=A0pm, mooo <randomname...@gmail.com> wrote: > I have a simple verilog program that increments a 32 bit counter, > converts the number to an ASCII string using $sformat and then pushes > the string to the host machine 1 byte at a time using an FTDI FT245RL. > > Unfortunately Xilinx XST keeps optimizing away the string register > vector. I've tried mucking around with various initialization and > access routines with no success. I can't seem to turn off > optimization, and all of the examples I find online differ very little > from my initialization routines. What am I doing wrong? =A0I'm using ISE > webpack 10.1, latest patches. > > module counter(CK12, TXE_, WR, RD_, LED, USBD); > > =A0 =A0input CK12; > =A0 =A0input TXE_; > =A0 =A0output WR; > =A0 =A0output RD_; > =A0 =A0output [7:0] LED; > =A0 =A0inout [7:0] USBD; > > =A0 =A0reg [31:0] count =3D 0; > > =A0 =A0reg [7:0] k; > =A0 =A0reg wrf =A0=3D 0; > =A0 =A0reg rd =A0 =3D 1; > =A0 =A0reg [7:0] lbyte =3D 8'b00000000; > > =A0 =A0reg td =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D 1; > =A0 =A0parameter MEM_SIZE =A0=3D 88; > =A0 =A0parameter STR_SIZE =A0=3D 11; > =A0 =A0reg [MEM_SIZE - 1:0] str; > =A0 =A0reg [7:0] strpos =3D 8'b00000000; > > =A0 =A0initial > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 for (k =3D 0; k < MEM_SIZE; k =3D k + 1) > =A0 =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0str[k] =A0 =A0=3D 0; > =A0 =A0 =A0 =A0 =A0 end > =A0 =A0 =A0end > > =A0 =A0always @(posedge CK12) > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 if (TXE_ =3D=3D 0 && wrf =3D=3D 1) > =A0 =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0count =A0 =A0=3D count + 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0wrf =A0 =A0 =A0 =A0 =3D 0; > =A0 =A0 =A0 =A0 =A0 end > > =A0 =A0 =A0 =A0 else if (wrf =3D=3D 0) =A0// If we've already lowered the= strobe, > latch the data > =A0 =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(td) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 $sformat(str, "%00000= 00000d\n", count); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 strpos =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 td =A0 =A0 =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0end > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0str =A0 =A0 =A0=3D str << 8; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0wrf =A0 =A0 =A0 =A0 =A0 =A0 =3D 1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0strpos =A0 =A0 =A0 =A0 =A0=3D strpos += 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(strpos =3D=3D STR_SIZE) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0td =A0 =A0 =A0 =A0 =A0 =A0=3D 1; > > =A0 =A0 =A0 =A0 =A0 end > =A0 =A0 =A0end > > =A0 =A0assign RD_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D rd; > =A0 =A0assign WR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D wrf; > =A0 =A0assign USBD =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D str[87:80]; > =A0 =A0assign LED =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D count[31:24= ]; > > endmodule > > Loading device for application Rf_Device from file '3s100e.nph' in > environment /opt/Xilinx/10.1/ISE. WARNING:Xst:1293 - FF/Latch str_0 > has a constant value of 0 in block . This FF/Latch will be trimmed > during the optimization process. > > WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_1 has > a constant value of 0 in block . This FF/Latch will be trimmed during > the optimization process. > > WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch str_2 has > a constant value of 0 in block . This FF/Latch will be trimmed during > the optimization process. Don't forget to use non-blocking assignment (<=3D) rather than direct assignment (=3D) for your registers. See: http://www.asic-world.com/tidbits= /blocking.htmlArticle: 139970
On Apr 21, 3:49 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 21, 10:31 am, djj08230 <djj08...@gmail.com> wrote: > > > > > On Apr 20, 7:43 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status > > > register, CRC Error bit is NOT 0. > > > > a subsequent call to 'get device id' yields: > > > > // *** BATCH CMD : ReadIdcode -p 1 > > > INFO:iMPACT:583 - '1': The idcode read from the device does not match > > > the idcode in the bsdl File. > > > INFO:iMPACT:1578 - '1': Device IDCODE : > > > 00001111111111111111111111111111 > > > INFO:iMPACT:1579 - '1': Expected IDCODE: > > > 00000001110000100010000010010011 > > > > and a big red 'ReadIDcode failed' block pops up in instead of the nice > > > blue block saying 'succeeded' > > > This may not be related to your VHDL at all. > > When using a Spartan3 (not E) I recall experiencing a similar > > behaviour. Configuration seemed not to be reliable when configuring > > the FPGA directly and bypassing the serial FLASH. > > Usually I had to power cycle a few times before being able to > > succedfully configure the FPGA. I never got an explanation to this > > behavior, it could be the board I was using, the tools or whatever. In > > my case programing the serial flash and then rebooting the board got a > > 100% success. > > Another point worth checking is the programming cable you are using. I > > used to get bad results with home made and cheap compatible programmig > > cables. All problems seemed to dissapear when using official USB > > Xilinx cable. > > > Josep- Hide quoted text - > > > - Show quoted text - > > oh, > > I fogot to mention this > > YOU MUST ERASE platform flash for reliable JTAG configuration > > if you dont you may have random errors.. > > Antti Yes, I'm beginning to believe that this an error in the jtag loading procedure and not my code. Xilinx support wants me to try the following: iMPACT and JTAG: A1. Provide an ordered list of devices in the JTAG chain A2. Note the cable speed (MHz), and try running the system at the slowest cable speed possible A3. Collect the _impact.log in your project directory after performing the failing operation A4. Read the Status Register after failing operations on an FPGA A5. Use the latest version of the software available from the Download Center Configuration via PROM: B1. What is the status of INIT and DONE B2. What configuration mode is being used B3. Will source files work via iMPACT B4. After the failed configuration attempt, read the Status Register of the FPGA via iMPACT B5. Get scope shots of power supplies and control pins during configuration, if possible ------------------------------------------------------------------------ How do I accomplish A1, A2, A4, B1, B2, B4? I can't find anything in this package... Also the system is non-responsive after the CRC error, how can I (B4) "read the Status Register of the FPGA via iMPACT" or is there something that still might be responsive after the "lock up"Article: 139971
On Apr 21, 3:29=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On Apr 21, 3:49 am, "Antti.Luk...@googlemail.com" > > > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 21, 10:31 am, djj08230 <djj08...@gmail.com> wrote: > > > > On Apr 20, 7:43 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status > > > > register, CRC Error bit is NOT 0. > > > > > a subsequent call to 'get device id' yields: > > > > > // *** BATCH CMD : ReadIdcode -p 1 > > > > INFO:iMPACT:583 - '1': The idcode read from the device does not mat= ch > > > > the idcode in the bsdl File. > > > > INFO:iMPACT:1578 - '1': =A0Device IDCODE : > > > > 00001111111111111111111111111111 > > > > INFO:iMPACT:1579 - '1': Expected IDCODE: > > > > 00000001110000100010000010010011 > > > > > and a big red 'ReadIDcode failed' block pops up in instead of the n= ice > > > > blue block saying 'succeeded' > > > > This may not be related to your VHDL at all. > > > When using a Spartan3 (not E) I recall experiencing a similar > > > behaviour. Configuration seemed not to be reliable when configuring > > > the FPGA directly and bypassing the serial FLASH. > > > Usually I had to power cycle a few times before being able to > > > succedfully configure the FPGA. I never got an explanation to this > > > behavior, it could be the board I was using, the tools or whatever. I= n > > > my case programing the serial flash and then rebooting the board got = a > > > 100% success. > > > Another point worth checking is the programming cable you are using. = I > > > used to get bad results with home made and cheap compatible programmi= g > > > cables. All problems seemed to dissapear when using official USB > > > Xilinx cable. > > > > Josep- Hide quoted text - > > > > - Show quoted text - > > > oh, > > > I fogot to mention this > > > YOU MUST ERASE platform flash for reliable JTAG configuration > > > if you dont you may have random errors.. > > > Antti > > Yes, I'm beginning to believe that this an error in the jtag loading > procedure and not my code. > > Xilinx support wants me to try the following: > > iMPACT and JTAG: > > =A0 =A0A1. Provide an ordered list of devices in the JTAG chain > =A0 =A0A2. Note the cable speed (MHz), and try running the system at the > slowest cable speed possible > =A0 =A0A3. Collect the _impact.log in your project directory after > performing the failing operation > =A0 =A0A4. Read the Status Register after failing operations on an FPGA > =A0 =A0A5. Use the latest version of the software available from the > Download Center > > Configuration via PROM: > > =A0 =A0B1. What is the status of INIT and DONE > =A0 =A0B2. What configuration mode is being used > =A0 =A0B3. Will source files work via iMPACT > =A0 =A0B4. After the failed configuration attempt, read the Status > Register of the FPGA via iMPACT > =A0 =A0B5. Get scope shots of power supplies and control pins during > configuration, if possible > > ------------------------------------------------------------------------ > > How do I accomplish A1, A2, A4, B1, B2, B4? > I can't find anything in this package... > Also the system is non-responsive after the CRC error, how can I (B4) > "read the Status Register of the FPGA via iMPACT" > or is there something that still might be responsive after the "lock > up"- Hide quoted text - > > - Show quoted text - you cant scan JTAG chain after CRC error? if that so you have major hardware issue, get another board (another type of board!) the config prom can cause one time failure of jtag conf, but chain should remain scannable AnttiArticle: 139972
On Apr 21, 10:08 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 21, 3:29 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On Apr 21, 3:49 am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On Apr 21, 10:31 am, djj08230 <djj08...@gmail.com> wrote: > > > > > On Apr 20, 7:43 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > Please note the WARNING: iMPACT:2217 - Error shows in the status > > > > > register, CRC Error bit is NOT 0. > > > > > > a subsequent call to 'get device id' yields: > > > > > > // *** BATCH CMD : ReadIdcode -p 1 > > > > > INFO:iMPACT:583 - '1': The idcode read from the device does not match > > > > > the idcode in the bsdl File. > > > > > INFO:iMPACT:1578 - '1': Device IDCODE : > > > > > 00001111111111111111111111111111 > > > > > INFO:iMPACT:1579 - '1': Expected IDCODE: > > > > > 00000001110000100010000010010011 > > > > > > and a big red 'ReadIDcode failed' block pops up in instead of the nice > > > > > blue block saying 'succeeded' > > > > > This may not be related to your VHDL at all. > > > > When using a Spartan3 (not E) I recall experiencing a similar > > > > behaviour. Configuration seemed not to be reliable when configuring > > > > the FPGA directly and bypassing the serial FLASH. > > > > Usually I had to power cycle a few times before being able to > > > > succedfully configure the FPGA. I never got an explanation to this > > > > behavior, it could be the board I was using, the tools or whatever. In > > > > my case programing the serial flash and then rebooting the board got a > > > > 100% success. > > > > Another point worth checking is the programming cable you are using. I > > > > used to get bad results with home made and cheap compatible programmig > > > > cables. All problems seemed to dissapear when using official USB > > > > Xilinx cable. > > > > > Josep- Hide quoted text - > > > > > - Show quoted text - > > > > oh, > > > > I fogot to mention this > > > > YOU MUST ERASE platform flash for reliable JTAG configuration > > > > if you dont you may have random errors.. > > > > Antti > > > Yes, I'm beginning to believe that this an error in the jtag loading > > procedure and not my code. > > > Xilinx support wants me to try the following: > > > iMPACT and JTAG: > > > A1. Provide an ordered list of devices in the JTAG chain > > A2. Note the cable speed (MHz), and try running the system at the > > slowest cable speed possible > > A3. Collect the _impact.log in your project directory after > > performing the failing operation > > A4. Read the Status Register after failing operations on an FPGA > > A5. Use the latest version of the software available from the > > Download Center > > > Configuration via PROM: > > > B1. What is the status of INIT and DONE > > B2. What configuration mode is being used > > B3. Will source files work via iMPACT > > B4. After the failed configuration attempt, read the Status > > Register of the FPGA via iMPACT > > B5. Get scope shots of power supplies and control pins during > > configuration, if possible > > > ------------------------------------------------------------------------ > > > How do I accomplish A1, A2, A4, B1, B2, B4? > > I can't find anything in this package... > > Also the system is non-responsive after the CRC error, how can I (B4) > > "read the Status Register of the FPGA via iMPACT" > > or is there something that still might be responsive after the "lock > > up"- Hide quoted text - > > > - Show quoted text - > > you cant scan JTAG chain after CRC error? > > if that so you have major hardware issue, get another board (another > type of board!) > > the config prom can cause one time failure of jtag conf, but chain > should remain scannable > > Antti I certainly can't 'get device id' or 'get device signature/ usercode' I didn't initialize chain. I have eliminated my program from causing any error though. I wrote my program to the SPI FLASH and it starts up fine and PIN15 is not an issue. However now that I did that, the JTAG connection to the is completely non-functional, but does not lock up the FPGA: ------------------------------------------------------------------------ // *** BATCH CMD : setMode -pff // *** BATCH CMD : setMode -pff // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs // *** BATCH CMD : ReadIdcode -p 1 INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111111 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001110000100010000010010011 Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify PROGRESS_START - Starting Operation. Identifying chain contents ....done. ERROR:iMPACT:585 - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. PROGRESS_END - End Operation. Elapsed time = 0 sec. // *** BATCH CMD : identifyMPM Enumerating cables. Please wait. PROGRESS_START - Starting Operation. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver file xusb_xlp.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811. Cable PID = 0008. Max current requested during enumeration is 300 mA. Type = 0x0005. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 2401. File version of C:/Xilinx/10.1/ISE/data/xusb_xp2.hex = 2401. Firmware hex file version = 2401. ======================================================= Found cable - > Type = 0x0005. ESN option: 00001322B47101. ESN = 00001322B47101. ======================================================= Connecting to cable (Usb Port - USB22). Checking cable driver. Driver file xusb_xlp.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 2 sec. Error opening cdb file for reading. // *** BATCH CMD : setCable -port usb21 -baud 3000000 Connecting to cable (Usb Port - USB21). Checking cable driver. Driver file xusb_xlp.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811. Cable PID = 0008. Max current requested during enumeration is 300 mA. Type = 0x0005. Cable Type = 3, Revision = 0. Setting cable speed to 3 MHz. Cable connection established. Firmware version = 2401. File version of C:/Xilinx/10.1/ISE/data/xusb_xp2.hex = 2401. Firmware hex file version = 2401. PLD file version = 200Dh. PLD version = 200Dh. Type = 0x0005. ESN option: 00001322B47101. Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify PROGRESS_START - Starting Operation. Identifying chain contents ....done. ERROR:iMPACT:585 - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. PROGRESS_END - End Operation. Elapsed time = 0 sec. // *** BATCH CMD : identifyMPM -------------------------------------------------------------------- but the SPI port works fine: ------------------------------------------------------------ Connecting to cable (Usb Port - USB21). Checking cable driver. Driver file xusb_xlp.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811. Cable PID = 0008. Max current requested during enumeration is 300 mA. Type = 0x0005. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 2401. File version of C:/Xilinx/10.1/ISE/data/xusb_xp2.hex = 2401. Firmware hex file version = 2401. PLD file version = 200Dh. PLD version = 200Dh. PROGRESS_END - End Operation. Elapsed time = 2 sec. ---------------------------------------------------------------------Article: 139973
On Apr 20, 6:20=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > On Sun, 19 Apr 2009 22:33:00 +0200, Frank Buss <f...@frank-buss.de> wrote= : > >Darcio Prestes wrote: > > >> Hey programmable logic seniors! I'm planning to build an Atari VCS > >> 2600 game cartridge in order to play with my "brand new" console > >> acquired from ebay. I would like to replace the old fashioned 27C > >> series EPROM by a programmable device thus cutting board space and > >> (main reason) merging the bankswitching logic and rom file in a single > >> device. My requirements are 32k x 8 (64k is a plus) of non volatile > >> memory and some space to house a couple of FFs and logic gates (simple > >> equations). My question is: which manufacturer, family and/or device > >> should I look for? Thanks for sharing your valuable experience with my > >> hobby project. > > >Wikipedia says that the VCS 2600 has a 6507 with 1.19 MHz. So if the bus= is > >not faster, the easiest solution would be just a microcontroller with > >sufficient flash storage, like the STM32 series or the LPC21xx series. > >Should be fast enough in a small assembler loop to decode an address > >requests, read the flash location and change the data pins to output. > > With ARM MCUs with fast IO like the NXP LPC series, you can use FIQs on t= he chip select to give very > fast response to external signals - I've read data from an image sensor a= t 4MHz like this in the > past. > The only problem is that to get enough on-chip RAM you end up paying for = a lot of flash you don't > need - and external SRAM usually works out cheaper. > > However a CPLD plus SRAM may end up being the cheapest overall solution. To Frank: It's true. A fast enough uC can do the job of handling bankswitching of games that don't use extra hardware like extra RAM. "Weird" cartridge emulation has yet to be tested but in theory it's feasible. We just need speed. To given RC reset constant we have ~50 ms to set the uC up and running. Yes, it should be enough time. To Nico: The 6507 processor used in VCS2600 can address up to 8 kb. The ROM (games) is mapped into the higher 4 kb and console's internal RAM and peripherals are at lower 4 kb. This is controled by A12 address pin. The cartridge just house the ROM chip. All control and timming is done by the console itself. The LPC family is fine because the address bus can be applied direct to its pins due the 5V tolerance. Level translators would be used only in data bus. In this case we can use the device suggested by Yann. To Gregory: What we need to consider is the 6507 processor read timming. The datasheet in my hands was scanned in low-res and thus hard to read it. As far as I can interpret it, we have ~600 ns to put data on bus after an address change and keep it valid for ~100 ns. To Mike: If we decide to use a uC, I would go for a LPC2142 (ARM7 - 64 kb FLASH - 16 kb RAM - 60 MHz). At digikey we get micro_controller + level_translator + voltage_regulator for ~$ 10.00 USD. Can we get a cheaper CPLD solution?Article: 139974
On Sat, 18 Apr 2009 10:52:09 -0700 (PDT), mooo <randomname650@gmail.com> wrote: >I have a simple verilog program that increments a 32 bit counter, >converts the number to an ASCII string using $sformat and then pushes >the string to the host machine 1 byte at a time using an FTDI FT245RL. > ... > $sformat(str, "%0000000000d\n", count); The xst document XST.PDF lists verilog system task which are supported (page 415 in xst.pdf version 11.1.0) and all others, including $sformat are ignored. This means that you are effectively not assigning to str register after initialization and it's always zero so it's a very good candidate for optimization. There is also a 1364.1 IEEE Standard for Verilog RTL synthesis document which says that all system tasks should be ignored which has the same outcome. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
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