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On Wed, 20 May 2009 00:40:42 +0100 "Andrew Holme" <ah@nospam.co.uk> wrote: > I would like to use a Spartan 3 DCM to divide a clock by 5. I don't > care about skew and would prefer not to connect the CLK_FB. I do > care very much about jitter. I'm actually using the FPGA to output a > pulse-width-modulated signal, so I'm committing a total "no-no" by > using it as an analogue component! > > I've read that the DCM DLL function is actually very clean as far as > phase noise / spectral purity are concerned, as long as the DLL > doesn't keep swapping taps. Does anyone know any sneaky non-standard > tricks that would allow me to have my divide-by-5 with tap-swapping > disabled? I could do the divide with CLBs; but I wonder if the DCM, > with its dedicated routing to the global clock buffers, could > actually be better? > > One caveat: I need the FPGA to be totally static at certain times, to > completely eliminate digital switching noise. Does enabling a DCM > activate any internal free-running oscillators? > > Finally, I must confess that my frequency is below the specified > minimum; but I'm hoping the minimum doesn't apply if I'm only doing > division. Am I in luck? > > TIA > Andrew. > > If you don't care about a 50% duty cycle, you could build a 2 up/3 down divider out of logic that would have very low jitter. Though the usual question applies: are you sure you wouldn't be better served just clock-enabling the logic? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140601
On May 19, 12:38=A0pm, "Naveen" <naveen.thoh...@gmail.com> wrote: > Hi, > > =A0 =A0I'm trying to develop a code for implementation of simple MAC > operation. I have almost finished with it. While doing this, i've used > verilog memory and initialised it with the input i.e. array of integers. > But i've done all these things in design block itself. But i need to give > the inputs from outside the design block either from another module or fr= om > some file. For this purpose i can use $readmemh or $readmemb. But since > this is not synthesizable, i can't proceed in this way. Is there any > alternative? Pls guide me, how can i proceed... Why do you say it is not synthesizable? Which synthesis tools do you use? XST certainly supports initialization with $readmemh if you place it in the same module as the memory definition and within an initial block. Also what device are you targetting? Regards, GaborArticle: 140602
On May 19, 4:40=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > I would like to use a Spartan 3 DCM to divide a clock by 5. =A0I don't ca= re > about skew and would prefer not to connect the CLK_FB. =A0I do care very = much > about jitter. =A0I'm actually using the FPGA to output a pulse-width-modu= lated > signal, so I'm committing a total "no-no" by using it as an analogue > component! > > I've read that the DCM DLL function is actually very clean as far as phas= e > noise / spectral purity are concerned, as long as the DLL doesn't keep > swapping taps. =A0Does anyone know any sneaky non-standard tricks that wo= uld > allow me to have my divide-by-5 with tap-swapping disabled? =A0I could do= the > divide with CLBs; but I wonder if the DCM, with its dedicated routing to = the > global clock buffers, could actually be better? > > One caveat: I need the FPGA to be totally static at certain times, to > completely eliminate digital switching noise. =A0Does enabling a DCM acti= vate > any internal free-running oscillators? > > Finally, I must confess that my frequency is below the specified minimum; > but I'm hoping the minimum doesn't apply if I'm only doing division. =A0A= m I > in luck? > > TIA > Andrew. I suggest you use the highest possible frequency for your pulse-width modulator clock. That gives you best resolution (granularity) and avoids the jitter issue you are (rightfully) concerned about. Peter AlfkeArticle: 140603
LittleAlex wrote: > On May 18, 10:47 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: >> This can be fixed with "lmutil lmremove" command, google for the >> command or read the lmutil help text. > That command works only if you have administrative access on the > license server. > > The situation Glen remembers still exists. This may then depend on flexlm settings. I have been quite succesful in using that command to remote flexlm servers to free licenses, and I don't have any admin access to those servers. I'm just a regular user for those servers. --KimArticle: 140604
LittleAlex <alex.louie@email.com> writes: > On May 18, 10:47 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: >> glen herrmannsfeldt wrote: >> > The one I remember occurs when the program or machine crash with >> > a licence outstanding. There is no release of the license, and it >> > continues to count against the number available. That was some years >> > ago, so maybe it has been fixed by now. >> >> This can be fixed with "lmutil lmremove" command, google for the >> command or read the lmutil help text. >> >> --Kim > > That command works only if you have administrative access on the > license server. > Not in my experience: anyone can download the lmtools and use the lmremove command. I even wrote a wxpython front end to make the arcane syntax a bit easier to deal with - it's in use by several non-admin-type users. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140605
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:0cb28ad3-c345-41dd-ac70-ee9ad001938e@v35g2000pro.googlegroups.com... >I suggest you use the highest possible frequency for your pulse-width >modulator clock. That gives you best resolution (granularity) and >avoids the jitter issue you are (rightfully) concerned about. Hi, Peter. The PWM is a continuous analogue output, generated by an AD9901-style phase detector inside the FPGA. There is no granularity.Article: 140606
Hi in VHDL , i want to assign, say a 32 bit bus to another excpet some bits Example : signal bus_1 : std_logic_vector(31 downto 0); signal bus_2 : std_logic_vector(31 downto 0); signal pin_11 :std_logic; signal pin_22 :std_logic; i want : bus_1(31 downto 23) <= bus_2(31 downto 23); bus_1(22) <= pin_22; bus_1(21 downto 12) <= bus_2(21 downto 12); bus_1(11) <= pin_11; bus_1(10 downto 0) <= bus_2(10 downto 0); uff, is there an easy way to do that ? Best Regards, barme2i.Article: 140607
Hi, Does anybody know if Actel's "Low Cost Programming Stick" included with the IGLOO Icicle kit can be used to program other actel dev boards? Actel's web page reads: "The miniature low-cost programming stick, which comes with the IGLOO Icicle Kit, features all the functionality of the FlashPro3 programmer, in addition to generating a special "activate programming" signal during programming that allows the Icicle evaluation board to switch the VCC value from 1.2 V to 1.5 V automatically during programming." Which would suggest that it maintains the FlashPro3 functionality, but I wonder if it could somehow be limited in what chips can be programmed with it? If it can be used with other devices, then the IGLOO kit is a very good value at a third of the price of the FlashPro3... Thanks, SteveArticle: 140608
barme2i@gmail.com wrote: > Hi > > in VHDL , i want to assign, say a 32 bit bus to another excpet some > bits > > Example : > > signal bus_1 : std_logic_vector(31 downto 0); > signal bus_2 : std_logic_vector(31 downto 0); > signal pin_11 :std_logic; > signal pin_22 :std_logic; > > i want : > bus_1(31 downto 23) <= bus_2(31 downto 23); > bus_1(22) <= pin_22; > bus_1(21 downto 12) <= bus_2(21 downto 12); > bus_1(11) <= pin_11; > bus_1(10 downto 0) <= bus_2(10 downto 0); > > uff, is there an easy way to do that ? Not really. There's a few possibilities to do it "differently", though, maybe one of them suits you better: 1. Put it all in one single statement: bus_1 <= bus_2(31 downto 23) & pin_22 & bus_2(21 downto 12) & pin_11 & bus_2(10 downto 0); 2. Put these statements inside a process (doesn't matter if it's clocked or not): bus_1 <= bus_2; bus_1 <= (22 => pin_22, 11 => pin_11); The latter, as I mentioned, works only inside a process, otherwise you'll get a "multiple drivers" error. Disclaimer: Haven't verfied this, might not work (as expected). :) HTH, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 140609
On May 20, 11:38=A0am, sbatt...@yahoo.co.jp wrote: > Hi, > Does anybody know if Actel's "Low Cost Programming Stick" included > with the IGLOO Icicle kit can be used to program other actel dev > boards? > Actel's web page reads: > "The miniature low-cost programming stick, which comes with the IGLOO > Icicle Kit, features all the functionality of the FlashPro3 > programmer, in addition to generating a special "activate programming" > signal during programming that allows the Icicle evaluation board to > switch the VCC value from 1.2 V to 1.5 V automatically during > programming." > > Which would suggest that it maintains the FlashPro3 functionality, but > I wonder if it could somehow be limited in what chips can be > programmed with it? > > If it can be used with other devices, then the IGLOO kit is a very > good value at a third of the price of the FlashPro3... > > Thanks, > > Steve i think it can but not tested AnttiArticle: 140610
Does anybody know how to disable the CONV_INTEGER warnings in ISIM (11.1)? at 3000290500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. at 3000365500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. ..... Thanks, Hans www.ht-lab.comArticle: 140611
On May 20, 5:42=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On May 20, 11:38=A0am, sbatt...@yahoo.co.jp wrote: > > > > > Hi, > > Does anybody know if Actel's "Low Cost Programming Stick" included > > with the IGLOO Icicle kit can be used to program other actel dev > > boards? > > Actel's web page reads: > > "The miniature low-cost programming stick, which comes with the IGLOO > > Icicle Kit, features all the functionality of the FlashPro3 > > programmer, in addition to generating a special "activate programming" > > signal during programming that allows the Icicle evaluation board to > > switch the VCC value from 1.2 V to 1.5 V automatically during > > programming." > > > Which would suggest that it maintains the FlashPro3 functionality, but > > I wonder if it could somehow be limited in what chips can be > > programmed with it? > > > If it can be used with other devices, then the IGLOO kit is a very > > good value at a third of the price of the FlashPro3... > > > Thanks, > > > Steve > > i think it can but not tested > > Antti Thanks for the quick reply! I dug into the user guide for the IGLOO nano starter kit, and, oddly there is space on the PCB for a separate header for FlashPro3, though somewhere in the manual it is stated that the programming stick is functionally equivalent.. it also says something to the effect of, "only the programming stick included with this kit should be used with this kit, the programming stick from another kit may be electrically equivalent, but still may not work properly." I don't really buy that story, though, I can't imagine them not being the same thing. If anyone has tried it and can vouch one way or the other, though, that would be great.. Cheers! SteveArticle: 140612
On May 20, 12:51=A0pm, sbatt...@yahoo.co.jp wrote: > On May 20, 5:42=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On May 20, 11:38=A0am, sbatt...@yahoo.co.jp wrote: > > > > Hi, > > > Does anybody know if Actel's "Low Cost Programming Stick" included > > > with the IGLOO Icicle kit can be used to program other actel dev > > > boards? > > > Actel's web page reads: > > > "The miniature low-cost programming stick, which comes with the IGLOO > > > Icicle Kit, features all the functionality of the FlashPro3 > > > programmer, in addition to generating a special "activate programming= " > > > signal during programming that allows the Icicle evaluation board to > > > switch the VCC value from 1.2 V to 1.5 V automatically during > > > programming." > > > > Which would suggest that it maintains the FlashPro3 functionality, bu= t > > > I wonder if it could somehow be limited in what chips can be > > > programmed with it? > > > > If it can be used with other devices, then the IGLOO kit is a very > > > good value at a third of the price of the FlashPro3... > > > > Thanks, > > > > Steve > > > i think it can but not tested > > > Antti > > Thanks for the quick reply! > > I dug into the user guide for the IGLOO nano starter kit, and, oddly > there is space on the PCB for a separate header for FlashPro3, though > somewhere in the manual it is stated that the programming stick is > functionally equivalent.. it also says something to the effect of, > "only the programming stick included with this kit should be used with > this kit, the programming stick from another kit may be electrically > equivalent, but still may not work properly." > I don't really buy that story, though, I can't imagine them not being > the same thing. > > If anyone has tried it and can vouch one way or the other, though, > that would be great.. > > Cheers! > > Steve the igloo kit has special feature to change the VCCINT voltage i think this is waht he manual refers too standard programming cable would not do that AnttiArticle: 140613
Hi All, Is there a standard/common way to specify nets as multi cycle path within the RTL ? In a way that it would be recognized by as many synthesis tools as possible ? Is there a standards document out there that addresses synthesis specific statements with RTL ? Thanks, rudiArticle: 140614
On May 18, 10:14=A0am, Jake7 <evgen...@gmail.com> wrote: > I've built a website -http://OutputLogic.com- =A0with online tools > that generate a Verilog code for parallel CRC and Scrambler given data > width and polynomial coefficients. > > Also, there are short posts that describe an efficient parallel CRC/ > Scrambler generation algorithm for Verilog or VHDL that I've used. > > -evgeni Thatks for these tools ! How about making it a bit more interesting and adding byte enables ?! Cheers, rudiArticle: 140615
On May 19, 7:40=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > I would like to use a Spartan 3 DCM to divide a clock by 5. =A0I don't ca= re > about skew and would prefer not to connect the CLK_FB. =A0I do care very = much > about jitter. =A0I'm actually using the FPGA to output a pulse-width-modu= lated > signal, so I'm committing a total "no-no" by using it as an analogue > component! > > I've read that the DCM DLL function is actually very clean as far as phas= e > noise / spectral purity are concerned, as long as the DLL doesn't keep > swapping taps. =A0Does anyone know any sneaky non-standard tricks that wo= uld > allow me to have my divide-by-5 with tap-swapping disabled? =A0I could do= the > divide with CLBs; but I wonder if the DCM, with its dedicated routing to = the > global clock buffers, could actually be better? > The DCM is clean, but the output can only be as clean as the input. A DCM does not reduce jitter under any circumstance as its core is a variable delay line rather than a VCO. > One caveat: I need the FPGA to be totally static at certain times, to > completely eliminate digital switching noise. =A0Does enabling a DCM acti= vate > any internal free-running oscillators? > As a delay line, the DCM does not have any oscillators. However if you stop the input clock, you will need to re-lock the DCM when the clock re-starts. This can take quite a few clock cycles and requires a reset to the DCM. > Finally, I must confess that my frequency is below the specified minimum; > but I'm hoping the minimum doesn't apply if I'm only doing division. =A0A= m I > in luck? > No. The DCM will only lock if it's delay line is long enough to make up one full cycle of the input clock. You can use the DCM at lower frequencies when you only use the CLKFX outputs, but the CLKDV output requires the delay line for duty cycle control. > TIA > Andrew. If you use a global clock input pin to the FPGA and place the BUFG component near the clock pin, you could probably get as good jitter performance as with using a DCM. If you need to clean up your input clock jitter you'll need a part with a PLL in it. Try to minimise the routing delays from the final flip-flop stage in your design to the output pins (i.e. use the IOB output flop if possible). Also note that jitter is often introduced from the power supply system, so make sure your power is clean. This includes core power, where power supply variation causes variation in internal delays (hence the note about reducing output routing). It also includes Vcco which can cause changes in the switching threshold level. The clock input is especially susceptible to this when the rise and fall times are longer. Using a differential clock source will minimize this effect. HTH, GaborArticle: 140616
I agree with Sean, there is no "except" statement or so to handle this kind of issues The quickest way is to put ur buses in a process, assign them normally with (bus_1 <= bus_2; in your example) then override the "except " pins at the end or the process. put a clock in your process : process(clk) but don't use it inernally, it is just a syntax issue . Tested with Xilinx XST ! Hassen KARRAYArticle: 140617
On Wed, 20 May 2009 10:42:13 +0200, Sean Durkin wrote:
>2. Put these statements inside a process
>(doesn't matter if it's clocked or not):
>
>bus_1 <= bus_2;
>bus_1 <= (22 => pin_22, 11 => pin_11);
Not quite; the aggregate has lots of missing subscripts
and won't work. This will, though:
process ....
begin
....
bus_1 <= bus_2; -- get all the defaults
bus_1(22) <= pin_22; -- exception #1
bus_1(11) <= pin_11; -- exception #2
...
end process;
Here's another possibility, rather more VHDL syntax trouble,
but perhaps prettier and more flexible. Create a
data type that represents an "exception": a bit
number, and the std_logic value to put into it...
type exception is record
subscript: natural;
value : std_logic;
end record;
And now make an unconstrained array of them:
type exception_list is array (natural range <>) of exception;
Now you can create a function that copies one std_logic_vector
to another, providing a default but also allowing for exceptions:
function patchup
( vec: std_logic_vector -- the original vector
; diffs: exception_list -- bits to update
) return std_logic_vector
is
variable result: std_logic_vector(vec'range);
begin
result := vec; -- get most of the bits from original
for i in diffs'range loop -- scan the exceptions
result(diffs(i).subscript) := diffs(i).value;
end loop;
return result;
end;
And your copy operation might look like this:
bus_1 <= patchup( bus_2, ( (11, pin_11), (22, pin_22) ) );
Note the nested aggregate: each inner value such as (11, pin_11)
represents one "exception" record, and the outer parentheses
enclose an "exception_list" array. The array will be
numbered (0 to 1), but you don't care about that.
This should be synthesisable. I reckon that the trouble of
writing the function is well worth it if you are going to
do that sort of thing more than once. And of course the
type definitions and the function are not locked to any
specific design, so they could go in a package.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 140618gabor wrote: > > The DCM is clean, but the output can only be as clean as the > input. A DCM does not reduce jitter under any circumstance > as its core is a variable delay line rather than a VCO. > Hi Gabor, Are you sure about that? I believe the DCM only updates it's taps every now and then, in fact I think the attribute "FACTORY_JF" controls the update rate. If the input jitter was several 'taps' in amplitude, and faster than the tap update rate, perhaps the DCM would attenuate jitter. The point I'm trying to make is that a delay locked loop certainly can attenuate jitter in some circumstances, for example if the incoming jitter is more than 1 tap in amplitude. I'm not certain the Xilinx ones do, but I believe your reasoning that they don't because "its core is a variable delay line rather than a VCO" is not valid. Cheers, Syms.Article: 140619
>>> Aiken <aikenp...@gmail.com> wrote:
>>>
>>>> How can I setup for running modelsim?
> Mike Treseler wrote:
>> The editor does seem to cover syntax checking without needing vcom.
Matthew Hicks wrote:
> That's because they use their own VHDL front end.
Yes, and for that reason Aiken
might not need to hook up modelsim
to jump to syntax errors.
-- Mike Treseler
Article: 140620
luudee wrote:
> Hi All,
>
> Is there a standard/common way to specify nets as multi cycle
> path within the RTL ? In a way that it would be recognized by
> as many synthesis tools as possible ?
No, that is a synthesis timing constraint.
I can eliminate the requirement in my
code by adding a synchronous handshake
or pipeline.
-- Mike Treseler
Article: 140621"HT-Lab" <hans64@ht-lab.com> wrote in message news:W7QQl.80572$861.55894@newsfe12.ams2... > Does anybody know how to disable the CONV_INTEGER warnings in ISIM (11.1)? > > at 3000290500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: > There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been > converted to 0. > at 3000365500 ps(1), Instance /cpu_top_tb/U_12/ : Warning: CONV_INTEGER: > There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been > converted to 0. Only just guessing at the context... I would think ISIM's post-route simulation elaborator is complaining that it's forcing to '0' an uninitialized integer referenced in a math operation.Article: 140622
On May 19, 2:39=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > Dear Vipul, > > Seems like you are always going to get > some sort of timing issue since the rst > signal and the SDA_IN signal are async. > > Propagating the STARTOP signal forward > to the STOPOP reset circuitry also seems > like a bad idea for some reason I can't > quite articulate, except for an idea that > the start and stop signals should be > symetrical. > > If you have a system clock, I would suggest > that you use registers at your SDA and SCL > inputs right at the IOs. Then use old values > of SDA and SCL to calculate your START and > STOP signals: > > start_stop_proc:process(clk) > begin > if(clk'event and clk=3D'1')then > =A0 STARTOP<=3D'0'; > =A0 STOPOP<=3D'0'; > =A0 SDA_1<=3DSDA_IN; > =A0 SDA_2<=3DSDA_1; > =A0 SCL_1<=3DSCL_IN; > =A0 if( SDA_1=3D'0' and SDA_2=3D'1' and SCL_1=3D'1')then > =A0 =A0STARTOP<=3D'1'; > =A0 end if; > =A0 if( SDA_1=3D'1' and SDA_2=3D'0' and SCL_1=3D'1')then > =A0 =A0STOPOP<=3D'1'; > =A0 end if; > end if; > end process; > > This should be very clean as long as your system clock > and timing is OK. And it give clean oneshot reset signals > for your address and data registers. > > Now if you are trying to run this from the SCL clock, perhaps > just taking the rst out of your process may work, or putting > it in the synchonous part of the block may work, and clean > up the code so that the both signals look symetrical: > > start_proc:process(SDA_IN) > begin > =A0if(SDA_IN'event and SDA_IN=3D'0')then > =A0 if(rst=3D'1')then > =A0 =A0STARTOP<=3D'0'; > =A0 elsif(scl=3D'1')then > =A0 =A0STARTOP<=3D'1'; > =A0 else > =A0 =A0STARTOP<=3D'0'; > =A0 end if; > =A0end if; > end process; > > stop_proc:process(SDA_IN) > begin > =A0if(SDA_IN'event and SDA_IN=3D'1')then > =A0 if(rst=3D'1')then > =A0 =A0STOPOP<=3D'0'; > =A0 elsif(scl=3D'1')then > =A0 =A0STOPOP<=3D'1'; > =A0 else > =A0 =A0STOPOP<=3D'0'; > =A0 end if; > =A0end if; > end process; > > Then these signals need to be synched with scl clock > signal before you start messing with your data registers. > And you have to look for their edges since the SDA signal > can drop and not come up if it's sending a zero datum. > > Using a system clock is a lot easier. > > I haven't ever done a I2C slave so you might get better > answers elsewhere. Good luck. > > Brad Smallridge > AiVision > > "VIPS" <thevipulsi...@gmail.com> wrote in message > > news:35bbb41b-ce32-4cb6-868e-a459b10d05a7@s28g2000vbp.googlegroups.com... > > > Hi all > > > I am implementing the I2C Slave and I am using the I2C clock SCL for > > detecting the start and stop condition . I am detecting the start and > > stop successfully in simulation but i am not able to do the same in > > the post synthesis scenario. More so I am getting a setup time > > violation for the same in the timing analysis . I am running the I2C > > at a very slow speed of 100KHz. > > > The code is below > > > process (SDA_IN, START_RST,rst) > > =A0 begin > > =A0 =A0 if rst =3D'1' then > > =A0 =A0 =A0 =A0STARTOP <=3D'0'; > > =A0 =A0-- elsif (START_RST =3D '1') then > > =A0 =A0-- =A0 =A0STARTOP <=3D '0'; > > =A0 =A0 elsif (SDA_IN'event and SDA_IN =3D '0') then > > =A0 =A0 =A0 STARTOP <=3D scl; > > =A0 =A0 end if; > > =A0 end process; > > -----------------------------------------------------------------------= ------- > > -- stop condition detection > > process (RST, SCL, SDA_IN, STARTOP) > > begin > > =A0 =A0if RST =3D '1' or SCL =3D '0' or STARTOP=3D'1' then > > =A0 =A0 =A0 =A0STOPOP <=3D '0'; > > =A0 elsif =A0SDA_IN =3D '1' and SDA_IN'event then > > =A0 =A0 =A0 if SCL =3D '1' then > > =A0 =A0 =A0 =A0 =A0 =A0 STOPOP <=3D '1'; > > =A0 =A0 =A0 =A0end if ; > > > =A0 end if; > > =A0end process; > > > Can =A0any one give me a reliable way to detect the start and stop > > condition that =A0the synthesis tool doesnot give any setup time > > violation. I am not using a high clock for sampling as the requirement > > is to use the SCL only. May be to save board resourse and space. > > > Help will be appreciated. I am using Altera max II CPLD and the > > synthesis tool is quartus 9.0 > > > Thanks > > > Vipul Dear Brad Thanks for your reply and for your time. Your suggestion is very logical and I tried to implement it . The tool still gives an error in the setup time though the slack reduced considerably . I will try to work around it . You have shown a good way to deal with it by making the two process look symmetrical. Thanks once again for your valuable time VipulArticle: 140623
hi all, im planning to implement barcode scanning using a CMOS sensor. The processing needs to happen inside a FPGA, so im evaluating my options in choosing a proper soft processor for the task. these are my requirements. 1) open source and need to be able to be used in commercial products 2) need to have good documentation and support tools (toolchain, simulators, emulators) 3) robust and stable 4) need to use in an xilinx spartan 3 device with 400K gates. i know about processors OpenRISC 1000, NIOS 2 and LEON 2, but not sure how good they are with regard to my requirements, specially the (2), (3) and (4) above. Please help. in addition, i like to here about microblaze and its licensing fees structure thanksArticle: 140624
On May 18, 5:06=A0pm, DH <dh1...@gmail.com> wrote: > Hi, thanks to everyone that replied to this post! I really appreciate > it. > > To Antti: Thanks, the YARI processor looks like a good processor. Why thank you :-) > Update: After some discussion at school, I'm going > to use the CoWare processor designer at school to make my processor > now, it provides a reference 5 stage pipelined RISC core with > bypassing done already, it's not MIPS, but there's compiler/assembler/ > linker available. The best thing about this tool (though may be hard > to do, we'll see) is that you can use it to generate the tool chain > along with the processor RTL code. I will fall back to good old VHDL > if this tool doesn't deliver, thanks to everyone that replied to this > post! Good luck with that. If you change your mind and want to give YARI a spin, I can help you. It might be useful to know how your core will be used. Fx. will it be backed up with external memory or used as an embedded processor using only the FPGA provided memory blocks? Which parts of the processor are you planning on experimenting with? Cheers, Tommy
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